Search dblp for Publications

export results for "Microarchitecture Level Interconnect Modeling Considering Layout Optimization."

 download as .bib file

@article{DBLP:journals/jolpe/LiaoH05,
  author       = {Weiping Liao and
                  Lei He},
  title        = {Microarchitecture Level Interconnect Modeling Considering Layout Optimization},
  journal      = {J. Low Power Electron.},
  volume       = {1},
  number       = {3},
  pages        = {297--308},
  year         = {2005},
  url          = {https://doi.org/10.1166/jolpe.2005.036},
  doi          = {10.1166/JOLPE.2005.036},
  timestamp    = {Mon, 13 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/jolpe/LiaoH05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}