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@inproceedings{DBLP:conf/isscc/RhoTKSBINMCSPPY17,
  author       = {Kwangmyoung Rho and
                  Kenji Tsuchida and
                  Dongkeun Kim and
                  Yutaka Shirai and
                  Jihyae Bae and
                  Tsuneo Inaba and
                  Hiromi Noro and
                  Hyunin Moon and
                  Sungwoong Chung and
                  Kazumasa Sunouchi and
                  Jinwon Park and
                  Kiseon Park and
                  Akihito Yamamoto and
                  Seoungju Chung and
                  Hyeongon Kim and
                  Hisato Oyamatsu and
                  Jonghoon Oh},
  title        = {23.5 {A} 4Gb {LPDDR2} {STT-MRAM} with compact 9F2 1T1MTJ cell and
                  hierarchical bitline architecture},
  booktitle    = {2017 {IEEE} International Solid-State Circuits Conference, {ISSCC}
                  2017, San Francisco, CA, USA, February 5-9, 2017},
  pages        = {396--397},
  publisher    = {{IEEE}},
  year         = {2017},
  url          = {https://doi.org/10.1109/ISSCC.2017.7870428},
  doi          = {10.1109/ISSCC.2017.7870428},
  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/RhoTKSBINMCSPPY17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/TakahashiAABCCCCGGIJKMMNNNPRSTTWY08,
  author       = {Osamu Takahashi and
                  Chad Adams and
                  D. Ault and
                  Erwin Behnen and
                  O. Chiang and
                  Scott R. Cottier and
                  Paula K. Coulman and
                  James Culp and
                  Gilles Gervais and
                  M. S. Gray and
                  Y. Itaka and
                  C. J. Johnson and
                  Fumihiro Kono and
                  L. Maurice and
                  Kevin W. McCullen and
                  Lam Nguyen and
                  Y. Nishino and
                  Hiromi Noro and
                  J{\"{u}}rgen Pille and
                  Mack W. Riley and
                  M. Shen and
                  Chiaki Takano and
                  Shunsako Tokito and
                  Tina Wagner and
                  Hiroshi Yoshihara},
  title        = {Migration of Cell Broadband Engine from 65nm {SOI} to 45nm {SOI}},
  booktitle    = {2008 {IEEE} International Solid-State Circuits Conference, {ISSCC}
                  2008, Digest of Technical Papers, San Francisco, CA, USA, February
                  3-7, 2008},
  pages        = {86--87},
  publisher    = {{IEEE}},
  year         = {2008},
  url          = {https://doi.org/10.1109/ISSCC.2008.4523069},
  doi          = {10.1109/ISSCC.2008.4523069},
  timestamp    = {Sun, 06 Oct 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/TakahashiAABCCCCGGIJKMMNNNPRSTTWY08.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/ibmrd/FlachsADHGKLLLLMOMTHKMNOPSYHWYBPTI07,
  author       = {Brian K. Flachs and
                  Shigehiro Asano and
                  Sang H. Dhong and
                  H. Peter Hofstee and
                  Gilles Gervais and
                  Roy Kim and
                  Tien Le and
                  Peichun Liu and
                  Jens Leenstra and
                  John S. Liberty and
                  Brad W. Michael and
                  Hwa{-}Joon Oh and
                  Silvia M. M{\"{u}}ller and
                  Osamu Takahashi and
                  Koji Hirairi and
                  Atsushi Kawasumi and
                  Hiroaki Murakami and
                  Hiromi Noro and
                  Shoji Onishi and
                  Juergen Pille and
                  Joel Silberman and
                  Suksoon Yong and
                  Akiyuki Hatakeyama and
                  Yukio Watanabe and
                  Naoka Yano and
                  Daniel A. Brokenshire and
                  Mohammad Peyravian and
                  VanDung To and
                  Eiji Iwata},
  title        = {Microarchitecture and implementation of the synergistic processor
                  in 65-nm and 90-nm {SOI}},
  journal      = {{IBM} J. Res. Dev.},
  volume       = {51},
  number       = {5},
  pages        = {529--544},
  year         = {2007},
  url          = {https://doi.org/10.1147/rd.515.0529},
  doi          = {10.1147/RD.515.0529},
  timestamp    = {Fri, 13 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/ibmrd/FlachsADHGKLLLLMOMTHKMNOPSYHWYBPTI07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/iccad/TakahashiCCDFHKMNOOPS05,
  author       = {Osamu Takahashi and
                  Russ Cook and
                  Scott R. Cottier and
                  Sang H. Dhong and
                  Brian K. Flachs and
                  Koji Hirairi and
                  Atsushi Kawasumi and
                  Hiroaki Murakami and
                  Hiromi Noro and
                  Hwa{-}Joon Oh and
                  S. Onish and
                  Juergen Pille and
                  Joel Silberman},
  title        = {The circuit design of the synergistic processor element of a {CELL}
                  processor},
  booktitle    = {2005 International Conference on Computer-Aided Design, {ICCAD} 2005,
                  San Jose, CA, USA, November 6-10, 2005},
  pages        = {111--117},
  publisher    = {{IEEE} Computer Society},
  year         = {2005},
  url          = {https://doi.org/10.1109/ICCAD.2005.1560049},
  doi          = {10.1109/ICCAD.2005.1560049},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/iccad/TakahashiCCDFHKMNOOPS05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}