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@inproceedings{DBLP:conf/dft/GhaidaZ07,
  author       = {Rani S. Ghaida and
                  Payman Zarkesh{-}Ha},
  editor       = {Cristiana Bolchini and
                  Yong{-}Bin Kim and
                  Adelio Salsano and
                  Nur A. Touba},
  title        = {Estimation of Electromigration-Aggravating Narrow Interconnects Using
                  a Layout Sensitivity Model},
  booktitle    = {22nd {IEEE} International Symposium on Defect and Fault-Tolerance
                  in {VLSI} Systems {(DFT} 2007), 26-28 September 2007, Rome, Italy},
  pages        = {59--67},
  publisher    = {{IEEE} Computer Society},
  year         = {2007},
  url          = {https://doi.org/10.1109/DFT.2007.12},
  doi          = {10.1109/DFT.2007.12},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/dft/GhaidaZ07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

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