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@inproceedings{DBLP:conf/essderc/BaoYRCBVBCRDRMTVTW14,
  author       = {Trong Huynh Bao and
                  Dmitry Yakimets and
                  Julien Ryckaert and
                  Ivan Ciofi and
                  Rogier Baert and
                  Anabela Veloso and
                  J{\"{u}}rgen B{\"{o}}mmels and
                  Nadine Collaert and
                  Philippe Roussel and
                  S. Demuynck and
                  Praveen Raghavan and
                  Abdelkarim Mercha and
                  Zsolt Tokei and
                  Diederik Verkest and
                  Aaron Thean and
                  Piet Wambacq},
  title        = {Circuit and process co-design with vertical gate-all-around nanowire
                  {FET} technology to extend {CMOS} scaling for 5nm and beyond technologies},
  booktitle    = {44th European Solid State Device Research Conference, {ESSDERC} 2014,
                  Venice Lido, Italy, September 22-26, 2014},
  pages        = {102--105},
  publisher    = {{IEEE}},
  year         = {2014},
  url          = {https://doi.org/10.1109/ESSDERC.2014.6948768},
  doi          = {10.1109/ESSDERC.2014.6948768},
  timestamp    = {Wed, 16 Oct 2019 14:14:50 +0200},
  biburl       = {https://dblp.org/rec/conf/essderc/BaoYRCBVBCRDRMTVTW14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

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