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@inproceedings{DBLP:conf/essderc/ElbazCLRBNVBUMP23,
author = {G. Elbaz and
Mika{\"{e}}l Cass{\'{e}} and
V. Labracherie and
G. Roussely and
Benoit Bertrand and
Heimanu Niebojewski and
Maud Vinet and
F. Balestro and
Matias Urdampilleta and
Tristan Meunier and
Bruna Cardoso Paz},
title = {Transport characterization of CMOS-based devices fabricated with isotopically-enriched
\({}^{\mbox{28}}\)Si for spin qubit applications},
booktitle = {53rd {IEEE} European Solid-State Device Research Conference, {ESSDERC}
2023, Lisbon, Portugal, September 11-14, 2023},
pages = {5--8},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ESSDERC59256.2023.10268523},
doi = {10.1109/ESSDERC59256.2023.10268523},
timestamp = {Mon, 09 Oct 2023 15:43:28 +0200},
biburl = {https://dblp.org/rec/conf/essderc/ElbazCLRBNVBUMP23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsit/NiebojewskiBNBP22,
author = {Heimanu Niebojewski and
Benoit Bertrand and
Etienne Nowak and
Thomas Bedecarrats and
Bruna Cardoso Paz and
Lauriane Contamin and
Pierre{-}Andr{\'{e}} Mortemousque and
V. Labracherie and
L. Brevard and
H. Sahin and
Jean Charbonnier and
C. Thomas and
Myriam Assous and
Mika{\"{e}}l Cass{\'{e}} and
Matias Urdampilleta and
Yann{-}Michel Niquet and
Fran{\c{c}}ois Perruchot and
Fred Gaillard and
Silvano De Franceschi and
Tristan Meunier and
Maud Vinet},
title = {Specificities of linear Si {QD} arrays integration and characterization},
booktitle = {{IEEE} Symposium on {VLSI} Technology and Circuits {(VLSI} Technology
and Circuits 2022), Honolulu, HI, USA, June 12-17, 2022},
pages = {415--416},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830352},
doi = {10.1109/VLSITECHNOLOGYANDCIR46769.2022.9830352},
timestamp = {Mon, 08 Jul 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsit/NiebojewskiBNBP22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/drc/HutinBNMCBJMUNF21,
author = {Louis Hutin and
Benoit Bertrand and
Heimanu Niebojewski and
Pierre{-}Andr{\'{e}} Mortemousque and
Mika{\"{e}}l Cass{\'{e}} and
G{\'{e}}rard Billiot and
Xavier Jehl and
Romain Maurand and
Matias Urdampilleta and
Yann{-}Michel Niquet and
S. De Franceschi and
Tristan Meunier and
Maud Vinet},
title = {{MOS} technology for quantum computing: recent progress and perspectives
for scaling up},
booktitle = {Device Research Conference, {DRC} 2021, Santa Barbara, CA, USA, June
20-23, 2021},
pages = {1--2},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/DRC52342.2021.9467200},
doi = {10.1109/DRC52342.2021.9467200},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/drc/HutinBNMCBJMUNF21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/eups/MansoGCWBPS17,
author = {Marco Manso and
Barbara Guerra and
Bertrand Casse and
James Winterbottom and
Mihai Buf and
Cristian Patachia and
Vlad Sorici},
editor = {Filipa Soares Borrego and
Joaquim Mendes and
Paulo Novais and
Ana Paiva},
title = {Next Generation Emergency Services - The Transformation Launched by
the {NEXES} Action},
booktitle = {European Project Space on Networks, Systems and Technologies, Porto,
Portugal, February 19-1, 2017},
publisher = {SciTePress},
year = {2017},
url = {https://doi.org/10.5220/0007902601060133},
doi = {10.5220/0007902601060133},
timestamp = {Tue, 11 Jan 2022 08:08:22 +0100},
biburl = {https://dblp.org/rec/conf/eups/MansoGCWBPS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/CasseauG12,
author = {Emmanuel Casseau and
Bertrand Le Gal},
title = {Design of multi-mode application-specific cores based on high-level
synthesis},
journal = {Integr.},
volume = {45},
number = {1},
pages = {9--21},
year = {2012},
url = {https://doi.org/10.1016/j.vlsi.2011.07.003},
doi = {10.1016/J.VLSI.2011.07.003},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/CasseauG12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ejasp/GalC11,
author = {Bertrand Le Gal and
Emmanuel Casseau},
title = {Latency-Sensitive High-Level Synthesis for Multiple Word-Length {DSP}
Design},
journal = {{EURASIP} J. Adv. Signal Process.},
volume = {2011},
year = {2011},
url = {https://doi.org/10.1155/2011/927670},
doi = {10.1155/2011/927670},
timestamp = {Thu, 12 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ejasp/GalC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsisp/GalC11,
author = {Bertrand Le Gal and
Emmanuel Casseau},
title = {Word-Length Aware {DSP} Hardware Design Flow Based on High-Level Synthesis},
journal = {J. Signal Process. Syst.},
volume = {62},
number = {3},
pages = {341--357},
year = {2011},
url = {https://doi.org/10.1007/s11265-010-0467-8},
doi = {10.1007/S11265-010-0467-8},
timestamp = {Thu, 12 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsisp/GalC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sies/LefftzBCCCMMMPV10,
author = {Vincent Lefftz and
Jean Bertrand and
Hugues Cass{\'{e}} and
Christophe Clienti and
Philippe Coussy and
Laurent Maillet{-}Contoz and
Philippe Mercier and
Pierre Moreau and
Laurence Pierre and
Emmanuel Vaumorin},
title = {A Design Flow for Critical Embedded Systems},
booktitle = {{IEEE} Fifth International Symposium on Industrial Embedded Systems,
{SIES} 2010, University of Trento, Italy, July 7-9, 2010},
pages = {229--233},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/SIES.2010.5551393},
doi = {10.1109/SIES.2010.5551393},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/sies/LefftzBCCCMMMPV10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/eusipco/GalC09,
author = {Bertrand Le Gal and
Emmanuel Casseau},
title = {Automated multimode system design for high performance {DSP} applications},
booktitle = {17th European Signal Processing Conference, {EUSIPCO} 2009, Glasgow,
Scotland, UK, August 24-28, 2009},
pages = {1289--1293},
publisher = {{IEEE}},
year = {2009},
url = {https://ieeexplore.ieee.org/document/7077444/},
timestamp = {Mon, 09 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/eusipco/GalC09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/samos/CasseauG09,
author = {Emmanuel Casseau and
Bertrand Le Gal},
editor = {Walid A. Najjar and
Michael J. Schulte},
title = {High-level synthesis for the design of FPGA-based signal processing
systems},
booktitle = {Proceedings of the 2009 International Conference on Embedded Computer
Systems: Architectures, Modeling and Simulation {(IC-SAMOS} 2009),
Samos, Greece, July 20-23, 2009},
pages = {25--32},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/ICSAMOS.2009.5289238},
doi = {10.1109/ICSAMOS.2009.5289238},
timestamp = {Thu, 25 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/samos/CasseauG09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tsi/GalCA08,
author = {Bertrand Le Gal and
Emmanuel Casseau and
Caaliph Andriamisaina},
title = {Synth{\`{e}}se de haut niveau tenant compte de la dynamique des traitements.
Analyse de la largeur des donn{\'{e}}es d'applications du {TDSI}
et gestion de cette information lors de la synth{\`{e}}se de haut
niveau},
journal = {Tech. Sci. Informatiques},
volume = {27},
number = {9-10},
pages = {1129--1154},
year = {2008},
url = {https://doi.org/10.3166/tsi.27.1129-1154},
doi = {10.3166/TSI.27.1129-1154},
timestamp = {Wed, 24 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tsi/GalCA08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GalCH08,
author = {Bertrand Le Gal and
Emmanuel Casseau and
Sylvain Huet},
title = {Dynamic Memory Access Management for High-Performance {DSP} Applications
Using High-Level Synthesis},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {16},
number = {11},
pages = {1454--1464},
year = {2008},
url = {https://doi.org/10.1109/TVLSI.2008.2000821},
doi = {10.1109/TVLSI.2008.2000821},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/GalCH08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/GalBKC07,
author = {Bertrand Le Gal and
Lilian Bossuet and
Shafqat Khan and
Emmanuel Casseau},
title = {{HLS} design flow for the synthesis of multimode systems under multiple
constraints},
booktitle = {14th {IEEE} International Conference on Electronics, Circuits, and
Systems, {ICECS} 2007, Marrakech, Morocco, December 11-14, 2007},
pages = {314--317},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1109/ICECS.2007.4510993},
doi = {10.1109/ICECS.2007.4510993},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/icecsys/GalBKC07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/GalC06,
author = {Bertrand Le Gal and
Emmanuel Casseau},
title = {{IP} Generation Targeting Multiple Bit-Width Standards},
booktitle = {13th {IEEE} International Conference on Electronics, Circuits, and
Systems, {ICECS} 2006, Nice, France, December 10-13, 2006},
pages = {784--787},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/ICECS.2006.379906},
doi = {10.1109/ICECS.2006.379906},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/icecsys/GalC06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sips/AndriamisainaGC06,
author = {Caaliph Andriamisaina and
Bertrand Le Gal and
Emmanuel Casseau},
title = {Bit-Width Optimizations for High-Level Synthesis of Digital Signal
Processing Systems},
booktitle = {Proceedings of the {IEEE} Workshop on Signal Processing Systems, SiPS
2006, Proceedings, October 2-4, 2006, Banff, Alberta, Canada},
pages = {280--285},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/SIPS.2006.352595},
doi = {10.1109/SIPS.2006.352595},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/sips/AndriamisainaGC06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/socc/GalAC06,
author = {Bertrand Le Gal and
Caaliph Andriamisaina and
Emmanuel Casseau},
title = {Bit-Width Aware High-Level Synthesis for Digital Signal Processing
Systems},
booktitle = {2006 {IEEE} International {SOC} Conference, Austin, Texas, USA, September
24-27, 2006},
pages = {175--178},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/SOCC.2006.283875},
doi = {10.1109/SOCC.2006.283875},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/socc/GalAC06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/AbdelliBCFJKGH05,
author = {Nabil Abdelli and
Pierre Bomel and
Emmanuel Casseau and
Anne{-}Marie Fouilliart and
Christophe J{\'{e}}go and
Philippe Kajfasz and
Bertrand Le Gal and
Nathalie Le Heno},
title = {Hardware Virtual Components Compliant with Communication System Standards},
booktitle = {Eighth Euromicro Symposium on Digital Systems Design {(DSD} 2005),
30 August - 3 September 2005, Porto, Portugal},
pages = {88--95},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/DSD.2005.44},
doi = {10.1109/DSD.2005.44},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dsd/AbdelliBCFJKGH05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/eusipco/CasseauGBJH005,
author = {Emmanuel Casseau and
Bertrand Le Gal and
Pierre Bomel and
Christophe J{\'{e}}go and
Sylvain Huet and
Eric Martin},
title = {C-based rapid prototyping for digital signal processing},
booktitle = {13th European Signal Processing Conference, {EUSIPCO} 2005, Antalya,
Turkey, September 4-8, 2005},
pages = {1--4},
publisher = {{IEEE}},
year = {2005},
url = {https://ieeexplore.ieee.org/document/7077970/},
timestamp = {Mon, 09 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/eusipco/CasseauGBJH005.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/eusipco/GalC005,
author = {Bertrand Le Gal and
Emmanuel Casseau and
Eric Martin},
title = {Pipelined memory controllers for {DSP} real-time applications handling
unpredictable data accesses},
booktitle = {13th European Signal Processing Conference, {EUSIPCO} 2005, Antalya,
Turkey, September 4-8, 2005},
pages = {1--4},
publisher = {{IEEE}},
year = {2005},
url = {https://ieeexplore.ieee.org/document/7078210/},
timestamp = {Mon, 09 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/eusipco/GalC005.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/GalCHM05,
author = {Bertrand Le Gal and
Emmanuel Casseau and
Sylvain Huet and
Eric Martin},
title = {Pipelined Memory Controllers for {DSP} Applications Handling Unpredictable
Data Accesses},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {268--269},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.56},
doi = {10.1109/ISVLSI.2005.56},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/GalCHM05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/CasseauGJHM04,
author = {Emmanuel Casseau and
Bertrand Le Gal and
Christophe J{\'{e}}go and
Nathalie Le Heno and
Eric Martin},
title = {Reed-Solomon behavioral virtual component for communication systems},
booktitle = {Proceedings of the 2004 International Symposium on Circuits and Systems,
{ISCAS} 2004, Vancouver, BC, Canada, May 23-26, 2004},
pages = {173--176},
publisher = {{IEEE}},
year = {2004},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/CasseauGJHM04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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