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@inproceedings{DBLP:conf/islped/KimCABS12,
  author       = {Daeyeon Kim and
                  Vikas Chandra and
                  Robert C. Aitken and
                  David T. Blaauw and
                  Dennis Sylvester},
  editor       = {Naresh R. Shanbhag and
                  Massimo Poncino and
                  Pai H. Chou and
                  Ajith Amerasekera},
  title        = {An adaptive write word-line pulse width and voltage modulation architecture
                  for bit-interleaved 8T SRAMs},
  booktitle    = {International Symposium on Low Power Electronics and Design, ISLPED'12,
                  Redondo Beach, CA, {USA} - July 30 - August 01, 2012},
  pages        = {91--96},
  publisher    = {{ACM}},
  year         = {2012},
  url          = {https://doi.org/10.1145/2333660.2333684},
  doi          = {10.1145/2333660.2333684},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/islped/KimCABS12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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