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@inproceedings{DBLP:conf/vlsic/PangRWSFM12,
  author       = {Liang{-}Teck Pang and
                  Phillip J. Restle and
                  Matthew R. Wordeman and
                  Joel A. Silberman and
                  Robert L. Franch and
                  Gary W. Maier},
  title        = {A shorted global clock design for multi-GHz 3D stacked chips},
  booktitle    = {Symposium on {VLSI} Circuits, {VLSIC} 2012, Honolulu, HI, USA, June
                  13-15, 2012},
  pages        = {170--171},
  publisher    = {{IEEE}},
  year         = {2012},
  url          = {https://doi.org/10.1109/VLSIC.2012.6243844},
  doi          = {10.1109/VLSIC.2012.6243844},
  timestamp    = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsic/PangRWSFM12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

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