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export results for "Speeding Up Sequential Simulated Annealing by Parallelization."
@inproceedings{DBLP:conf/parelec/Czech06, author = {Zbigniew J. Czech}, title = {Speeding Up Sequential Simulated Annealing by Parallelization}, booktitle = {Fifth International Conference on Parallel Computing in Electrical Engineering {(PARELEC} 2006), 13-17 September 2006, Bialystok, Poland}, pages = {349--356}, year = {2006}, crossref = {DBLP:conf/parelec/2006}, url = {https://doi.org/10.1109/PARELEC.2006.74}, doi = {10.1109/PARELEC.2006.74}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/parelec/Czech06.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@proceedings{DBLP:conf/parelec/2006, title = {Fifth International Conference on Parallel Computing in Electrical Engineering {(PARELEC} 2006), 13-17 September 2006, Bialystok, Poland}, publisher = {{IEEE} Computer Society}, year = {2006}, url = {https://ieeexplore.ieee.org/xpl/conhome/11156/proceeding}, isbn = {0-7695-2554-7}, timestamp = {Sat, 17 Aug 2024 14:13:08 +0200}, biburl = {https://dblp.org/rec/conf/parelec/2006.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
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