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@inproceedings{DBLP:conf/date/MoreiraYCCZKQKK20,
  author       = {Orlando Moreira and
                  Amirreza Yousefzadeh and
                  Fabian Chersi and
                  Gokturk Cinserin and
                  Rik{-}Jan Zwartenkot and
                  Ajay Kapoor and
                  Peng Qiao and
                  Peter Kievits and
                  Mina A. Khoei and
                  Louis Rouillard and
                  Aimee Ferouge and
                  Jonathan Tapson and
                  Ashoka Visweswara},
  title        = {NeuronFlow: a neuromorphic processor architecture for Live {AI} applications},
  booktitle    = {{DATE}},
  pages        = {840--845},
  publisher    = {{IEEE}},
  year         = {2020}
}

@article{DBLP:journals/mj/KakoeeSPB12,
  author       = {Mohammad Reza Kakoee and
                  Ashoka Visweswara Sathanur and
                  Antonio Pullini and
                  Luca Benini},
  title        = {Row-based {FBB:} {A} design-time optimization for post-silicon tunable
                  circuits},
  journal      = {Microelectron. J.},
  volume       = {43},
  number       = {7},
  pages        = {456--465},
  year         = {2012}
}

@article{DBLP:journals/tvlsi/SathanurBMMP11,
  author       = {Ashoka Visweswara Sathanur and
                  Luca Benini and
                  Alberto Macii and
                  Enrico Macii and
                  Massimo Poncino},
  title        = {Fast Computation of Discharge Current Upper Bounds for Clustered Power
                  Gating},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {19},
  number       = {1},
  pages        = {146--151},
  year         = {2011}
}

@article{DBLP:journals/tvlsi/SathanurBMMP11a,
  author       = {Ashoka Visweswara Sathanur and
                  Luca Benini and
                  Alberto Macii and
                  Enrico Macii and
                  Massimo Poncino},
  title        = {Row-Based Power-Gating: {A} Novel Sleep Transistor Insertion Methodology
                  for Leakage Power Optimization in Nanometer {CMOS} Circuits},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {19},
  number       = {3},
  pages        = {469--482},
  year         = {2011}
}

@inproceedings{DBLP:conf/vlsi/ArtesASHC11,
  author       = {Antonio Art{\'{e}}s and
                  Jos{\'{e}} Luis Ayala and
                  Ashoka Visweswara Sathanur and
                  Jos Huisken and
                  Francky Catthoor},
  title        = {Run-time self-tuning banked loop buffer architecture for power optimization
                  of dynamic workload applications},
  booktitle    = {VLSI-SoC},
  pages        = {136--141},
  publisher    = {{IEEE}},
  year         = {2011}
}

@inproceedings{DBLP:conf/icecsys/SathanurHSG10,
  author       = {Ashoka Visweswara Sathanur and
                  Jos Huisken and
                  Jan Stuyt and
                  Harmke de Groot},
  title        = {Activity profile driven simultaneous vt assignment and power switch
                  sizing for leakage power minimization in nanometer {CMOS} designs},
  booktitle    = {{ICECS}},
  pages        = {519--522},
  publisher    = {{IEEE}},
  year         = {2010}
}

@inproceedings{DBLP:conf/islped/KakoeeSPHB10,
  author       = {Mohammad Reza Kakoee and
                  Ashoka Visweswara Sathanur and
                  Antonio Pullini and
                  Jos Huisken and
                  Luca Benini},
  title        = {Automatic synthesis of near-threshold circuits with fine-grained performance
                  tunability},
  booktitle    = {{ISLPED}},
  pages        = {401--406},
  publisher    = {{ACM}},
  year         = {2010}
}

@article{DBLP:journals/jolpe/SathanurBMMP09,
  author       = {Ashoka Visweswara Sathanur and
                  Luca Benini and
                  Alberto Macii and
                  Enrico Macii and
                  Massimo Poncino},
  title        = {Exploiting Temporal Discharge Current Information to Improve the Efficiency
                  of Clustered Power-Gating},
  journal      = {J. Low Power Electron.},
  volume       = {5},
  number       = {1},
  pages        = {113--121},
  year         = {2009}
}

@inproceedings{DBLP:conf/date/SathanurPBMM09,
  author       = {Ashoka Visweswara Sathanur and
                  Antonio Pullini and
                  Luca Benini and
                  Giovanni De Micheli and
                  Enrico Macii},
  title        = {Physically clustered forward body biasing for variability compensation
                  in nanometer {CMOS} design},
  booktitle    = {{DATE}},
  pages        = {154--159},
  publisher    = {{IEEE}},
  year         = {2009}
}

@article{DBLP:journals/integration/ChakrabortyDSSMMP08,
  author       = {Ashutosh Chakraborty and
                  Karthik Duraisami and
                  Ashoka Visweswara Sathanur and
                  Prassanna Sithambaram and
                  Alberto Macii and
                  Enrico Macii and
                  Massimo Poncino},
  title        = {Implementation of a thermal management unit for canceling temperature-dependent
                  clock skew variations},
  journal      = {Integr.},
  volume       = {41},
  number       = {1},
  pages        = {2--8},
  year         = {2008}
}

@article{DBLP:journals/jolpe/CalimeraDSSBMMP08,
  author       = {Andrea Calimera and
                  Karthik Duraisami and
                  Ashoka Visweswara Sathanur and
                  Prassanna Sithambaram and
                  R. Iris Bahar and
                  Alberto Macii and
                  Enrico Macii and
                  Massimo Poncino},
  title        = {Thermal-Aware Design Techniques for Nanometer {CMOS} Circuits},
  journal      = {J. Low Power Electron.},
  volume       = {4},
  number       = {3},
  pages        = {374--384},
  year         = {2008}
}

@article{DBLP:journals/tvlsi/ChakrabortyDSSBMMP08,
  author       = {Ashutosh Chakraborty and
                  Karthik Duraisami and
                  Ashoka Visweswara Sathanur and
                  Prassanna Sithambaram and
                  Luca Benini and
                  Alberto Macii and
                  Enrico Macii and
                  Massimo Poncino},
  title        = {Dynamic Thermal Clock Skew Compensation Using Tunable Delay Buffers},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {16},
  number       = {6},
  pages        = {639--649},
  year         = {2008}
}

@inproceedings{DBLP:conf/date/SathanurPBMMP08,
  author       = {Ashoka Visweswara Sathanur and
                  Antonio Pullini and
                  Luca Benini and
                  Alberto Macii and
                  Enrico Macii and
                  Massimo Poncino},
  title        = {A Scalable Algorithmic Framework for Row-Based Power-Gating},
  booktitle    = {{DATE}},
  pages        = {379--384},
  publisher    = {{ACM}},
  year         = {2008}
}

@inproceedings{DBLP:conf/glvlsi/SathanurPBMMP08,
  author       = {Ashoka Visweswara Sathanur and
                  Antonio Pullini and
                  Luca Benini and
                  Alberto Macii and
                  Enrico Macii and
                  Massimo Poncino},
  title        = {Optimal sleep transistor synthesis under timing and area constraints},
  booktitle    = {{ACM} Great Lakes Symposium on {VLSI}},
  pages        = {177--182},
  publisher    = {{ACM}},
  year         = {2008}
}

@inproceedings{DBLP:conf/iscas/SathanurCPBMMP08,
  author       = {Ashoka Visweswara Sathanur and
                  Andrea Calimera and
                  Antonio Pullini and
                  Luca Benini and
                  Alberto Macii and
                  Enrico Macii and
                  Massimo Poncino},
  title        = {On quantifying the figures of merit of power-gating for leakage power
                  minimization in nanometer {CMOS} circuits},
  booktitle    = {{ISCAS}},
  pages        = {2761--2764},
  publisher    = {{IEEE}},
  year         = {2008}
}

@inproceedings{DBLP:conf/islped/SathanurBMMP08,
  author       = {Ashoka Visweswara Sathanur and
                  Luca Benini and
                  Alberto Macii and
                  Enrico Macii and
                  Massimo Poncino},
  title        = {Multiple power-gating domain (multi-VGND) architecture for improved
                  leakage power reduction},
  booktitle    = {{ISLPED}},
  pages        = {51--56},
  publisher    = {{ACM}},
  year         = {2008}
}

@inproceedings{DBLP:conf/patmos/SathanurBMMP08,
  author       = {Ashoka Visweswara Sathanur and
                  Luca Benini and
                  Alberto Macii and
                  Enrico Macii and
                  Massimo Poncino},
  title        = {Temporal Discharge Current Driven Clustering for Improved Leakage
                  Power Reduction in Row-Based Power-Gating},
  booktitle    = {{PATMOS}},
  series       = {Lecture Notes in Computer Science},
  volume       = {5349},
  pages        = {42--51},
  publisher    = {Springer},
  year         = {2008}
}

@inproceedings{DBLP:conf/date/SathanurCBMMP07,
  author       = {Ashoka Visweswara Sathanur and
                  Andrea Calimera and
                  Luca Benini and
                  Alberto Macii and
                  Enrico Macii and
                  Massimo Poncino},
  title        = {Interactive presentation: Efficient computation of discharge current
                  upper bounds for clustered sleep transistor sizing},
  booktitle    = {{DATE}},
  pages        = {1544--1549},
  publisher    = {{EDA} Consortium, San Jose, CA, {USA}},
  year         = {2007}
}

@inproceedings{DBLP:conf/glvlsi/CalimeraPSBMMP07,
  author       = {Andrea Calimera and
                  Antonio Pullini and
                  Ashoka Visweswara Sathanur and
                  Luca Benini and
                  Alberto Macii and
                  Enrico Macii and
                  Massimo Poncino},
  title        = {Design of a family of sleep transistor cells for a clustered power-gating
                  flow in 65nm technology},
  booktitle    = {{ACM} Great Lakes Symposium on {VLSI}},
  pages        = {501--504},
  publisher    = {{ACM}},
  year         = {2007}
}

@inproceedings{DBLP:conf/iscas/DuraisamiSSMMP07,
  author       = {Karthik Duraisami and
                  Prassanna Sithambaram and
                  Ashoka Visweswara Sathanur and
                  Alberto Macii and
                  Enrico Macii and
                  Massimo Poncino},
  title        = {Design Exploration of a Thermal Management Unit for Dynamic Control
                  of Temperature-Induced Clock Skew},
  booktitle    = {{ISCAS}},
  pages        = {1061--1064},
  publisher    = {{IEEE}},
  year         = {2007}
}

@inproceedings{DBLP:conf/islped/SathanurPBMMP07,
  author       = {Ashoka Visweswara Sathanur and
                  Antonio Pullini and
                  Luca Benini and
                  Alberto Macii and
                  Enrico Macii and
                  Massimo Poncino},
  title        = {Timing-driven row-based power gating},
  booktitle    = {{ISLPED}},
  pages        = {104--109},
  publisher    = {{ACM}},
  year         = {2007}
}

@inproceedings{DBLP:conf/iscas/ChakrabortyDSSMMP06,
  author       = {Ashutosh Chakraborty and
                  Karthik Duraisami and
                  Ashoka Visweswara Sathanur and
                  Prassanna Sithambaram and
                  Alberto Macii and
                  Enrico Macii and
                  Massimo Poncino},
  title        = {Implications of ultra low-voltage devices on design techniques for
                  controlling leakage in NanoCMOS circuits},
  booktitle    = {{ISCAS}},
  publisher    = {{IEEE}},
  year         = {2006}
}

@inproceedings{DBLP:conf/islped/ChakrabortyDSSBMMP06,
  author       = {Ashutosh Chakraborty and
                  Karthik Duraisami and
                  Ashoka Visweswara Sathanur and
                  Prassanna Sithambaram and
                  Luca Benini and
                  Alberto Macii and
                  Enrico Macii and
                  Massimo Poncino},
  title        = {Dynamic thermal clock skew compensation using tunable delay buffers},
  booktitle    = {{ISLPED}},
  pages        = {162--167},
  publisher    = {{ACM}},
  year         = {2006}
}

@inproceedings{DBLP:conf/patmos/ChakrabortyDSSMMP06,
  author       = {Ashutosh Chakraborty and
                  Karthik Duraisami and
                  Ashoka Visweswara Sathanur and
                  Prassanna Sithambaram and
                  Alberto Macii and
                  Enrico Macii and
                  Massimo Poncino},
  title        = {Dynamic Management of Thermally-Induced Clock Skew: An Implementation
                  Perspective},
  booktitle    = {{PATMOS}},
  series       = {Lecture Notes in Computer Science},
  volume       = {4148},
  pages        = {214--224},
  publisher    = {Springer},
  year         = {2006}
}

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