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@article{DBLP:journals/vlsisp/AsanovicMW93,
  author       = {Krste Asanovic and
                  Nelson Morgan and
                  John Wawrzynek},
  title        = {Using simulations of reduced precision arithmetic to design a neuro-microprocessor},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {6},
  number       = {1},
  pages        = {33--44},
  year         = {1993},
  url          = {https://doi.org/10.1007/BF01581957},
  doi          = {10.1007/BF01581957},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/AsanovicMW93.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/BhattacharyyaL93,
  author       = {Shuvra S. Bhattacharyya and
                  Edward A. Lee},
  title        = {Scheduling synchronous dataflow graphs for efficient looping},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {6},
  number       = {3},
  pages        = {271--288},
  year         = {1993},
  url          = {https://doi.org/10.1007/BF01608539},
  doi          = {10.1007/BF01608539},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/BhattacharyyaL93.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/Brebner93,
  author       = {Gordon J. Brebner},
  title        = {Configurable array logic circuits for computing network error detection
                  codes},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {6},
  number       = {2},
  pages        = {101--117},
  year         = {1993},
  url          = {https://doi.org/10.1007/BF01607875},
  doi          = {10.1007/BF01607875},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/Brebner93.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/Brunvand93,
  author       = {Erik Brunvand},
  title        = {Using FPGAs to implement self-timed systems},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {6},
  number       = {2},
  pages        = {173--190},
  year         = {1993},
  url          = {https://doi.org/10.1007/BF01607880},
  doi          = {10.1007/BF01607880},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/Brunvand93.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/CasagrandeCGM93,
  author       = {Giulio Casagrande and
                  Armando Chiari and
                  Carla Golla and
                  Salvatore Miceli},
  title        = {Vlsi programmable digital filter for video signal processing},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {6},
  number       = {3},
  pages        = {219--231},
  year         = {1993},
  url          = {https://doi.org/10.1007/BF01608535},
  doi          = {10.1007/BF01608535},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/CasagrandeCGM93.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/ChenZ93,
  author       = {Tom Chen and
                  Li Zhu},
  title        = {An expandable column fft architecture using circuit switching networks},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {6},
  number       = {3},
  pages        = {243--257},
  year         = {1993},
  url          = {https://doi.org/10.1007/BF01608537},
  doi          = {10.1007/BF01608537},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/ChenZ93.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/Fagin93,
  author       = {Barry S. Fagin},
  title        = {Quantitative measurements of {FPGA} utility in special and general
                  purpose processors},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {6},
  number       = {2},
  pages        = {129--137},
  year         = {1993},
  url          = {https://doi.org/10.1007/BF01607877},
  doi          = {10.1007/BF01607877},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/Fagin93.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/Graf93,
  author       = {Hans Peter Graf},
  title        = {Special issue on {VLSI} neural networks},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {6},
  number       = {1},
  pages        = {5},
  year         = {1993},
  url          = {https://doi.org/10.1007/BF01581954},
  doi          = {10.1007/BF01581954},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/Graf93.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/GrafSJ93,
  author       = {Hans Peter Graf and
                  Eduard S{\"{a}}ckinger and
                  Lawrence D. Jackel},
  title        = {Recent developments of electronic neural nets in North America},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {6},
  number       = {1},
  pages        = {19--31},
  year         = {1993},
  url          = {https://doi.org/10.1007/BF01581956},
  doi          = {10.1007/BF01581956},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/GrafSJ93.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/Hirai93,
  author       = {Yuzo Hirai},
  title        = {Recent {VLSI} neural networks in Japan},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {6},
  number       = {1},
  pages        = {7--18},
  year         = {1993},
  url          = {https://doi.org/10.1007/BF01581955},
  doi          = {10.1007/BF01581955},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/Hirai93.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/HuiskenDEEM93,
  author       = {Jos Huisken and
                  Antoine Delaruelle and
                  B. Egberts and
                  P. Eeckhout and
                  Jef L. van Meerbergen},
  title        = {Synthesis of synchronous communication hardware in a multiprocessor
                  architecture},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {6},
  number       = {3},
  pages        = {289--299},
  year         = {1993},
  url          = {https://doi.org/10.1007/BF01608540},
  doi          = {10.1007/BF01608540},
  timestamp    = {Thu, 23 Jun 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/HuiskenDEEM93.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/IsoahoPVT93,
  author       = {Jouni Isoaho and
                  Jari Pasanen and
                  Olli Vainio and
                  Hannu Tenhunen},
  title        = {{DSP} system integration and prototyping with {FPGAS}},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {6},
  number       = {2},
  pages        = {155--172},
  year         = {1993},
  url          = {https://doi.org/10.1007/BF01607879},
  doi          = {10.1007/BF01607879},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/IsoahoPVT93.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/JabriPLX93,
  author       = {Marwan A. Jabri and
                  Stephen Pickard and
                  Philip H. W. Leong and
                  Y. Xie},
  title        = {Algorithmic and implementation issues in analog low power learning
                  neural network chips},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {6},
  number       = {1},
  pages        = {67--76},
  year         = {1993},
  url          = {https://doi.org/10.1007/BF01581960},
  doi          = {10.1007/BF01581960},
  timestamp    = {Mon, 28 Aug 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/JabriPLX93.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/LeeSC93a,
  author       = {Ji{-}Chien Lee and
                  Bing J. Sheu and
                  Rama Chellappa},
  title        = {A mixed-signal {VLSI} competitive neuroprocessor for video motion
                  detection},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {6},
  number       = {1},
  pages        = {57--66},
  year         = {1993},
  url          = {https://doi.org/10.1007/BF01581959},
  doi          = {10.1007/BF01581959},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/LeeSC93a.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/Leeser93,
  author       = {Miriam Leeser},
  title        = {High level synthesis and generation FPGAs with the {BEDROC} system},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {6},
  number       = {3},
  pages        = {7},
  year         = {1993},
  url          = {https://doi.org/10.1007/BF01608541},
  doi          = {10.1007/BF01608541},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/Leeser93.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/LeeserCALM93,
  author       = {Miriam Leeser and
                  Richard Chapman and
                  Mark D. Aagaard and
                  Mark H. Linderman and
                  Stephan Meier},
  title        = {High level synthesis and generating FPGAs with the {BEDROC} system},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {6},
  number       = {2},
  pages        = {191--214},
  year         = {1993},
  url          = {https://doi.org/10.1007/BF01607881},
  doi          = {10.1007/BF01607881},
  timestamp    = {Thu, 18 Apr 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/LeeserCALM93.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/Mandelbaum93,
  author       = {David M. Mandelbaum},
  title        = {A method for calculation of the square root using combinatorial logic},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {6},
  number       = {3},
  pages        = {233--242},
  year         = {1993},
  url          = {https://doi.org/10.1007/BF01608536},
  doi          = {10.1007/BF01608536},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/Mandelbaum93.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/Mintzer93,
  author       = {Les Mintzer},
  title        = {{FIR} filters with field-programmable gate arrays},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {6},
  number       = {2},
  pages        = {119--127},
  year         = {1993},
  url          = {https://doi.org/10.1007/BF01607876},
  doi          = {10.1007/BF01607876},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/Mintzer93.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/Monaghan93,
  author       = {Sean Monaghan},
  title        = {A gate-level reconfigurable Monte carlo processor},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {6},
  number       = {2},
  pages        = {139--153},
  year         = {1993},
  url          = {https://doi.org/10.1007/BF01607878},
  doi          = {10.1007/BF01607878},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/Monaghan93.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/MooreL93,
  author       = {Will Moore and
                  Wayne Luk},
  title        = {Introduction},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {6},
  number       = {2},
  pages        = {99--100},
  year         = {1993},
  url          = {https://doi.org/10.1007/BF01607874},
  doi          = {10.1007/BF01607874},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/MooreL93.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/RamacherBB93,
  author       = {Ulrich Ramacher and
                  J{\"{o}}rg Beichter and
                  Nico Br{\"{u}}ls},
  title        = {A general-purpose signal processor architecture for neurocomputing
                  and preprocessing applications},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {6},
  number       = {1},
  pages        = {45--56},
  year         = {1993},
  url          = {https://doi.org/10.1007/BF01581958},
  doi          = {10.1007/BF01581958},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/RamacherBB93.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/SunKL93,
  author       = {Jenn{-}Dong Sun and
                  Hari Krishna and
                  K.{-}Y. Lin},
  title        = {A superfast algorithm for single-error correction in rrns and hardware
                  implementation},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {6},
  number       = {3},
  pages        = {259--269},
  year         = {1993},
  url          = {https://doi.org/10.1007/BF01608538},
  doi          = {10.1007/BF01608538},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/SunKL93.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/WuAC93,
  author       = {Yu{-}jhih Wu and
                  Michael D. Alston and
                  Paul M. Chau},
  title        = {Dynamic adaptation of quantization thresholds for soft-decision viterbi
                  decoding with a reinforcement learning neural network},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {6},
  number       = {1},
  pages        = {77--84},
  year         = {1993},
  url          = {https://doi.org/10.1007/BF01581961},
  doi          = {10.1007/BF01581961},
  timestamp    = {Mon, 28 Aug 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/WuAC93.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/ZimmermannLK93,
  author       = {Karl{-}Heinz Zimmermann and
                  Tien{-}Chien Lee and
                  Sun{-}Yuan Kung},
  title        = {On partitioning and fault tolerance issues for neural array processors},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {6},
  number       = {1},
  pages        = {85--94},
  year         = {1993},
  url          = {https://doi.org/10.1007/BF01581962},
  doi          = {10.1007/BF01581962},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/ZimmermannLK93.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

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