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Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

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@article{DBLP:journals/tvlsi/AminV99,
  author       = {Minesh B. Amin and
                  Bapiraju Vinnakota},
  title        = {Data parallel fault simulation},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {7},
  number       = {2},
  pages        = {183--190},
  year         = {1999},
  url          = {https://doi.org/10.1109/92.766745},
  doi          = {10.1109/92.766745},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/AminV99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/BakshiG99,
  author       = {Smita Bakshi and
                  Daniel D. Gajski},
  title        = {Partitioning and pipelining for performance-constrained hardware/software
                  systems},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {7},
  number       = {4},
  pages        = {419--432},
  year         = {1999},
  url          = {https://doi.org/10.1109/92.805749},
  doi          = {10.1109/92.805749},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/BakshiG99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/BernardinisRSTB99,
  author       = {Fernando De Bernardinis and
                  Roberto Roncella and
                  Roberto Saletti and
                  Pierangelo Terreni and
                  Graziano Bertini},
  title        = {An efficient {VLSI} architecture for real-time additive synthesis
                  of musical signals},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {7},
  number       = {1},
  pages        = {105--110},
  year         = {1999},
  url          = {https://doi.org/10.1109/92.748205},
  doi          = {10.1109/92.748205},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/BernardinisRSTB99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/BloughKO99,
  author       = {Douglas M. Blough and
                  Fadi J. Kurdahi and
                  Seong Yong Ohm},
  title        = {High-level synthesis of recoverable {VLSI} microarchitectures},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {7},
  number       = {4},
  pages        = {401--410},
  year         = {1999},
  url          = {https://doi.org/10.1109/92.805747},
  doi          = {10.1109/92.805747},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/BloughKO99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/BosiBS99,
  author       = {B. Bosi and
                  Guy Bois and
                  Yvon Savaria},
  title        = {Reconfigurable pipelined 2-D convolvers for fast digital signal processing},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {7},
  number       = {3},
  pages        = {299--308},
  year         = {1999},
  url          = {https://doi.org/10.1109/92.784091},
  doi          = {10.1109/92.784091},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/BosiBS99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/BurlesonKNRSWW99,
  author       = {Wayne P. Burleson and
                  Jason Ko and
                  Douglas Niehaus and
                  Krithi Ramamritham and
                  John A. Stankovic and
                  Gary Wallace and
                  Charles C. Weems},
  title        = {The spring scheduling coprocessor: a scheduling accelerator},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {7},
  number       = {1},
  pages        = {38--47},
  year         = {1999},
  url          = {https://doi.org/10.1109/92.748199},
  doi          = {10.1109/92.748199},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/BurlesonKNRSWW99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/ChakrabartiM99,
  author       = {Chaitali Chakrabarti and
                  Clint Mumford},
  title        = {Efficient realizations of encoders and decoders based on the 2-D discrete
                  wavelet transform},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {7},
  number       = {3},
  pages        = {289--298},
  year         = {1999},
  url          = {https://doi.org/10.1109/92.784090},
  doi          = {10.1109/92.784090},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/ChakrabartiM99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/ChenJWLC99,
  author       = {J.{-}Y. Chen and
                  Wen{-}Ben Jone and
                  Jinn{-}Shyan Wang and
                  Hsueh{-}I Lu and
                  Tien{-}Fu Chen},
  title        = {Segmented bus design for low-power systems},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {7},
  number       = {1},
  pages        = {25--29},
  year         = {1999},
  url          = {https://doi.org/10.1109/92.748197},
  doi          = {10.1109/92.748197},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/ChenJWLC99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/ChenSJ99,
  author       = {Tom Chen and
                  Glen Sunada and
                  Jain Jin},
  title        = {{COBRA:} a 100-MOPS single-chip programmable and expandable {FFT}},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {7},
  number       = {2},
  pages        = {174--182},
  year         = {1999},
  url          = {https://doi.org/10.1109/92.766744},
  doi          = {10.1109/92.766744},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/ChenSJ99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/ChoXC99,
  author       = {Seong{-}Hwan Cho and
                  Thucydides Xanthopoulos and
                  Anantha P. Chandrakasan},
  title        = {A low power variable length decoder for {MPEG-2} based on nonuniform
                  fine-grain table partitioning},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {7},
  number       = {2},
  pages        = {249--257},
  year         = {1999},
  url          = {https://doi.org/10.1109/92.766752},
  doi          = {10.1109/92.766752},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/ChoXC99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/ChowSRCPR99,
  author       = {Paul Chow and
                  Soon Ong Seo and
                  Jonathan Rose and
                  Kevin Chung and
                  Gerard P{\'{a}}ez{-}Monz{\'{o}}n and
                  Immanuel Rahardja},
  title        = {The design of an SRAM-based field-programmable gate array. I. Architecture},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {7},
  number       = {2},
  pages        = {191--197},
  year         = {1999},
  url          = {https://doi.org/10.1109/92.766746},
  doi          = {10.1109/92.766746},
  timestamp    = {Mon, 11 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tvlsi/ChowSRCPR99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/ChowSRCPR99a,
  author       = {Paul Chow and
                  Soon Ong Seo and
                  Jonathan Rose and
                  Kevin Chung and
                  Gerard P{\'{a}}ez{-}Monz{\'{o}}n and
                  Immanuel Rahardja},
  title        = {The design of a SRAM-based field-programmable gate array-Part {II:}
                  Circuit design and layout},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {7},
  number       = {3},
  pages        = {321--330},
  year         = {1999},
  url          = {https://doi.org/10.1109/92.784093},
  doi          = {10.1109/92.784093},
  timestamp    = {Wed, 14 Apr 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tvlsi/ChowSRCPR99a.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/DanckaertMCMG99,
  author       = {Koen Danckaert and
                  Kostas Masselos and
                  Francky Catthoor and
                  Hugo De Man and
                  Constantinos E. Goutis},
  title        = {Strategy for power-efficient design of parallel systems},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {7},
  number       = {2},
  pages        = {258--265},
  year         = {1999},
  url          = {https://doi.org/10.1109/92.766753},
  doi          = {10.1109/92.766753},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/DanckaertMCMG99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/DaveLJ99,
  author       = {Bharat P. Dave and
                  Ganesh Lakshminarayana and
                  Niraj K. Jha},
  title        = {{COSYN:} Hardware-software co-synthesis of heterogeneous distributed
                  embedded systems},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {7},
  number       = {1},
  pages        = {92--104},
  year         = {1999},
  url          = {https://doi.org/10.1109/92.748204},
  doi          = {10.1109/92.748204},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/DaveLJ99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/DenkP99,
  author       = {Tracy C. Denk and
                  Keshab K. Parhi},
  title        = {Two-dimensional retiming {[VLSI} design]},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {7},
  number       = {2},
  pages        = {198--211},
  year         = {1999},
  url          = {https://doi.org/10.1109/92.766747},
  doi          = {10.1109/92.766747},
  timestamp    = {Tue, 07 May 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tvlsi/DenkP99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/DuttaW99,
  author       = {Santanu Dutta and
                  Wayne H. Wolf},
  title        = {A circuit-driven design methodology for video signal-processing datapath
                  elements},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {7},
  number       = {2},
  pages        = {229--240},
  year         = {1999},
  url          = {https://doi.org/10.1109/92.766750},
  doi          = {10.1109/92.766750},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/DuttaW99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/FangWC99,
  author       = {Wen{-}Jong Fang and
                  Allen C.{-}H. Wu and
                  Duan{-}Ping Chen},
  title        = {EmGen-a module generator for logic emulation applications},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {7},
  number       = {4},
  pages        = {488--492},
  year         = {1999},
  url          = {https://doi.org/10.1109/92.805756},
  doi          = {10.1109/92.805756},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/FangWC99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/FavalliM99,
  author       = {Michele Favalli and
                  Cecilia Metra},
  title        = {Bus crosstalk fault-detection capabilities of error-detecting codes
                  for on-line testing},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {7},
  number       = {3},
  pages        = {392--396},
  year         = {1999},
  url          = {https://doi.org/10.1109/92.784100},
  doi          = {10.1109/92.784100},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/FavalliM99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/GoelS99,
  author       = {Manish Goel and
                  Naresh R. Shanbhag},
  title        = {Dynamic algorithm transformations (DAT)-a systematic approach to low-power
                  reconfigurable signal processing},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {7},
  number       = {4},
  pages        = {463--476},
  year         = {1999},
  url          = {https://doi.org/10.1109/92.805753},
  doi          = {10.1109/92.805753},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/GoelS99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/GopalakrishnanKB99,
  author       = {Ganesh Gopalakrishnan and
                  Prabhakar Kudva and
                  Erik Brunvand},
  title        = {Peephole optimization of asynchronous macromodule networks},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {7},
  number       = {1},
  pages        = {30--37},
  year         = {1999},
  url          = {https://doi.org/10.1109/92.748198},
  doi          = {10.1109/92.748198},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/GopalakrishnanKB99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/InamoriNE99,
  author       = {Minoru Inamori and
                  Jiro Naganuma and
                  Makoto Endo},
  title        = {A memory-based architecture for {MPEG2} system protocol LSIs},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {7},
  number       = {3},
  pages        = {339--344},
  year         = {1999},
  url          = {https://doi.org/10.1109/92.784095},
  doi          = {10.1109/92.784095},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/InamoriNE99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/IsmailFN99,
  author       = {Yehea I. Ismail and
                  Eby G. Friedman and
                  Jos{\'{e}} Luis Neves},
  title        = {Figures of merit to characterize the importance of on-chip inductance},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {7},
  number       = {4},
  pages        = {442--449},
  year         = {1999},
  url          = {https://doi.org/10.1109/92.805751},
  doi          = {10.1109/92.805751},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/IsmailFN99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/KarypisAKS99,
  author       = {George Karypis and
                  Rajat Aggarwal and
                  Vipin Kumar and
                  Shashi Shekhar},
  title        = {Multilevel hypergraph partitioning: applications in {VLSI} domain},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {7},
  number       = {1},
  pages        = {69--79},
  year         = {1999},
  url          = {https://doi.org/10.1109/92.748202},
  doi          = {10.1109/92.748202},
  timestamp    = {Mon, 08 Nov 2021 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/KarypisAKS99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/KrishnaCR99,
  author       = {Vamsi Krishna and
                  Ramamurti Chandramouli and
                  N. Ranganathan},
  title        = {Computation of lower bounds for switching activity using decision
                  theory},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {7},
  number       = {1},
  pages        = {125--129},
  year         = {1999},
  url          = {https://doi.org/10.1109/92.748209},
  doi          = {10.1109/92.748209},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/KrishnaCR99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/KrishnaRE99,
  author       = {Vamsi Krishna and
                  N. Ranganathan and
                  Abdel Ejnioui},
  title        = {A tree-matching chip},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {7},
  number       = {2},
  pages        = {277--280},
  year         = {1999},
  url          = {https://doi.org/10.1109/92.766755},
  doi          = {10.1109/92.766755},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/KrishnaRE99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/LafruitCCM99,
  author       = {Gauthier Lafruit and
                  Francky Catthoor and
                  Jan Cornelis and
                  Hugo De Man},
  title        = {An efficient {VLSI} architecture for 2-D wavelet image coding with
                  novel image scan},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {7},
  number       = {1},
  pages        = {56--68},
  year         = {1999},
  url          = {https://doi.org/10.1109/92.748201},
  doi          = {10.1109/92.748201},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/LafruitCCM99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/LakshminarayanaRJD99,
  author       = {Ganesh Lakshminarayana and
                  Anand Raghunathan and
                  Niraj K. Jha and
                  Sujit Dey},
  title        = {Power management in high-level synthesis},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {7},
  number       = {1},
  pages        = {7--15},
  year         = {1999},
  url          = {https://doi.org/10.1109/92.748195},
  doi          = {10.1109/92.748195},
  timestamp    = {Thu, 14 Oct 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tvlsi/LakshminarayanaRJD99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/LiSM99,
  author       = {Chung{-}Sheng Li and
                  Kumar N. Sivarajan and
                  David G. Messerschmitt},
  title        = {Statistical analysis of timing rules for high-speed synchronous {VLSI}
                  systems},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {7},
  number       = {4},
  pages        = {477--482},
  year         = {1999},
  url          = {https://doi.org/10.1109/92.805754},
  doi          = {10.1109/92.805754},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/LiSM99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/LinO99,
  author       = {Rong Lin and
                  Stephan Olariu},
  title        = {Efficient {VLSI} architectures for Columnsort},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {7},
  number       = {1},
  pages        = {135--138},
  year         = {1999},
  url          = {https://doi.org/10.1109/92.748211},
  doi          = {10.1109/92.748211},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/LinO99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/LinSJ99,
  author       = {Jiing{-}Yuan Lin and
                  Wen{-}Zen Shen and
                  Jing{-}Yang Jou},
  title        = {A structure-oriented power modeling technique for macrocells},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {7},
  number       = {3},
  pages        = {380--391},
  year         = {1999},
  url          = {https://doi.org/10.1109/92.784099},
  doi          = {10.1109/92.784099},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/LinSJ99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/LiuCML99,
  author       = {Tong Liu and
                  Xiao{-}Tao Chen and
                  Fred J. Meyer and
                  Fabrizio Lombardi},
  title        = {Test generation and scheduling for layout-based detection of bridge
                  faults in interconnects},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {7},
  number       = {1},
  pages        = {48--55},
  year         = {1999},
  url          = {https://doi.org/10.1109/92.748200},
  doi          = {10.1109/92.748200},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/LiuCML99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/Mahant-ShettiBL99,
  author       = {Shivaling S. Mahant{-}Shetti and
                  Poras T. Balsara and
                  Carl Lemonds},
  title        = {High performance low power array multiplier using temporal tiling},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {7},
  number       = {1},
  pages        = {121--124},
  year         = {1999},
  url          = {https://doi.org/10.1109/92.748208},
  doi          = {10.1109/92.748208},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/Mahant-ShettiBL99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/MandalCG99,
  author       = {Chittaranjan A. Mandal and
                  P. P. Chakrabarti and
                  Sujoy Ghose},
  title        = {A design space exploration scheme for data-path synthesis},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {7},
  number       = {3},
  pages        = {331--338},
  year         = {1999},
  url          = {https://doi.org/10.1109/92.784094},
  doi          = {10.1109/92.784094},
  timestamp    = {Mon, 07 Nov 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/MandalCG99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/MaseraPRZ99,
  author       = {Guido Masera and
                  Gianluca Piccinini and
                  Massimo Ruo Roch and
                  Maurizio Zamboni},
  title        = {{VLSI} architectures for turbo codes},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {7},
  number       = {3},
  pages        = {369--379},
  year         = {1999},
  url          = {https://doi.org/10.1109/92.784098},
  doi          = {10.1109/92.784098},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/MaseraPRZ99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/MasselosMSG99,
  author       = {Kostas Masselos and
                  Panagiotis Merakos and
                  Thanos Stouraitis and
                  Constantinos E. Goutis},
  title        = {Novel techniques for bus power consumption reduction in realizations
                  of sum-of-product computation},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {7},
  number       = {4},
  pages        = {492--497},
  year         = {1999},
  url          = {https://doi.org/10.1109/92.805757},
  doi          = {10.1109/92.805757},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/MasselosMSG99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/MizunoI99,
  author       = {Hiroyuki Mizuno and
                  Koichiro Ishibashi},
  title        = {A separated bit-line unified cache: Conciliating small on-chip cache
                  die-area and low miss ratio},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {7},
  number       = {1},
  pages        = {139--144},
  year         = {1999},
  url          = {https://doi.org/10.1109/92.748213},
  doi          = {10.1109/92.748213},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/MizunoI99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/MuS99,
  author       = {Fenghao Mu and
                  Christer Svensson},
  title        = {A layout-based schematic method for very high-speed {CMOS} cell design},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {7},
  number       = {1},
  pages        = {144--148},
  year         = {1999},
  url          = {https://doi.org/10.1109/92.748214},
  doi          = {10.1109/92.748214},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/MuS99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/PandaD99,
  author       = {Preeti Ranjan Panda and
                  Nikil D. Dutt},
  title        = {Low-power memory mapping through reducing address bus activity},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {7},
  number       = {3},
  pages        = {309--320},
  year         = {1999},
  url          = {https://doi.org/10.1109/92.784092},
  doi          = {10.1109/92.784092},
  timestamp    = {Sat, 05 Sep 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tvlsi/PandaD99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/PapachristouNS99,
  author       = {Christos A. Papachristou and
                  Mehrdad Nourani and
                  Mark Spining},
  title        = {A multiple clocking scheme for low-power {RTL} design},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {7},
  number       = {2},
  pages        = {266--276},
  year         = {1999},
  url          = {https://doi.org/10.1109/92.766754},
  doi          = {10.1109/92.766754},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/PapachristouNS99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/Parhi99,
  author       = {Keshab K. Parhi},
  title        = {Low-energy {CSMT} carry generators and binary adders},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {7},
  number       = {4},
  pages        = {450--462},
  year         = {1999},
  url          = {https://doi.org/10.1109/92.805752},
  doi          = {10.1109/92.805752},
  timestamp    = {Tue, 07 May 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tvlsi/Parhi99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/RamprasadSH99,
  author       = {Sumant Ramprasad and
                  Naresh R. Shanbhag and
                  Ibrahim N. Hajj},
  title        = {A coding framework for low-power address and data busses},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {7},
  number       = {2},
  pages        = {212--221},
  year         = {1999},
  url          = {https://doi.org/10.1109/92.766748},
  doi          = {10.1109/92.766748},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/RamprasadSH99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/RamprasadSH99a,
  author       = {Sumant Ramprasad and
                  Naresh R. Shanbhag and
                  Ibrahim N. Hajj},
  title        = {Information-theoretic bounds on average signal transition activity
                  {[VLSI} systems]},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {7},
  number       = {3},
  pages        = {359--368},
  year         = {1999},
  url          = {https://doi.org/10.1109/92.784097},
  doi          = {10.1109/92.784097},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/RamprasadSH99a.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/Sklyarov99,
  author       = {Valery Sklyarov},
  title        = {Hierarchical finite-state machines and their use for digital control},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {7},
  number       = {2},
  pages        = {222--228},
  year         = {1999},
  url          = {https://doi.org/10.1109/92.766749},
  doi          = {10.1109/92.766749},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/Sklyarov99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/SparmannMR99,
  author       = {Uwe Sparmann and
                  Holger M{\"{u}}ller and
                  Sudhakar M. Reddy},
  title        = {Universal delay test sets for logic networks},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {7},
  number       = {2},
  pages        = {156--166},
  year         = {1999},
  url          = {https://doi.org/10.1109/92.766742},
  doi          = {10.1109/92.766742},
  timestamp    = {Mon, 25 Oct 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tvlsi/SparmannMR99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/SuHCW99,
  author       = {Chih{-}Yuang Su and
                  Shih{-}Am Hwang and
                  Po{-}Song Chen and
                  Cheng{-}Wen Wu},
  title        = {An improved Montgomery's algorithm for high-speed {RSA} public-key
                  cryptosystem},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {7},
  number       = {2},
  pages        = {280--284},
  year         = {1999},
  url          = {https://doi.org/10.1109/92.766756},
  doi          = {10.1109/92.766756},
  timestamp    = {Sat, 30 Sep 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tvlsi/SuHCW99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/TsengW99,
  author       = {Wang{-}Dauh Tseng and
                  Kuochen Wang},
  title        = {Fuzzy-based {CMOS} circuit partitioning in built-in current testing},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {7},
  number       = {1},
  pages        = {116--120},
  year         = {1999},
  url          = {https://doi.org/10.1109/92.748207},
  doi          = {10.1109/92.748207},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/TsengW99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/WangR99,
  author       = {Chuan{-}Yu Wang and
                  Kaushik Roy},
  title        = {An activity-driven encoding scheme for power optimization in microprogrammed
                  control unit},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {7},
  number       = {1},
  pages        = {130--134},
  year         = {1999},
  url          = {https://doi.org/10.1109/92.748210},
  doi          = {10.1109/92.748210},
  timestamp    = {Sun, 11 Oct 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tvlsi/WangR99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/WeiCRJYD99,
  author       = {Liqiong Wei and
                  Zhanping Chen and
                  Kaushik Roy and
                  Mark C. Johnson and
                  Yibin Ye and
                  Vivek De},
  title        = {Design and optimization of dual-threshold circuits for low-voltage
                  low-power applications},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {7},
  number       = {1},
  pages        = {16--24},
  year         = {1999},
  url          = {https://doi.org/10.1109/92.748196},
  doi          = {10.1109/92.748196},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/WeiCRJYD99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/WiltonRV99,
  author       = {Steven J. E. Wilton and
                  Jonathan Rose and
                  Zvonko G. Vranesic},
  title        = {The memory/logic interface in FPGAs with large embedded memory arrays},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {7},
  number       = {1},
  pages        = {80--91},
  year         = {1999},
  url          = {https://doi.org/10.1109/92.748203},
  doi          = {10.1109/92.748203},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/WiltonRV99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/WuJ99,
  author       = {Chung{-}Yu Wu and
                  Hsin{-}Chin Jiang},
  title        = {An improved BJT-based silicon retina with tunable image smoothing
                  capability},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {7},
  number       = {2},
  pages        = {241--248},
  year         = {1999},
  url          = {https://doi.org/10.1109/92.766751},
  doi          = {10.1109/92.766751},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/WuJ99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/WuytackCJM99,
  author       = {Sven Wuytack and
                  Francky Catthoor and
                  Gjalt G. de Jong and
                  Hugo De Man},
  title        = {Minimizing the required memory bandwidth in {VLSI} system realizations},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {7},
  number       = {4},
  pages        = {433--441},
  year         = {1999},
  url          = {https://doi.org/10.1109/92.805750},
  doi          = {10.1109/92.805750},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/WuytackCJM99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/XuK99,
  author       = {Min Xu and
                  Fadi J. Kurdahi},
  title        = {Accurate prediction of quality metrics for logic level designs targeted
                  toward lookup-table-based FPGAs},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {7},
  number       = {4},
  pages        = {411--418},
  year         = {1999},
  url          = {https://doi.org/10.1109/92.805748},
  doi          = {10.1109/92.805748},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/XuK99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/YehL99,
  author       = {Yuan{-}Hau Yeh and
                  Chen{-}Yi Lee},
  title        = {Cost-effective {VLSI} architectures and buffer size optimization for
                  full-search block matching algorithms},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {7},
  number       = {3},
  pages        = {345--358},
  year         = {1999},
  url          = {https://doi.org/10.1109/92.784096},
  doi          = {10.1109/92.784096},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/YehL99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/YooGS99,
  author       = {Jae{-}Tack Yoo and
                  Ganesh Gopalakrishnan and
                  Kent F. Smith},
  title        = {Timing constraints for high-speed counterflow-clocked pipelining},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {7},
  number       = {2},
  pages        = {167--173},
  year         = {1999},
  url          = {https://doi.org/10.1109/92.766743},
  doi          = {10.1109/92.766743},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/YooGS99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/YunD99,
  author       = {Kenneth Y. Yun and
                  Ayoob E. Dooply},
  title        = {Pausible clocking-based heterogeneous systems},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {7},
  number       = {4},
  pages        = {482--488},
  year         = {1999},
  url          = {https://doi.org/10.1109/92.805755},
  doi          = {10.1109/92.805755},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/YunD99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/ZyubanK99,
  author       = {Victor V. Zyuban and
                  Peter M. Kogge},
  title        = {Application of {STD} to latch-power estimation},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {7},
  number       = {1},
  pages        = {111--115},
  year         = {1999},
  url          = {https://doi.org/10.1109/92.748206},
  doi          = {10.1109/92.748206},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/ZyubanK99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

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