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@article{DBLP:journals/tcad/AjwaniCM11,
author = {Gaurav Ajwani and
Chris Chu and
Wai{-}Kei Mak},
title = {{FOARS:} {FLUTE} Based Obstacle-Avoiding Rectilinear Steiner Tree
Construction},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {2},
pages = {194--204},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2010.2096571},
doi = {10.1109/TCAD.2010.2096571},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AjwaniCM11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ArumiMFEHK11,
author = {Daniel Arum{\'{\i}} and
Rosa Rodr{\'{\i}}guez{-}Monta{\~{n}}{\'{e}}s and
Joan Figueras and
Stefan Eichenberger and
Camelia Hora and
Bram Kruseman},
title = {Diagnosis of Interconnect Full Open Defects in the Presence of Fan-Out},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {12},
pages = {1911--1922},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2165071},
doi = {10.1109/TCAD.2011.2165071},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ArumiMFEHK11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AyoubIR11,
author = {Raid Zuhair Ayoub and
Krishnam Raju Indukuri and
Tajana Simunic Rosing},
title = {Temperature Aware Dynamic Workload Scheduling in Multisocket {CPU}
Servers},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {9},
pages = {1359--1372},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2153852},
doi = {10.1109/TCAD.2011.2153852},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AyoubIR11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BanerjeeSS11,
author = {Pritha Banerjee and
Megha Sangtani and
Susmita Sur{-}Kolay},
title = {Floorplanning for Partially Reconfigurable FPGAs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {1},
pages = {8--17},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2010.2079390},
doi = {10.1109/TCAD.2010.2079390},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BanerjeeSS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BarrioMMMH11,
author = {Alberto A. Del Barrio and
Seda Ogrenci Memik and
Mar{\'{\i}}a C. Molina and
Jose Manuel Mendias and
Rom{\'{a}}n Hermida},
title = {A Distributed Controller for Managing Speculative Functional Units
in High Level Synthesis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {3},
pages = {350--363},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2010.2089565},
doi = {10.1109/TCAD.2010.2089565},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BarrioMMMH11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BeniniC11,
author = {Luca Benini and
Luca P. Carloni},
title = {Guest Editorial: Special Section on the {ACM/IEEE} Symposium on Networks-on-Chip
2010},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {4},
pages = {492--493},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2115270},
doi = {10.1109/TCAD.2011.2115270},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BeniniC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BerettaRAS11,
author = {Ivan Beretta and
Vincenzo Rana and
David Atienza and
Donatella Sciuto},
title = {A Mapping Flow for Dynamically Reconfigurable Multi-Core System-on-Chip
Design},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {8},
pages = {1211--1224},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2138140},
doi = {10.1109/TCAD.2011.2138140},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BerettaRAS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BhatO11,
author = {Harish S. Bhat and
Braxton Osting},
title = {2-D Inductor-Capacitor Lattice Synthesis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {10},
pages = {1483--1492},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2159605},
doi = {10.1109/TCAD.2011.2159605},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BhatO11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BiswasB11,
author = {Sounil Biswas and
Ronald D. Blanton},
title = {Reducing Test Execution Cost of Integrated, Heterogeneous Systems
Using Continuous Test Data},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {1},
pages = {148--158},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2010.2066630},
doi = {10.1109/TCAD.2010.2066630},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BiswasB11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BogdanM11,
author = {Paul Bogdan and
Radu Marculescu},
title = {Non-Stationary Traffic Analysis and Its Implications on Multicore
Platform Design},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {4},
pages = {508--519},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2111270},
doi = {10.1109/TCAD.2011.2111270},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BogdanM11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BogdanM11a,
author = {Paul Bogdan and
Radu Marculescu},
title = {Hitting Time Analysis for Fault-Tolerant Communication at Nanoscale
in Future Multiprocessor Platforms},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {8},
pages = {1197--1210},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2138430},
doi = {10.1109/TCAD.2011.2138430},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BogdanM11a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BolandC11,
author = {David Boland and
George A. Constantinides},
title = {Bounding Variable Values and Round-Off Effects Using Handelman Representations},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {11},
pages = {1691--1704},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2161307},
doi = {10.1109/TCAD.2011.2161307},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BolandC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BounceurMS11,
author = {Ahc{\`{e}}ne Bounceur and
Salvador Mir and
Haralampos{-}G. D. Stratigopoulos},
title = {Estimation of Analog Parametric Test Metrics Using Copulas},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {9},
pages = {1400--1410},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2149522},
doi = {10.1109/TCAD.2011.2149522},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BounceurMS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BrambillaGG11,
author = {Angelo Brambilla and
Giambattista Gruosso and
Giancarlo Storti Gajani},
title = {A Probe-Based Harmonic Balance Method to Simulate Coupled Oscillators},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {7},
pages = {960--971},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2110570},
doi = {10.1109/TCAD.2011.2110570},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BrambillaGG11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChanHBC11,
author = {Johnnie Chan and
Gilbert Hendry and
Keren Bergman and
Luca P. Carloni},
title = {Physical-Layer Modeling and System-Level Design of Chip-Scale Photonic
Interconnection Networks},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {10},
pages = {1507--1520},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2157157},
doi = {10.1109/TCAD.2011.2157157},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChanHBC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenCX11,
author = {Zhen Chen and
Krishnendu Chakrabarty and
Dong Xiang},
title = {{MVP:} Minimum-Violations Partitioning for Reducing Capture Power
in At-Speed Delay-Fault Testing},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {11},
pages = {1762--1767},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2162237},
doi = {10.1109/TCAD.2011.2162237},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/ChenCX11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenKY11,
author = {C.{-}C. Chen and
C.{-}W. Kuo and
Y.{-}J. Yang},
title = {Generating Passive Compact Models for Piezoelectric Devices},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {3},
pages = {464--467},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2010.2090750},
doi = {10.1109/TCAD.2010.2090750},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChenKY11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenSMW11,
author = {Quan Chen and
Wim Schoenmaker and
Peter Meuris and
Ngai Wong},
title = {An Effective Formulation of Coupled Electromagnetic-TCAD Simulation
for Extremely High Frequency Onward},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {6},
pages = {866--876},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2010.2103270},
doi = {10.1109/TCAD.2010.2103270},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChenSMW11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChengGSQH11,
author = {Lerong Cheng and
Puneet Gupta and
Costas J. Spanos and
Kun Qian and
Lei He},
title = {Physically Justifiable Die-Level Modeling of Spatial Variation in
View of Systematic Across Wafer Variability},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {3},
pages = {388--401},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2010.2089568},
doi = {10.1109/TCAD.2010.2089568},
timestamp = {Thu, 28 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChengGSQH11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChiangYT11,
author = {Ming{-}Chao Chiang and
Tse{-}Chen Yeh and
Guo{-}Fu Tseng},
title = {A {QEMU} and SystemC-Based Cycle-Accurate {ISS} for Performance Estimation
on SoC Development},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {4},
pages = {593--606},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2010.2095631},
doi = {10.1109/TCAD.2010.2095631},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChiangYT11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChouHHTH11,
author = {Sheng Chou and
Cheng{-}Shen Han and
Po{-}Kai Huang and
Ko{-}Fan Tien and
Tsung{-}Yi Ho},
title = {An Effective and Efficient Framework for Clock Latency Range Aware
Clock Network Synthesis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {7},
pages = {1045--1057},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2110591},
doi = {10.1109/TCAD.2011.2110591},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChouHHTH11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChuangKSC11,
author = {Yi{-}Lin Chuang and
Sangmin Kim and
Youngsoo Shin and
Yao{-}Wen Chang},
title = {Pulsed-Latch Aware Placement for Timing-Integrity Optimization},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {12},
pages = {1856--1869},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2165717},
doi = {10.1109/TCAD.2011.2165717},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChuangKSC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChuangLC11,
author = {Yi{-}Lin Chuang and
Po{-}Wei Lee and
Yao{-}Wen Chang},
title = {Voltage-Drop Aware Analytical Placement by Global Power Spreading
for Mixed-Size Circuit Designs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {11},
pages = {1649--1662},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2163071},
doi = {10.1109/TCAD.2011.2163071},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChuangLC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CongHJ11,
author = {Jason Cong and
Hui Huang and
Wei Jiang},
title = {Pattern-Mining for Behavioral Synthesis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {6},
pages = {939--944},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2106370},
doi = {10.1109/TCAD.2011.2106370},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CongHJ11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CongLNNVZ11,
author = {Jason Cong and
Bin Liu and
Stephen Neuendorffer and
Juanjo Noguera and
Kees A. Vissers and
Zhiru Zhang},
title = {High-Level Synthesis for FPGAs: From Prototyping to Deployment},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {4},
pages = {473--491},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2110592},
doi = {10.1109/TCAD.2011.2110592},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/CongLNNVZ11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CuiCTA11,
author = {Aijiao Cui and
Chip{-}Hong Chang and
Sofi{\`{e}}ne Tahar and
Amr T. Abdel{-}Hamid},
title = {A Robust {FSM} Watermarking Scheme for {IP} Protection of Sequential
Circuit Design},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {5},
pages = {678--690},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2010.2098131},
doi = {10.1109/TCAD.2010.2098131},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CuiCTA11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CzyszMMRST11,
author = {Dariusz Czysz and
Grzegorz Mrugalski and
Nilanjan Mukherjee and
Janusz Rajski and
Przemyslaw Szczerbicki and
Jerzy Tyszer},
title = {Deterministic Clustering of Incompatible Test Cubes for Higher Power-Aware
{EDT} Compression},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {8},
pages = {1225--1238},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2126574},
doi = {10.1109/TCAD.2011.2126574},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CzyszMMRST11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DingTP11,
author = {Duo Ding and
J. Andres Torres and
David Z. Pan},
title = {High Performance Lithography Hotspot Detection With Successively Refined
Pattern Identifications and Machine Learning},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {11},
pages = {1621--1634},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2164537},
doi = {10.1109/TCAD.2011.2164537},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DingTP11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DregoCBS11,
author = {Nigel Drego and
Anantha P. Chandrakasan and
Duane S. Boning and
Devavrat Shah},
title = {Reduction of Variation-Induced Energy Overhead in Multi-Core Processors},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {6},
pages = {891--904},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2010.2102431},
doi = {10.1109/TCAD.2010.2102431},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DregoCBS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/EggersglussD11,
author = {Stephan Eggersgl{\"{u}}{\ss} and
Rolf Drechsler},
title = {Efficient Data Structures and Methodologies for SAT-Based {ATPG} Providing
High Fault Coverage in Industrial Application},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {9},
pages = {1411--1415},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2152450},
doi = {10.1109/TCAD.2011.2152450},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/EggersglussD11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/EickSLSG11,
author = {Michael Eick and
Martin Strasser and
Kun Lu and
Ulf Schlichtmann and
Helmut E. Graeb},
title = {Comprehensive Generation of Hierarchical Placement Rules for Analog
Integrated Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {2},
pages = {180--193},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2010.2097172},
doi = {10.1109/TCAD.2010.2097172},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/EickSLSG11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ErdoganO11,
author = {Erdem Serkan Erdogan and
Sule Ozev},
title = {A Multi-Site Test Solution for Quadrature Modulation {RF} Transceivers},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {9},
pages = {1421--1425},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2144594},
doi = {10.1109/TCAD.2011.2144594},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ErdoganO11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/FengZYTZ11,
author = {Chunyang Feng and
Hai Zhou and
Changhao Yan and
Jun Tao and
Xuan Zeng},
title = {Efficient Approximation Algorithms for Chemical Mechanical Polishing
Dummy Fill},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {3},
pages = {402--415},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2010.2088030},
doi = {10.1109/TCAD.2010.2088030},
timestamp = {Wed, 16 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/FengZYTZ11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/FengZZ11,
author = {Zhuo Feng and
Xueqian Zhao and
Zhiyu Zeng},
title = {Robust Parallel Preconditioned Power Grid Simulation on {GPU} With
Adaptive Runtime Performance Modeling and Optimization},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {4},
pages = {562--573},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2010.2091437},
doi = {10.1109/TCAD.2010.2091437},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/FengZZ11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/FeySFD11,
author = {G{\"{o}}rschwin Fey and
Andr{\'{e}} S{\"{u}}lflow and
Stefan Frehse and
Rolf Drechsler},
title = {Effective Robustness Analysis Using Bounded Model Checking Techniques},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {8},
pages = {1239--1252},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2120950},
doi = {10.1109/TCAD.2011.2120950},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/FeySFD11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ForemanHCT11,
author = {Eric A. Foreman and
Peter A. Habitz and
Ming{-}C. Cheng and
Christino Tamon},
title = {Inclusion of Chemical-Mechanical Polishing Variation in Statistical
Static Timing Analysis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {11},
pages = {1758--1762},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2162066},
doi = {10.1109/TCAD.2011.2162066},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ForemanHCT11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Garcia-LoureiroSAVAMK11,
author = {Antonio J. Garc{\'{\i}}a{-}Loureiro and
Natalia Seoane and
Manuel Aldegunde and
Ra{\'{u}}l Val{\'{\i}}n Ferreiro and
Asen Asenov and
Antonio Martinez and
Karol Kalna},
title = {Implementation of the Density Gradient Quantum Corrections for 3-D
Simulations of Multigate Nanoscaled Transistors},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {6},
pages = {841--851},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2107990},
doi = {10.1109/TCAD.2011.2107990},
timestamp = {Wed, 23 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/Garcia-LoureiroSAVAMK11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GebhardtYS11,
author = {Daniel Gebhardt and
JunBok You and
Kenneth S. Stevens},
title = {Design of an Energy-Efficient Asynchronous NoC and Its Optimization
Tools for Heterogeneous SoCs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {9},
pages = {1387--1399},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2149870},
doi = {10.1109/TCAD.2011.2149870},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GebhardtYS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GhaniN11,
author = {Nahi H. Abdul Ghani and
Farid N. Najm},
title = {Fast Vectorless Power Grid Verification Under an {RLC} Model},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {5},
pages = {691--703},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2010.2096593},
doi = {10.1109/TCAD.2010.2096593},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GhaniN11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GhasemazarP11,
author = {Mohammad Ghasemazar and
Massoud Pedram},
title = {Optimizing the Power-Delay Product of a Linear Pipeline by Opportunistic
Time Borrowing},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {10},
pages = {1493--1506},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2159218},
doi = {10.1109/TCAD.2011.2159218},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GhasemazarP11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GolshanKB11,
author = {Shahin Golshan and
Hessam Kooti and
Elaheh Bozorgzadeh},
title = {SEU-Aware High-Level Data Path Synthesis and Layout Generation on
SRAM-Based FPGAs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {6},
pages = {829--840},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2106851},
doi = {10.1109/TCAD.2011.2106851},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GolshanKB11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GongZLTZ11,
author = {Min Gong and
Hai Zhou and
Li Li and
Jun Tao and
Xuan Zeng},
title = {Binning Optimization for Transparently-Latched Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {2},
pages = {270--283},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2010.2081870},
doi = {10.1109/TCAD.2010.2081870},
timestamp = {Wed, 16 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GongZLTZ11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GowdaVKB11,
author = {Tejaswi Gowda and
Sarma B. K. Vrudhula and
Niranjan Kulkarni and
Krzysztof S. Berezowski},
title = {Identification of Threshold Functions and Synthesis of Threshold Networks},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {5},
pages = {665--677},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2010.2100232},
doi = {10.1109/TCAD.2010.2100232},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/GowdaVKB11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Gu11,
author = {Chenjie Gu},
title = {{QLMOR:} {A} Projection-Based Nonlinear Model Order Reduction Approach
Using Quadratic-Linear Representation of Nonlinear Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {9},
pages = {1307--1320},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2142184},
doi = {10.1109/TCAD.2011.2142184},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Gu11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HabalG11,
author = {Husni M. Habal and
Helmut Graeb},
title = {Constraint-Based Layout-Driven Sizing of Analog Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {8},
pages = {1089--1102},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2158732},
doi = {10.1109/TCAD.2011.2158732},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HabalG11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HanumaiahVC11,
author = {Vinay Hanumaiah and
Sarma B. K. Vrudhula and
Karam S. Chatha},
title = {Performance Optimal Online {DVFS} and Task Migration Techniques for
Thermally Constrained Multi-Core Processors},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {11},
pages = {1677--1690},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2161308},
doi = {10.1109/TCAD.2011.2161308},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HanumaiahVC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HorakNCV11,
author = {Michael N. Horak and
Steven M. Nowick and
Matthew Carlberg and
Uzi Vishkin},
title = {A Low-Overhead Asynchronous Interconnection Network for {GALS} Chip
Multiprocessors},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {4},
pages = {494--507},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2114970},
doi = {10.1109/TCAD.2011.2114970},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HorakNCV11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HouLT11,
author = {Chih{-}Sheng Hou and
Jin{-}Fu Li and
Tsu{-}Wei Tseng},
title = {Memory Built-in Self-Repair Planning Framework for RAMs in SoCs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {11},
pages = {1731--1743},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2160174},
doi = {10.1109/TCAD.2011.2160174},
timestamp = {Tue, 17 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HouLT11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HsiehLB11,
author = {Tong{-}Yu Hsieh and
Kuen{-}Jong Lee and
Melvin A. Breuer},
title = {An Error-Tolerance-Based Test Methodology to Support Product Grading
for Yield Enhancement},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {6},
pages = {930--934},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2113690},
doi = {10.1109/TCAD.2011.2113690},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HsiehLB11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HsuCN11,
author = {Chin{-}Hsiung Hsu and
Yao{-}Wen Chang and
Sani R. Nassif},
title = {Simultaneous Layout Migration and Decomposition for Double Patterning
Technology},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {2},
pages = {284--294},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2010.2079990},
doi = {10.1109/TCAD.2010.2079990},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HsuCN11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HuOITSMK11,
author = {Wei Hu and
Jason Oberg and
Ali Irturk and
Mohit Tiwari and
Timothy Sherwood and
Dejun Mu and
Ryan Kastner},
title = {Theoretical Fundamentals of Gate Level Information Flow Tracking},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {8},
pages = {1128--1140},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2120970},
doi = {10.1109/TCAD.2011.2120970},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HuOITSMK11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HuTXZZS11,
author = {Jingtong Hu and
Wei{-}Che Tseng and
Chun Jason Xue and
Qingfeng Zhuge and
Yingchao Zhao and
Edwin Hsing{-}Mean Sha},
title = {Write Activity Minimization for Nonvolatile Main Memory Via Scheduling
and Recomputation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {4},
pages = {584--592},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2010.2097307},
doi = {10.1109/TCAD.2010.2097307},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HuTXZZS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HuangH11,
author = {Tsung{-}Wei Huang and
Tsung{-}Yi Ho},
title = {A Two-Stage Integer Linear Programming-Based Droplet Routing Algorithm
for Pin-Constrained Digital Microfluidic Biochips},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {2},
pages = {215--228},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2010.2097190},
doi = {10.1109/TCAD.2010.2097190},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HuangH11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HuangLY11,
author = {Tao Huang and
Liang Li and
Evangeline F. Y. Young},
title = {On the Construction of Optimal Obstacle-Avoiding Rectilinear Steiner
Minimum Trees},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {5},
pages = {718--731},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2010.2098930},
doi = {10.1109/TCAD.2010.2098930},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HuangLY11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HuangYH11,
author = {Tsung{-}Wei Huang and
Shih{-}Yuan Yeh and
Tsung{-}Yi Ho},
title = {A Network-Flow Based Pin-Count Aware Routing Algorithm for Broadcast-Addressing
{EWOD} Chips},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {12},
pages = {1786--1799},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2163158},
doi = {10.1109/TCAD.2011.2163158},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HuangYH11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/IonutiuRS11,
author = {Roxana Ionutiu and
Joost Rommes and
Wil H. A. Schilders},
title = {SparseRC: Sparsity Preserving Model Reduction for {RC} Circuits With
Many Terminals},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {12},
pages = {1828--1841},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2166075},
doi = {10.1109/TCAD.2011.2166075},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/IonutiuRS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/IrturkMOSK11,
author = {Ali Irturk and
Janarbek Matai and
Jason Oberg and
Jeffrey Su and
Ryan Kastner},
title = {Simulate and Eliminate: {A} Top-to-Bottom Design Methodology for Automatic
Generation of Application Specific Architectures},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {8},
pages = {1173--1183},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2120990},
doi = {10.1109/TCAD.2011.2120990},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/IrturkMOSK11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JaffariA11,
author = {Javid Jaffari and
Mohab Anis},
title = {On Efficient LHS-Based Yield Analysis of Analog Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {1},
pages = {159--163},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2010.2070930},
doi = {10.1109/TCAD.2010.2070930},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JaffariA11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JainRGSC11,
author = {Tushar N. K. Jain and
Mukund Ramakrishna and
Paul V. Gratz and
Alexander Sprintson and
Gwan Choi},
title = {Asynchronous Bypass Channels for Multi-Synchronous NoCs: {A} Router
Microarchitecture, Topology, and Routing Algorithm},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {11},
pages = {1663--1676},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2161190},
doi = {10.1109/TCAD.2011.2161190},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/JainRGSC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JamaaMM11,
author = {M. Haykel Ben Jamaa and
Kartik Mohanram and
Giovanni De Micheli},
title = {An Efficient Gate Library for Ambipolar {CNTFET} Logic},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {2},
pages = {242--255},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2010.2085250},
doi = {10.1109/TCAD.2010.2085250},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JamaaMM11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JangJK11,
author = {Hochang Jang and
Deokjin Joo and
Taewhan Kim},
title = {Buffer Sizing and Polarity Assignment in Clock Tree Synthesis for
Power/Ground Noise Minimization},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {1},
pages = {96--109},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2010.2066650},
doi = {10.1109/TCAD.2010.2066650},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JangJK11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JangP11,
author = {Wooyoung Jang and
David Z. Pan},
title = {Application-Aware NoC Design for Efficient {SDRAM} Access},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {10},
pages = {1521--1533},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2160176},
doi = {10.1109/TCAD.2011.2160176},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JangP11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JooKH11,
author = {Young{-}Pyo Joo and
Sungchan Kim and
Soonhoi Ha},
title = {Fast Communication Architecture Exploration of Processor Pool-Based
MPSoC via Static Performance Analysis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {3},
pages = {468--472},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2010.2088930},
doi = {10.1109/TCAD.2010.2088930},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JooKH11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JouLW11,
author = {Jer{-}Min Jou and
Yun{-}Lung Lee and
Sih{-}Sian Wu},
title = {Model-Driven Design and Generation of New Multi-Facet Arbiters: From
the Design Model to the Hardware Synthesis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {8},
pages = {1184--1196},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2139211},
doi = {10.1109/TCAD.2011.2139211},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JouLW11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KangKYK11,
author = {Kyungsu Kang and
Jungsoo Kim and
Sungjoo Yoo and
Chong{-}Min Kyung},
title = {Runtime Power Management of 3-D Multi-Core Architectures Under Peak
Power and Temperature Constraints},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {6},
pages = {905--918},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2010.2101371},
doi = {10.1109/TCAD.2010.2101371},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KangKYK11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KaoYAC11,
author = {Yu{-}Hsiang Kao and
Ming Yang and
N. Sertac Artan and
H. Jonathan Chao},
title = {CNoC: High-Radix Clos Network-on-Chip},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {12},
pages = {1897--1910},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2164538},
doi = {10.1109/TCAD.2011.2164538},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KaoYAC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KavousianosC11,
author = {Xrysovalantis Kavousianos and
Krishnendu Chakrabarty},
title = {Generation of Compact Stuck-At Test Sets Targeting Unmodeled Defects},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {5},
pages = {787--791},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2010.2101750},
doi = {10.1109/TCAD.2010.2101750},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/KavousianosC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KerenLS11,
author = {Osnat Keren and
Ilya Levin and
Radomir S. Stankovic},
title = {Determining the Number of Paths in Decision Diagrams by Using Autocorrelation
Coefficients},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {1},
pages = {31--44},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2010.2069290},
doi = {10.1109/TCAD.2010.2069290},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/KerenLS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KimLSYCP11,
author = {Yongjoo Kim and
Jongeun Lee and
Aviral Shrivastava and
Jonghee W. Yoon and
Doosan Cho and
Yunheung Paek},
title = {High Throughput Data Mapping for Coarse-Grained Reconfigurable Architectures},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {11},
pages = {1599--1609},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2161217},
doi = {10.1109/TCAD.2011.2161217},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/KimLSYCP11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KimMW11,
author = {Se Hun Kim and
Saibal Mukhopadhyay and
Wayne H. Wolf},
title = {Modeling and Analysis of Image Dependence and Its Implications for
Energy Savings in Error Tolerant Image Processing},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {8},
pages = {1163--1172},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2126573},
doi = {10.1109/TCAD.2011.2126573},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KimMW11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KimPCC11,
author = {Younghyun Kim and
Sangyoung Park and
Youngjin Cho and
Naehyuck Chang},
title = {System-Level Online Power Estimation Using an On-Chip Bus Performance
Monitoring Unit},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {11},
pages = {1585--1598},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2160349},
doi = {10.1109/TCAD.2011.2160349},
timestamp = {Thu, 28 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KimPCC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KimSK11,
author = {Kyosun Kim and
Sangho Shin and
Sung{-}Mo Kang},
title = {Field Programmable Stateful Logic Array},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {12},
pages = {1800--1813},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2165067},
doi = {10.1109/TCAD.2011.2165067},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KimSK11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KimYK11,
author = {Jungsoo Kim and
Sungjoo Yoo and
Chong{-}Min Kyung},
title = {Program Phase-Aware Dynamic Voltage Scaling Under Variable Computational
Workload and Memory Stall Environment},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {1},
pages = {110--123},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2010.2068630},
doi = {10.1109/TCAD.2010.2068630},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KimYK11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KinsmanN11,
author = {Adam B. Kinsman and
Nicola Nicolici},
title = {Automated Range and Precision Bit-Width Allocation for Iterative Computations},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {9},
pages = {1265--1278},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2152840},
doi = {10.1109/TCAD.2011.2152840},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KinsmanN11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LanLLHC11,
author = {Ying{-}Cherng Lan and
Yueh{-}Chi Lin and
Shih{-}Hsin Lo and
Yu Hen Hu and
Sao{-}Jie Chen},
title = {A Bidirectional NoC (BiNoC) Architecture With Dynamic Self-Reconfigurable
Channel},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {3},
pages = {427--440},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2010.2086930},
doi = {10.1109/TCAD.2010.2086930},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LanLLHC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LeeCD11,
author = {Ganghee Lee and
Kiyoung Choi and
Nikil D. Dutt},
title = {Mapping Multi-Domain Applications Onto Coarse-Grained Reconfigurable
Architectures},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {5},
pages = {637--650},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2010.2098571},
doi = {10.1109/TCAD.2010.2098571},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LeeCD11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LeeDW11,
author = {Mincent Lee and
Li{-}Ming Denq and
Cheng{-}Wen Wu},
title = {A Memory Built-In Self-Repair Scheme Based on Configurable Spares},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {6},
pages = {919--929},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2106812},
doi = {10.1109/TCAD.2011.2106812},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LeeDW11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LeeL11,
author = {Young{-}Joon Lee and
Sung Kyu Lim},
title = {Co-Optimization and Analysis of Signal, Power, and Thermal Interconnects
in 3-D ICs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {11},
pages = {1635--1648},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2157159},
doi = {10.1109/TCAD.2011.2157159},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LeeL11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LeeLH11,
author = {Kuen{-}Jong Lee and
Wei{-}Cheng Lien and
Tong{-}Yu Hsieh},
title = {Test Response Compaction via Output Bit Selection},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {10},
pages = {1534--1544},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2159116},
doi = {10.1109/TCAD.2011.2159116},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LeeLH11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LeeS11,
author = {Jongeun Lee and
Aviral Shrivastava},
title = {Static Analysis of Register File Vulnerability},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {4},
pages = {607--616},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2010.2095630},
doi = {10.1109/TCAD.2010.2095630},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/LeeS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiH11,
author = {Min Li and
Michael S. Hsiao},
title = {3-D Parallel Fault Simulation With {GPGPU}},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {10},
pages = {1545--1555},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2158432},
doi = {10.1109/TCAD.2011.2158432},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiH11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiMS11,
author = {Xiao{-}Chun Li and
Jun{-}Fa Mao and
Madhavan Swaminathan},
title = {Transient Analysis of CMOS-Gate-Driven {RLGC} Interconnects Based
on {FDTD}},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {4},
pages = {574--583},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2010.2095650},
doi = {10.1109/TCAD.2010.2095650},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiMS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiaoCL11,
author = {Kuan{-}Yu Liao and
Chia{-}Yuan Chang and
James Chien{-}Mo Li},
title = {A Parallel Test Pattern Generation Algorithm to Meet Multiple Quality
Objectives},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {11},
pages = {1767--1772},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2157693},
doi = {10.1109/TCAD.2011.2157693},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiaoCL11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LinB11,
author = {Yen{-}Tzu Lin and
R. D. (Shawn) Blanton},
title = {{METER:} Measuring Test Effectiveness Regionally},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {7},
pages = {1058--1071},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2113670},
doi = {10.1109/TCAD.2011.2113670},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LinB11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LinC11,
author = {Cliff Chiung{-}Yu Lin and
Yao{-}Wen Chang},
title = {Cross-Contamination Aware Design Methodology for Pin-Constrained Digital
Microfluidic Biochips},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {6},
pages = {817--828},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2108010},
doi = {10.1109/TCAD.2011.2108010},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LinC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LinCL11,
author = {Yen{-}Hung Lin and
Shu{-}Hsin Chang and
Yih{-}Lang Li},
title = {Critical-Trunk-Based Obstacle-Avoiding Rectilinear Steiner Tree Routings
and Buffer Insertion for Delay and Slack Optimization},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {9},
pages = {1335--1348},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2150222},
doi = {10.1109/TCAD.2011.2150222},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LinCL11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LinH11,
author = {Jai{-}Ming Lin and
Zhi{-}Xiong Hung},
title = {{UFO:} Unified Convex Optimization Algorithms for Fixed-Outline Floorplanning
Considering Pre-Placed Modules},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {7},
pages = {1034--1044},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2114531},
doi = {10.1109/TCAD.2011.2114531},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LinH11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LinHC11,
author = {Mark Po{-}Hung Lin and
Chih{-}Cheng Hsu and
Yao{-}Tsung Chang},
title = {Post-Placement Power Optimization With Multi-Bit Flip-Flops},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {12},
pages = {1870--1882},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2165716},
doi = {10.1109/TCAD.2011.2165716},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/LinHC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LinMM11,
author = {Yi{-}Wei Lin and
Malgorzata Marek{-}Sadowska and
Wojciech Maly},
title = {On Cell Layout-Performance Relationships in VeSFET-Based, High-Density
Regular Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {2},
pages = {229--241},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2010.2097191},
doi = {10.1109/TCAD.2010.2097191},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LinMM11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LinZWC11,
author = {Mark Po{-}Hung Lin and
Hongbo Zhang and
Martin D. F. Wong and
Yao{-}Wen Chang},
title = {Thermal-Driven Analog Placement Considering Device Matching},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {3},
pages = {325--336},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2010.2097308},
doi = {10.1109/TCAD.2010.2097308},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/LinZWC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LingBSZ11,
author = {Andrew C. Ling and
Stephen Dean Brown and
Sean Safarpour and
Jianwen Zhu},
title = {Toward Automated ECOs in FPGAs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {1},
pages = {18--30},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2010.2067833},
doi = {10.1109/TCAD.2010.2067833},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LingBSZ11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LittleWMTBY11,
author = {Scott Little and
David Walter and
Chris J. Myers and
Robert A. Thacker and
Satish Batchu and
Tomohiro Yoneda},
title = {Verification of Analog/Mixed-Signal Circuits Using Labeled Hybrid
Petri Nets},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {4},
pages = {617--630},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2010.2097450},
doi = {10.1109/TCAD.2010.2097450},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LittleWMTBY11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiuFG11,
author = {Bo Liu and
Francisco V. Fern{\'{a}}ndez and
Georges G. E. Gielen},
title = {Efficient and Accurate Statistical Analog Yield Optimization and Variation-Aware
Circuit Sizing Based on Computational Intelligence Techniques},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {6},
pages = {793--805},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2106850},
doi = {10.1109/TCAD.2011.2106850},
timestamp = {Thu, 15 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiuFG11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiuSH11,
author = {Yifang Liu and
Rupesh S. Shelar and
Jiang Hu},
title = {Simultaneous Technology Mapping and Placement for Delay Minimization},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {3},
pages = {416--426},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2010.2089569},
doi = {10.1109/TCAD.2010.2089569},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiuSH11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiuZRG11,
author = {Bo Liu and
Dixian Zhao and
Patrick Reynaert and
Georges G. E. Gielen},
title = {Synthesis of Integrated Passive Components for High-Frequency {RF}
ICs Based on Evolutionary Computation and Machine Learning Techniques},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {10},
pages = {1458--1468},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2162067},
doi = {10.1109/TCAD.2011.2162067},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiuZRG11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LoiAFMB11,
author = {Igor Loi and
Federico Angiolini and
Shinobu Fujita and
Subhasish Mitra and
Luca Benini},
title = {Characterization and Implementation of Fault-Tolerant Vertical Links
for 3-D Networks-on-Chip},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {1},
pages = {124--134},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2010.2065990},
doi = {10.1109/TCAD.2010.2065990},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LoiAFMB11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LuoYMWS11,
author = {Lijuan Luo and
Tan Yan and
Qiang Ma and
Martin D. F. Wong and
Toshiyuki Shibuya},
title = {A New Strategy for Simultaneous Escape Based on Boundary Routing},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {2},
pages = {205--214},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2010.2097173},
doi = {10.1109/TCAD.2010.2097173},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LuoYMWS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MaQYZ11,
author = {Qiang Ma and
Zaichen Qian and
Evangeline F. Y. Young and
Hai Zhou},
title = {MSV-Driven Floorplanning},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {8},
pages = {1152--1162},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2131890},
doi = {10.1109/TCAD.2011.2131890},
timestamp = {Wed, 16 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MaQYZ11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MaT11,
author = {Junxia Ma and
Mohammad Tehranipoor},
title = {Layout-Aware Critical Path Delay Test Under Maximum Power Supply Noise
Effects},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {12},
pages = {1923--1934},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2163159},
doi = {10.1109/TCAD.2011.2163159},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MaT11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MaXTY11,
author = {Qiang Ma and
Linfu Xiao and
Yiu{-}Cheong Tam and
Evangeline F. Y. Young},
title = {Simultaneous Handling of Symmetry, Common Centroid, and General Placement
Constraints},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {1},
pages = {85--95},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2010.2064490},
doi = {10.1109/TCAD.2010.2064490},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MaXTY11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MaffezzoniD11,
author = {Paolo Maffezzoni and
Dario D'Amore},
title = {Analysis of Phase Diffusion Process in Oscillators Due to White and
Colored-Noise Sources},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {10},
pages = {1574--1578},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2157919},
doi = {10.1109/TCAD.2011.2157919},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MaffezzoniD11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MaslovS11,
author = {Dmitri Maslov and
Mehdi Saeedi},
title = {Reversible Circuit Optimization Via Leaving the Boolean Domain},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {6},
pages = {806--816},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2105555},
doi = {10.1109/TCAD.2011.2105555},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/MaslovS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MatsutaniKIUNA11,
author = {Hiroki Matsutani and
Michihiro Koibuchi and
Daisuke Ikebuchi and
Kimiyoshi Usami and
Hiroshi Nakamura and
Hideharu Amano},
title = {Performance, Area, and Power Evaluations of Ultrafine-Grained Run-Time
Power-Gating Routers for CMPs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {4},
pages = {520--533},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2110470},
doi = {10.1109/TCAD.2011.2110470},
timestamp = {Fri, 22 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/MatsutaniKIUNA11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MeleF11,
author = {Santino Mele and
Michele Favalli},
title = {A {SAT} Based Test Generation Method for Delay Fault Testing of Macro
Based Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {4},
pages = {631--635},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2010.2093290},
doi = {10.1109/TCAD.2010.2093290},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MeleF11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MiettinenHRV11,
author = {Pekka Miettinen and
Mikko Honkala and
Janne Roos and
Martti Valtonen},
title = {PartMOR: Partitioning-Based Realizable Model-Order Reduction Method
for {RLC} Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {3},
pages = {374--387},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2010.2090751},
doi = {10.1109/TCAD.2010.2090751},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MiettinenHRV11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MintarnoSZVCBDM11,
author = {Evelyn Mintarno and
Jo{\"{e}}lle Skaf and
Rui Zheng and
Jyothi Velamala and
Yu Cao and
Stephen P. Boyd and
Robert W. Dutton and
Subhasish Mitra},
title = {Self-Tuning for Maximized Lifetime Energy-Efficiency in the Presence
of Circuit Aging},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {5},
pages = {760--773},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2010.2100531},
doi = {10.1109/TCAD.2010.2100531},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MintarnoSZVCBDM11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MizunumaLY11,
author = {Hitoshi Mizunuma and
Yi{-}Chang Lu and
Chia{-}Lin Yang},
title = {Thermal Modeling and Analysis for 3-D ICs With Integrated Microchannel
Cooling},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {9},
pages = {1293--1306},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2144596},
doi = {10.1109/TCAD.2011.2144596},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MizunumaLY11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MukherjeeDM11,
author = {Subhankar Mukherjee and
Pallab Dasgupta and
Siddhartha Mukhopadhyay},
title = {Auxiliary Specifications for Context-Sensitive Monitoring of {AMS}
Assertions},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {10},
pages = {1446--1457},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2155065},
doi = {10.1109/TCAD.2011.2155065},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MukherjeeDM11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MukherjeePRT11,
author = {Nilanjan Mukherjee and
Artur Pogiel and
Janusz Rajski and
Jerzy Tyszer},
title = {BIST-Based Fault Diagnosis for Read-Only Memories},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {7},
pages = {1072--1085},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2127030},
doi = {10.1109/TCAD.2011.2127030},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MukherjeePRT11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/NoiaCGMV11,
author = {Brandon Noia and
Krishnendu Chakrabarty and
Sandeep Kumar Goel and
Erik Jan Marinissen and
Jouke Verbree},
title = {Test-Architecture Optimization and Test Scheduling for TSV-Based 3-D
Stacked ICs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {11},
pages = {1705--1718},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2160177},
doi = {10.1109/TCAD.2011.2160177},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/NoiaCGMV11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/NurvitadhiHKL11,
author = {Eriko Nurvitadhi and
James C. Hoe and
Timothy Kam and
Shih{-}Lien Lu},
title = {Automatic Pipelining From Transactional Datapath Specifications},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {3},
pages = {441--454},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2010.2088950},
doi = {10.1109/TCAD.2010.2088950},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/NurvitadhiHKL11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/OzdalH11,
author = {Muhammet Mustafa Ozdal and
Renato Fernandes Hentschke},
title = {An Algorithmic Study of Exact Route Matching for Integrated Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {12},
pages = {1842--1855},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2165068},
doi = {10.1109/TCAD.2011.2165068},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/OzdalH11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PaikLS11,
author = {Seungwhun Paik and
Seonggwan Lee and
Youngsoo Shin},
title = {Retiming Pulsed-Latch Circuits With Regulating Pulse Width},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {8},
pages = {1114--1127},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2126932},
doi = {10.1109/TCAD.2011.2126932},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PaikLS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PalesiAFC11,
author = {Maurizio Palesi and
Giuseppe Ascia and
Fabrizio Fazzino and
Vincenzo Catania},
title = {Data Encoding Schemes in Networks on Chip},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {5},
pages = {774--786},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2010.2098590},
doi = {10.1109/TCAD.2010.2098590},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PalesiAFC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Papadopoulou11,
author = {Evanthia Papadopoulou},
title = {Net-Aware Critical Area Extraction for Opens in {VLSI} Circuits Via
Higher-Order Voronoi Diagrams},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {5},
pages = {704--717},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2010.2100550},
doi = {10.1109/TCAD.2010.2100550},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Papadopoulou11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz11,
author = {Irith Pomeranz},
title = {Generation of Multi-Cycle Broadside Tests},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {8},
pages = {1253--1257},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2138470},
doi = {10.1109/TCAD.2011.2138470},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz11a,
author = {Irith Pomeranz},
title = {Scan Shift Power of Functional Broadside Tests},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {9},
pages = {1416--1420},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2149890},
doi = {10.1109/TCAD.2011.2149890},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz11a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz11b,
author = {Irith Pomeranz},
title = {Subsets of Primary Input Vectors in Sequential Test Generation for
Single Stuck-at Faults},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {10},
pages = {1579--1583},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2157158},
doi = {10.1109/TCAD.2011.2157158},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz11b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/QianRZB11,
author = {Weikang Qian and
Marc D. Riedel and
Hongchao Zhou and
Jehoshua Bruck},
title = {Transforming Probabilities With Combinational Logic},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {9},
pages = {1279--1292},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2144630},
doi = {10.1109/TCAD.2011.2144630},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/QianRZB11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RajaramP11,
author = {Anand Rajaram and
David Z. Pan},
title = {Robust Chip-Level Clock Tree Synthesis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {6},
pages = {877--890},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2106852},
doi = {10.1109/TCAD.2011.2106852},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/RajaramP11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RamanujamSLP11,
author = {Rohit Sunkam Ramanujam and
Vassos Soteriou and
Bill Lin and
Li{-}Shiuan Peh},
title = {Extending the Effective Throughput of NoCs With Distributed Shared-Buffer
Routers},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {4},
pages = {548--561},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2110550},
doi = {10.1109/TCAD.2011.2110550},
timestamp = {Mon, 01 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/RamanujamSLP11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ReddiB11,
author = {Vijay Janapa Reddi and
David M. Brooks},
title = {Resilient Architectures via Collaborative Design: Maximizing Commodity
Processor Performance in the Presence of Variations},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {10},
pages = {1429--1445},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2163635},
doi = {10.1109/TCAD.2011.2163635},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ReddiB11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RenD11,
author = {Huan Ren and
Shantanu Dutt},
title = {Effective Power Optimization Under Timing and Voltage-Island Constraints
Via Simultaneous V\({}_{\mbox{dd}}\), V\({}_{\mbox{th}}\) Assignments,
Gate Sizing, and Placement},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {5},
pages = {746--759},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2010.2097330},
doi = {10.1109/TCAD.2010.2097330},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/RenD11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RiversGSKB11,
author = {Jude A. Rivers and
Meeta Sharma Gupta and
Jeonghee Shin and
Prabhakar Kudva and
Pradip Bose},
title = {Error Tolerance in Server Class Processors},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {7},
pages = {945--959},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2158100},
doi = {10.1109/TCAD.2011.2158100},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/RiversGSKB11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RizzoliMMM11,
author = {Vittorio Rizzoli and
Diego Masotti and
Franco Mastri and
Emanuele Montanari},
title = {System-Oriented Harmonic-Balance Algorithms for Circuit-Level Simulation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {2},
pages = {256--269},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2010.2092250},
doi = {10.1109/TCAD.2010.2092250},
timestamp = {Wed, 07 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/RizzoliMMM11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RodrigoFRMBCSD11,
author = {Samuel Rodrigo and
Jos{\'{e}} Flich and
Antoni Roca and
Simone Medardoni and
Davide Bertozzi and
Jes{\'{u}}s Camacho Villanueva and
Federico Silla and
Jos{\'{e}} Duato},
title = {Cost-Efficient On-Chip Routing Implementations for {CMP} and MPSoC
Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {4},
pages = {534--547},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2119150},
doi = {10.1109/TCAD.2011.2119150},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/RodrigoFRMBCSD11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RostamiM11,
author = {Masoud Rostami and
Kartik Mohanram},
title = {Dual-V\({}_{\mbox{th}}\) Independent-Gate FinFETs for Low Power Logic
Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {3},
pages = {337--349},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2010.2097310},
doi = {10.1109/TCAD.2010.2097310},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/RostamiM11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RoyD11,
author = {Sourajeet Roy and
Anestis Dounavis},
title = {Transient Simulation of Distributed Networks Using Delay Extraction
Based Numerical Convolution},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {3},
pages = {364--373},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2010.2090065},
doi = {10.1109/TCAD.2010.2090065},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/RoyD11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Rubanov11,
author = {Nikolay Rubanov},
title = {A General Framework to Perform the {MAX/MIN} Operations in Parameterized
Statistical Timing Analysis Using Information Theoretic Concepts},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {7},
pages = {1011--1019},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2113610},
doi = {10.1109/TCAD.2011.2113610},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Rubanov11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SabryCARB11,
author = {Mohamed M. Sabry and
Ayse K. Coskun and
David Atienza and
Tajana Simunic Rosing and
Thomas Brunschwiler},
title = {Energy-Efficient Multiobjective Thermal Control for Liquid-Cooled
3-D Stacked Architectures},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {12},
pages = {1883--1896},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2164540},
doi = {10.1109/TCAD.2011.2164540},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SabryCARB11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Sapatnekar11,
author = {Sachin S. Sapatnekar},
title = {Editorial},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {1},
pages = {1},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2010.2097013},
doi = {10.1109/TCAD.2010.2097013},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Sapatnekar11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SaxenaC11,
author = {Prashant Saxena and
Yao{-}Wen Chang},
title = {Guest Editorial},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {2},
pages = {165--166},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2010.2098150},
doi = {10.1109/TCAD.2010.2098150},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SaxenaC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ShebaitaDPI11,
author = {Ahmed Shebaita and
Debasish Das and
Dusan Petranovic and
Yehea I. Ismail},
title = {A Novel Moment Based Framework for Accurate and Efficient Static Timing
Analysis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {8},
pages = {1258--1262},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2121110},
doi = {10.1109/TCAD.2011.2121110},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ShebaitaDPI11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ShenQXWZL11,
author = {ShengYu Shen and
Ying Qin and
Liquan Xiao and
Kefei Wang and
Jianmin Zhang and
Sikun Li},
title = {A Halting Algorithm to Determine the Existence of the Decoder},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {10},
pages = {1556--1563},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2159792},
doi = {10.1109/TCAD.2011.2159792},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ShenQXWZL11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SinanogluA11,
author = {Ozgur Sinanoglu and
Sobeeh Almukhaizim},
title = {Unified 2-D X-Alignment for Improving the Observability of Response
Compactors},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {11},
pages = {1744--1757},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2160175},
doi = {10.1109/TCAD.2011.2160175},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/SinanogluA11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SuvakD11,
author = {Onder Suvak and
Alper Demir},
title = {On Phase Models for Oscillators},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {7},
pages = {972--985},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2113630},
doi = {10.1109/TCAD.2011.2113630},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SuvakD11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TannirK11,
author = {Dani Tannir and
Roni Khazaka},
title = {Adjoint Sensitivity Analysis of Nonlinear Distortion in Radio Frequency
Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {6},
pages = {934--939},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2108559},
doi = {10.1109/TCAD.2011.2108559},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TannirK11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ThongN11,
author = {Jason Thong and
Nicola Nicolici},
title = {An Optimal and Practical Approach to Single Constant Multiplication},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {9},
pages = {1373--1386},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2153853},
doi = {10.1109/TCAD.2011.2153853},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ThongN11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TolbertZLM11,
author = {Jeremy R. Tolbert and
Xin Zhao and
Sung Kyu Lim and
Saibal Mukhopadhyay},
title = {Analysis and Design of Energy and Slew Aware Subthreshold Clock Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {9},
pages = {1349--1358},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2144595},
doi = {10.1109/TCAD.2011.2144595},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TolbertZLM11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/VeetilCBS11,
author = {Vineeth Veetil and
Kaviraj Chopra and
David T. Blaauw and
Dennis Sylvester},
title = {Fast Statistical Static Timing Analysis Using Smart Monte Carlo Techniques},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {6},
pages = {852--865},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2108030},
doi = {10.1109/TCAD.2011.2108030},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/VeetilCBS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/VillenaS11,
author = {Jorge Fernandez Villena and
L. Miguel Silveira},
title = {Multi-Dimensional Automatic Sampling Schemes for Multi-Point Modeling
Methodologies},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {8},
pages = {1141--1151},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2158721},
doi = {10.1109/TCAD.2011.2158721},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/VillenaS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangCNWXV11,
author = {Feng Wang and
Yibo Chen and
Chrysostomos Nicopoulos and
Xiaoxia Wu and
Yuan Xie and
Narayanan Vijaykrishnan},
title = {Variation-Aware Task and Communication Mapping for MPSoC Architecture},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {2},
pages = {295--307},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2010.2077830},
doi = {10.1109/TCAD.2010.2077830},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WangCNWXV11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangZCYCG11,
author = {Renshen Wang and
Yulei Zhang and
Nan{-}Chi Chou and
Evangeline F. Y. Young and
Chung{-}Kuan Cheng and
Ronald L. Graham},
title = {Bus Matrix Synthesis Based on Steiner Graphs for Power Efficient System-on-Chip
Communications},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {2},
pages = {167--179},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2010.2097170},
doi = {10.1109/TCAD.2010.2097170},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WangZCYCG11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WeiCH11,
author = {Tongquan Wei and
Xiaodao Chen and
Shiyan Hu},
title = {Reliability-Driven Energy-Efficient Task Scheduling for Multiprocessor
Real-Time Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {10},
pages = {1569--1573},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2160178},
doi = {10.1109/TCAD.2011.2160178},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WeiCH11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WuDL11,
author = {Tai{-}Hsuan Wu and
Azadeh Davoodi and
Jeffrey T. Linderoth},
title = {{GRIP:} Global Routing via Integer Programming},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {1},
pages = {72--84},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2010.2066030},
doi = {10.1109/TCAD.2010.2066030},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WuDL11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WuWWJTZHJHLHY11,
author = {Shianling Wu and
Laung{-}Terng Wang and
Xiaoqing Wen and
Zhigang Jiang and
Lang Tan and
Yu Zhang and
Yu Hu and
Wen{-}Ben Jone and
Michael S. Hsiao and
James Chien{-}Mo Li and
Jiun{-}Lang Huang and
Lizhen Yu},
title = {Using Launch-on-Capture for Testing Scan Designs Containing Synchronous
and Asynchronous Clock Domains},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {3},
pages = {455--463},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2010.2092510},
doi = {10.1109/TCAD.2010.2092510},
timestamp = {Fri, 25 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WuWWJTZHJHLHY11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/XiangZ11,
author = {Dong Xiang and
Ye Zhang},
title = {Cost-Effective Power-Aware Core Testing in NoCs Based on a New Unicast-Based
Multicast Scheme},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {1},
pages = {135--147},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2010.2066070},
doi = {10.1109/TCAD.2010.2066070},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/XiangZ11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/XiaoY11,
author = {Zigang Xiao and
Evangeline F. Y. Young},
title = {Placement and Routing for Cross-Referencing Digital Microfluidic Biochips},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {7},
pages = {1000--1010},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2113730},
doi = {10.1109/TCAD.2011.2113730},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/XiaoY11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/XieD11,
author = {Lin Xie and
Azadeh Davoodi},
title = {Bound-Based Statistically-Critical Path Extraction Under Process Variations},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {1},
pages = {59--71},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2010.2072670},
doi = {10.1109/TCAD.2010.2072670},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/XieD11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/XiongW11,
author = {Xuanxing Xiong and
Jia Wang},
title = {Dual Algorithms for Vectorless Power Grid Verification Under Linear
Current Constraints},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {10},
pages = {1469--1482},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2158433},
doi = {10.1109/TCAD.2011.2158433},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/XiongW11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YanCM11,
author = {Jackey Z. Yan and
Chris C. N. Chu and
Wai{-}Kei Mak},
title = {SafeChoice: {A} Novel Approach to Hypergraph Clustering for Wirelength-Driven
Placement},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {7},
pages = {1020--1033},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2114950},
doi = {10.1109/TCAD.2011.2114950},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YanCM11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YangKAFI11,
author = {Sheng Yang and
S. Saqib Khursheed and
Bashir M. Al{-}Hashimi and
David Flynn and
Sachin Idgunji},
title = {Reliable State Retention-Based Embedded Processors Through Monitoring
and Recovery},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {12},
pages = {1773--1785},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2166590},
doi = {10.1109/TCAD.2011.2166590},
timestamp = {Mon, 15 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YangKAFI11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YangSVB11,
author = {Yu{-}Shen Yang and
Subarna Sinha and
Andreas G. Veneris and
Robert K. Brayton},
title = {Automating Logic Transformations With Approximate SPFDs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {5},
pages = {651--664},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2110590},
doi = {10.1109/TCAD.2011.2110590},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YangSVB11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YaoSR11,
author = {Chunhua Yao and
Kewal K. Saluja and
Parameswaran Ramanathan},
title = {Power and Thermal Constrained Test Scheduling Under Deep Submicron
Technologies},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {2},
pages = {317--322},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2010.2079350},
doi = {10.1109/TCAD.2010.2079350},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YaoSR11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YeDLN11,
author = {Xiaoji Ye and
Wei Dong and
Peng Li and
Sani R. Nassif},
title = {Hierarchical Multialgorithm Parallel Circuit Simulation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {1},
pages = {45--58},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2010.2067870},
doi = {10.1109/TCAD.2010.2067870},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YeDLN11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YuL11,
author = {Guo Yu and
Peng Li},
title = {Hierarchical Analog/Mixed-Signal Circuit Optimization Under Process
Variations and Tuning},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {2},
pages = {313--317},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2010.2071250},
doi = {10.1109/TCAD.2010.2071250},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YuL11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YuanLGQ11,
author = {Lin Yuan and
Sean Leventhal and
Junjun Gu and
Gang Qu},
title = {TALk: {A} Temperature-Aware Leakage Minimization Technique for Real-Time
Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {10},
pages = {1564--1568},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2160541},
doi = {10.1109/TCAD.2011.2160541},
timestamp = {Wed, 15 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/YuanLGQ11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhangLLARB11,
author = {Wangyang Zhang and
Xin Li and
Frank Liu and
Emrah Acar and
Rob A. Rutenbar and
Ronald D. Blanton},
title = {Virtual Probe: {A} Statistical Framework for Low-Cost Silicon Characterization
of Nanoscale Integrated Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {12},
pages = {1814--1827},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2164536},
doi = {10.1109/TCAD.2011.2164536},
timestamp = {Fri, 22 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/ZhangLLARB11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhangPHWM11,
author = {Jie Zhang and
Nishant Patil and
Arash Hazeghi and
H.{-}S. Philip Wong and
Subhasish Mitra},
title = {Characterization and Design of Logic Circuits in the Presence of Carbon
Nanotube Density Variations},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {8},
pages = {1103--1113},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2121010},
doi = {10.1109/TCAD.2011.2121010},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZhangPHWM11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhaoGCFH11,
author = {Xueqian Zhao and
Yonghe Guo and
Xiaodao Chen and
Zhuo Feng and
Shiyan Hu},
title = {Hierarchical Cross-Entropy Optimization for Fast On-Chip Decap Budgeting},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {11},
pages = {1610--1620},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2162068},
doi = {10.1109/TCAD.2011.2162068},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZhaoGCFH11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhaoLLL11,
author = {Xin Zhao and
Dean L. Lewis and
Hsien{-}Hsin S. Lee and
Sung Kyu Lim},
title = {Low-Power Clock Tree Design for Pre-Bond Testing of 3-D Stacked ICs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {5},
pages = {732--745},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2010.2098130},
doi = {10.1109/TCAD.2010.2098130},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZhaoLLL11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhaoXC11,
author = {Yang Zhao and
Tao Xu and
Krishnendu Chakrabarty},
title = {Broadcast Electrode-Addressing and Scheduling Methods for Pin-Constrained
Digital Microfluidic Biochips},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {7},
pages = {986--999},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2116250},
doi = {10.1109/TCAD.2011.2116250},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/ZhaoXC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhongKA11,
author = {Shida Zhong and
S. Saqib Khursheed and
Bashir M. Al{-}Hashimi},
title = {A Fast and Accurate Process Variation-Aware Modeling Technique for
Resistive Bridge Defects},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {11},
pages = {1719--1730},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2162065},
doi = {10.1109/TCAD.2011.2162065},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZhongKA11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhouLZT11,
author = {Tracey Y. Zhou and
Hang Liu and
Dian Zhou and
Tuna B. Tarim},
title = {A Fast Analog Circuit Analysis Algorithm for Design Modification and
Verification},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {2},
pages = {308--313},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2010.2081750},
doi = {10.1109/TCAD.2010.2081750},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZhouLZT11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhuoCSB11,
author = {Cheng Zhuo and
Kaviraj Chopra and
Dennis Sylvester and
David T. Blaauw},
title = {Process Variation and Temperature-Aware Full Chip Oxide Breakdown
Reliability Analysis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {9},
pages = {1321--1334},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2142183},
doi = {10.1109/TCAD.2011.2142183},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZhuoCSB11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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