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@article{DBLP:journals/integration/Bayrakci15,
  author       = {Alp Arslan Bayrakci},
  title        = {Stochastic logical effort as a variation aware delay model to estimate
                  timing yield},
  journal      = {Integr.},
  volume       = {48},
  pages        = {101--108},
  year         = {2015},
  url          = {https://doi.org/10.1016/j.vlsi.2014.07.003},
  doi          = {10.1016/J.VLSI.2014.07.003},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/Bayrakci15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/CasuM15,
  author       = {Mario R. Casu and
                  Paolo Mantovani},
  title        = {A synchronous latency-insensitive {RISC} for better than worst-case
                  design},
  journal      = {Integr.},
  volume       = {48},
  pages        = {72--82},
  year         = {2015},
  url          = {https://doi.org/10.1016/j.vlsi.2014.01.003},
  doi          = {10.1016/J.VLSI.2014.01.003},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/CasuM15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/ChandrasettyA15,
  author       = {Vikram Arkalgud Chandrasetty and
                  Syed Mahfuzul Aziz},
  title        = {Resource efficient {LDPC} decoders for multimedia communication},
  journal      = {Integr.},
  volume       = {48},
  pages        = {213--220},
  year         = {2015},
  url          = {https://doi.org/10.1016/j.vlsi.2014.09.002},
  doi          = {10.1016/J.VLSI.2014.09.002},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/ChandrasettyA15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/HsuLC15,
  author       = {Chih{-}Cheng Hsu and
                  Mark Po{-}Hung Lin and
                  Yao{-}Tsung Chang},
  title        = {Crosstalk-aware multi-bit flip-flop generation for power optimization},
  journal      = {Integr.},
  volume       = {48},
  pages        = {146--157},
  year         = {2015},
  url          = {https://doi.org/10.1016/j.vlsi.2014.08.002},
  doi          = {10.1016/J.VLSI.2014.08.002},
  timestamp    = {Sun, 12 Nov 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/HsuLC15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/JiangX15,
  author       = {Bo Jiang and
                  Tian Xia},
  title        = {{ADPLL} design parameters determinations through noise modeling},
  journal      = {Integr.},
  volume       = {48},
  pages        = {138--145},
  year         = {2015},
  url          = {https://doi.org/10.1016/j.vlsi.2014.08.001},
  doi          = {10.1016/J.VLSI.2014.08.001},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/JiangX15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/JinWL15,
  author       = {Song Jin and
                  Yu Wang and
                  Tongna Liu},
  title        = {On optimizing system energy of voltage-frequency island based 3-D
                  multi-core SoCs under thermal constraints},
  journal      = {Integr.},
  volume       = {48},
  pages        = {36--45},
  year         = {2015},
  url          = {https://doi.org/10.1016/j.vlsi.2014.05.001},
  doi          = {10.1016/J.VLSI.2014.05.001},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/JinWL15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/LourencoCPMH15,
  author       = {Nuno Louren{\c{c}}o and
                  Ant{\'{o}}nio Canelas and
                  Ricardo Povoa and
                  Ricardo Martins and
                  Nuno Horta},
  title        = {Floorplan-aware analog {IC} sizing and optimization based on topological
                  constraints},
  journal      = {Integr.},
  volume       = {48},
  pages        = {183--197},
  year         = {2015},
  url          = {https://doi.org/10.1016/j.vlsi.2014.07.002},
  doi          = {10.1016/J.VLSI.2014.07.002},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/LourencoCPMH15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/MahabadiKKNM15,
  author       = {Aminollah Mahabadi and
                  Ahmad Khonsari and
                  Behnam Khodabandeloo and
                  Hamid Noori and
                  Alireza Majidi},
  title        = {Critical path-aware voltage island partitioning and floorplanning
                  for hard real-time embedded systems},
  journal      = {Integr.},
  volume       = {48},
  pages        = {21--35},
  year         = {2015},
  url          = {https://doi.org/10.1016/j.vlsi.2014.05.002},
  doi          = {10.1016/J.VLSI.2014.05.002},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/MahabadiKKNM15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/Majzoub15,
  author       = {Sohaib Majzoub},
  title        = {Reducing random-dopant fluctuation impact using footer transistors
                  in many-core systems},
  journal      = {Integr.},
  volume       = {48},
  pages        = {46--54},
  year         = {2015},
  url          = {https://doi.org/10.1016/j.vlsi.2014.06.005},
  doi          = {10.1016/J.VLSI.2014.06.005},
  timestamp    = {Mon, 03 Jan 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/Majzoub15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/MalakLIDJGLT15,
  author       = {Akram Malak and
                  Yao Li and
                  Ramy Iskander and
                  Fran{\c{c}}ois Durbin and
                  Farakh Javid and
                  Jean{-}Marc Guebhard and
                  Marie{-}Minerve Lou{\"{e}}rat and
                  Andr{\'{e}} Tissot},
  title        = {Fast multidimensional optimization of analog circuits initiated by
                  monodimensional global Peano explorations},
  journal      = {Integr.},
  volume       = {48},
  pages        = {198--212},
  year         = {2015},
  url          = {https://doi.org/10.1016/j.vlsi.2014.04.002},
  doi          = {10.1016/J.VLSI.2014.04.002},
  timestamp    = {Fri, 13 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/MalakLIDJGLT15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/MirzaeiMM15,
  author       = {Mohammad Mirzaei and
                  Mahdi Mosaffa and
                  Siamak Mohammadi},
  title        = {Variation-aware approaches with power improvement in digital circuits},
  journal      = {Integr.},
  volume       = {48},
  pages        = {83--100},
  year         = {2015},
  url          = {https://doi.org/10.1016/j.vlsi.2014.07.001},
  doi          = {10.1016/J.VLSI.2014.07.001},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/MirzaeiMM15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/MoiseevWK15,
  author       = {Konstantin Moiseev and
                  Shmuel Wimer and
                  Avinoam Kolodny},
  title        = {Timing-constrained power minimization in {VLSI} circuits by simultaneous
                  multilayer wire spacing},
  journal      = {Integr.},
  volume       = {48},
  pages        = {116--128},
  year         = {2015},
  url          = {https://doi.org/10.1016/j.vlsi.2014.03.002},
  doi          = {10.1016/J.VLSI.2014.03.002},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/MoiseevWK15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/Nnolim15,
  author       = {Uche Afam Nnolim},
  title        = {Log-hybrid architecture for tonal correction combined with modified
                  un-sharp masking filter algorithm for colour image enhancement},
  journal      = {Integr.},
  volume       = {48},
  pages        = {221--229},
  year         = {2015},
  url          = {https://doi.org/10.1016/j.vlsi.2014.09.001},
  doi          = {10.1016/J.VLSI.2014.09.001},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/Nnolim15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/OuCL15,
  author       = {Shih{-}Hao Ou and
                  Kuo{-}Chiang Chang and
                  Chih{-}Wei Liu},
  title        = {An energy-efficient, high-precision {SFP} {LPFIR} filter engine for
                  digital hearing aids},
  journal      = {Integr.},
  volume       = {48},
  pages        = {230--238},
  year         = {2015},
  url          = {https://doi.org/10.1016/j.vlsi.2014.06.004},
  doi          = {10.1016/J.VLSI.2014.06.004},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/OuCL15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/RosenSHBB15,
  author       = {Julius von Rosen and
                  Felix Salfelder and
                  Lars Hedrich and
                  Benjamin Betting and
                  Uwe Brinkschulte},
  title        = {A highly dependable self-adaptive mixed-signal multi-core system-on-chip
                  architecture},
  journal      = {Integr.},
  volume       = {48},
  pages        = {55--71},
  year         = {2015},
  url          = {https://doi.org/10.1016/j.vlsi.2014.04.001},
  doi          = {10.1016/J.VLSI.2014.04.001},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/RosenSHBB15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/TrikiWAP15,
  author       = {Maryam Triki and
                  Yanzhi Wang and
                  Ahmed Chiheb Ammari and
                  Massoud Pedram},
  title        = {Hierarchical power management of a system with autonomously power-managed
                  components using reinforcement learning},
  journal      = {Integr.},
  volume       = {48},
  pages        = {10--20},
  year         = {2015},
  url          = {https://doi.org/10.1016/j.vlsi.2014.06.001},
  doi          = {10.1016/J.VLSI.2014.06.001},
  timestamp    = {Thu, 23 Jun 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/integration/TrikiWAP15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/VaisbandF15,
  author       = {Inna Vaisband and
                  Eby G. Friedman},
  title        = {Energy efficient adaptive clustering of on-chip power delivery systems},
  journal      = {Integr.},
  volume       = {48},
  pages        = {1--9},
  year         = {2015},
  url          = {https://doi.org/10.1016/j.vlsi.2014.06.003},
  doi          = {10.1016/J.VLSI.2014.06.003},
  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/integration/VaisbandF15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/WimerS15,
  author       = {Shmuel Wimer and
                  Amnon Stanislavsky},
  title        = {Energy efficient hybrid adder architecture},
  journal      = {Integr.},
  volume       = {48},
  pages        = {109--115},
  year         = {2015},
  url          = {https://doi.org/10.1016/j.vlsi.2014.06.002},
  doi          = {10.1016/J.VLSI.2014.06.002},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/WimerS15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/Yan15,
  author       = {Jin{-}Tai Yan},
  title        = {Length-constrained escape routing of differential pairs},
  journal      = {Integr.},
  volume       = {48},
  pages        = {158--169},
  year         = {2015},
  url          = {https://doi.org/10.1016/j.vlsi.2014.07.006},
  doi          = {10.1016/J.VLSI.2014.07.006},
  timestamp    = {Sat, 09 Apr 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/integration/Yan15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/YaoYCZS15,
  author       = {Hailong Yao and
                  Fan Yang and
                  Yici Cai and
                  Qiang Zhou and
                  Chiu{-}Wing Sham},
  title        = {{SIAR:} Customized real-time interactive router for analog circuits},
  journal      = {Integr.},
  volume       = {48},
  pages        = {170--182},
  year         = {2015},
  url          = {https://doi.org/10.1016/j.vlsi.2014.03.001},
  doi          = {10.1016/J.VLSI.2014.03.001},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/YaoYCZS15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/ZhouLZYYZ15,
  author       = {Xingbao Zhou and
                  Wai{-}Shing Luk and
                  Hai Zhou and
                  Fan Yang and
                  Changhao Yan and
                  Xuan Zeng},
  title        = {Multi-parameter clock skew scheduling},
  journal      = {Integr.},
  volume       = {48},
  pages        = {129--137},
  year         = {2015},
  url          = {https://doi.org/10.1016/j.vlsi.2014.07.005},
  doi          = {10.1016/J.VLSI.2014.07.005},
  timestamp    = {Wed, 16 Aug 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/integration/ZhouLZYYZ15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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