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@inproceedings{DBLP:conf/slip/ChittamuruTP17,
  author       = {Sai Vineel Reddy Chittamuru and
                  Ishan G. Thakkar and
                  Sudeep Pasricha},
  title        = {Analyzing voltage bias and temperature induced aging effects in photonic
                  interconnects for manycore computing},
  booktitle    = {{ACM/IEEE} 2017 International Workshop on System Level Interconnect
                  Prediction, {SLIP} 2017, Austin, TX, USA, June 17, 2017},
  pages        = {1--8},
  publisher    = {{IEEE} Computer Society},
  year         = {2017},
  url          = {https://doi.org/10.1109/SLIP.2017.7974906},
  doi          = {10.1109/SLIP.2017.7974906},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/slip/ChittamuruTP17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/slip/Chow0TY17,
  author       = {Wing{-}Kai Chow and
                  Jian Kuang and
                  Peishan Tu and
                  Evangeline F. Y. Young},
  title        = {Fence-aware detailed-routability driven placement},
  booktitle    = {{ACM/IEEE} 2017 International Workshop on System Level Interconnect
                  Prediction, {SLIP} 2017, Austin, TX, USA, June 17, 2017},
  pages        = {1--7},
  publisher    = {{IEEE} Computer Society},
  year         = {2017},
  url          = {https://doi.org/10.1109/SLIP.2017.7974905},
  doi          = {10.1109/SLIP.2017.7974905},
  timestamp    = {Tue, 18 Jul 2017 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/slip/Chow0TY17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/slip/DaulagalaS17,
  author       = {Isuru Daulagala and
                  Ioannis Savidis},
  title        = {Clock tree synthesis for heterogeneous 3-D integrated circuits},
  booktitle    = {{ACM/IEEE} 2017 International Workshop on System Level Interconnect
                  Prediction, {SLIP} 2017, Austin, TX, USA, June 17, 2017},
  pages        = {1--6},
  publisher    = {{IEEE} Computer Society},
  year         = {2017},
  url          = {https://doi.org/10.1109/SLIP.2017.7974911},
  doi          = {10.1109/SLIP.2017.7974911},
  timestamp    = {Tue, 18 Jul 2017 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/slip/DaulagalaS17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/slip/FilippiniT17,
  author       = {Leo Filippini and
                  Baris Taskin},
  title        = {A charge recovery logic system bus},
  booktitle    = {{ACM/IEEE} 2017 International Workshop on System Level Interconnect
                  Prediction, {SLIP} 2017, Austin, TX, USA, June 17, 2017},
  pages        = {1--4},
  publisher    = {{IEEE} Computer Society},
  year         = {2017},
  url          = {https://doi.org/10.1109/SLIP.2017.7974909},
  doi          = {10.1109/SLIP.2017.7974909},
  timestamp    = {Fri, 30 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/slip/FilippiniT17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/slip/HuangXYC17,
  author       = {Jinglei Huang and
                  Xiaodong Xu and
                  Lan Yao and
                  Song Chen},
  title        = {Reconfigurable topology synthesis for application-specific noc on
                  partially dynamically reconfigurable FPGAs},
  booktitle    = {{ACM/IEEE} 2017 International Workshop on System Level Interconnect
                  Prediction, {SLIP} 2017, Austin, TX, USA, June 17, 2017},
  pages        = {1--8},
  publisher    = {{IEEE} Computer Society},
  year         = {2017},
  url          = {https://doi.org/10.1109/SLIP.2017.7974907},
  doi          = {10.1109/SLIP.2017.7974907},
  timestamp    = {Sat, 08 Sep 2018 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/slip/HuangXYC17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/slip/LernerLT17,
  author       = {Scott Lerner and
                  Eric Leggett and
                  Baris Taskin},
  title        = {Slew-down: analysis of slew relaxation for low-impact clock buffers},
  booktitle    = {{ACM/IEEE} 2017 International Workshop on System Level Interconnect
                  Prediction, {SLIP} 2017, Austin, TX, USA, June 17, 2017},
  pages        = {1--4},
  publisher    = {{IEEE} Computer Society},
  year         = {2017},
  url          = {https://doi.org/10.1109/SLIP.2017.7974910},
  doi          = {10.1109/SLIP.2017.7974910},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/slip/LernerLT17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/slip/Schlichtmann17,
  author       = {Ulf Schlichtmann},
  title        = {Frontiers of timing},
  booktitle    = {{ACM/IEEE} 2017 International Workshop on System Level Interconnect
                  Prediction, {SLIP} 2017, Austin, TX, USA, June 17, 2017},
  pages        = {1--4},
  publisher    = {{IEEE} Computer Society},
  year         = {2017},
  url          = {https://doi.org/10.1109/SLIP.2017.7974912},
  doi          = {10.1109/SLIP.2017.7974912},
  timestamp    = {Mon, 16 Sep 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/slip/Schlichtmann17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/slip/TuCY17,
  author       = {Peishan Tu and
                  Wing{-}Kai Chow and
                  Evangeline F. Y. Young},
  title        = {Timing driven routing tree construction},
  booktitle    = {{ACM/IEEE} 2017 International Workshop on System Level Interconnect
                  Prediction, {SLIP} 2017, Austin, TX, USA, June 17, 2017},
  pages        = {1--8},
  publisher    = {{IEEE} Computer Society},
  year         = {2017},
  url          = {https://doi.org/10.1109/SLIP.2017.7974908},
  doi          = {10.1109/SLIP.2017.7974908},
  timestamp    = {Tue, 18 Jul 2017 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/slip/TuCY17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@proceedings{DBLP:conf/slip/2017,
  title        = {{ACM/IEEE} 2017 International Workshop on System Level Interconnect
                  Prediction, {SLIP} 2017, Austin, TX, USA, June 17, 2017},
  publisher    = {{IEEE} Computer Society},
  year         = {2017},
  url          = {https://ieeexplore.ieee.org/xpl/conhome/7974634/proceeding},
  isbn         = {978-1-5386-1536-2},
  timestamp    = {Wed, 16 Oct 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/slip/2017.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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