Stop the war!Остановите войну!
for scientists:
default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDSearch dblp for Publications
export results for "toc:db/conf/patmos/patmos2018.bht:"
download as .bib file
@inproceedings{DBLP:conf/patmos/AalsaudASXY18,
author = {Ali Aalsaud and
Haider Alrudainy and
Rishad A. Shafik and
Fei Xia and
Alex Yakovlev},
title = {MEMS-Based Runtime Idle Energy Minimization for Bursty Workloads in
Heterogeneous Many-Core Systems},
booktitle = {28th International Symposium on Power and Timing Modeling, Optimization
and Simulation, {PATMOS} 2018, Platja d'Aro, Spain, July 2-4, 2018},
pages = {198--205},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/PATMOS.2018.8464152},
doi = {10.1109/PATMOS.2018.8464152},
timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/AalsaudASXY18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/AalsaudRXSY18,
author = {Ali Aalsaud and
Ashur Rafiev and
Fei Xia and
Rishad A. Shafik and
Alex Yakovlev},
title = {Model-Free Runtime Management of Concurrent Workloads for Energy-Efficient
Many-Core Heterogeneous Systems},
booktitle = {28th International Symposium on Power and Timing Modeling, Optimization
and Simulation, {PATMOS} 2018, Platja d'Aro, Spain, July 2-4, 2018},
pages = {206--213},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/PATMOS.2018.8464142},
doi = {10.1109/PATMOS.2018.8464142},
timestamp = {Tue, 18 Sep 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/AalsaudRXSY18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/AmayaGR18,
author = {Andres Amaya and
Luis E. Rueda G. and
Elkim Roa},
title = {A Multi-Level Power-on Reset for Fine-Grained Power Management},
booktitle = {28th International Symposium on Power and Timing Modeling, Optimization
and Simulation, {PATMOS} 2018, Platja d'Aro, Spain, July 2-4, 2018},
pages = {129--132},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/PATMOS.2018.8464167},
doi = {10.1109/PATMOS.2018.8464167},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/AmayaGR18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/AmeurAVF18,
author = {Amal Ben Ameur and
Michel Auguin and
Fran{\c{c}}ois Verdier and
Valerio Frascolla},
title = {Mobile Terminals System-Level Memory Exploratio for Power and Performance
Optimization},
booktitle = {28th International Symposium on Power and Timing Modeling, Optimization
and Simulation, {PATMOS} 2018, Platja d'Aro, Spain, July 2-4, 2018},
pages = {23--28},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/PATMOS.2018.8464166},
doi = {10.1109/PATMOS.2018.8464166},
timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/AmeurAVF18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/AnagnostouGHFGT18,
author = {P. Anagnostou and
Andres Gomez and
Pascal A. Hager and
Hamed Fatemi and
Jos{\'{e}} Pineda de Gyvez and
Lothar Thiele and
Luca Benini},
title = {Torpor: {A} Power-Aware {HW} Scheduler for Energy Harvesting IoT SoCs},
booktitle = {28th International Symposium on Power and Timing Modeling, Optimization
and Simulation, {PATMOS} 2018, Platja d'Aro, Spain, July 2-4, 2018},
pages = {54--61},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/PATMOS.2018.8464146},
doi = {10.1109/PATMOS.2018.8464146},
timestamp = {Wed, 08 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/AnagnostouGHFGT18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/AparicioI18,
author = {Hernan Aparicio and
Pablo Ituero},
title = {A 40nm Critical Path Monitor for the Detection of Setup and Hold Time
Violations},
booktitle = {28th International Symposium on Power and Timing Modeling, Optimization
and Simulation, {PATMOS} 2018, Platja d'Aro, Spain, July 2-4, 2018},
pages = {13--18},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/PATMOS.2018.8464155},
doi = {10.1109/PATMOS.2018.8464155},
timestamp = {Tue, 18 Sep 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/AparicioI18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/ArribaCG18,
author = {Guillem Martinez de Arriba and
Ertugrul Coskuner and
Joan J. Garcia{-}Garcia},
title = {Enhanced {RF} Harvesting System by the Utilization of Resonant Cavities},
booktitle = {28th International Symposium on Power and Timing Modeling, Optimization
and Simulation, {PATMOS} 2018, Platja d'Aro, Spain, July 2-4, 2018},
pages = {29--31},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/PATMOS.2018.8464175},
doi = {10.1109/PATMOS.2018.8464175},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/ArribaCG18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/BahramaliL18,
author = {Asghar Bahramali and
Marisa L{\'{o}}pez{-}Vallejo},
title = {A Temperature Variation Tolerant CMOS-Only Voltage Reference for {RFID}
Applications},
booktitle = {28th International Symposium on Power and Timing Modeling, Optimization
and Simulation, {PATMOS} 2018, Platja d'Aro, Spain, July 2-4, 2018},
pages = {62--67},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/PATMOS.2018.8464164},
doi = {10.1109/PATMOS.2018.8464164},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/BahramaliL18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/BambergJSPG18,
author = {Lennart Bamberg and
Jan Moritz Joseph and
Robert Schmidt and
Thilo Pionteck and
Alberto Garc{\'{\i}}a Ortiz},
title = {Coding-aware Link Energy Estimation for 2D and 3D Networks-on-Chip
with Virtual Channels},
booktitle = {28th International Symposium on Power and Timing Modeling, Optimization
and Simulation, {PATMOS} 2018, Platja d'Aro, Spain, July 2-4, 2018},
pages = {222--228},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/PATMOS.2018.8464171},
doi = {10.1109/PATMOS.2018.8464171},
timestamp = {Thu, 16 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/BambergJSPG18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/BambergO18,
author = {Lennart Bamberg and
Alberto Garc{\'{\i}}a Ortiz},
title = {Exploiting Temporal Misalignment to Optimize the Interconnect Performance
for 3D Integration},
booktitle = {28th International Symposium on Power and Timing Modeling, Optimization
and Simulation, {PATMOS} 2018, Platja d'Aro, Spain, July 2-4, 2018},
pages = {214--221},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/PATMOS.2018.8464172},
doi = {10.1109/PATMOS.2018.8464172},
timestamp = {Wed, 25 Sep 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/BambergO18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/BarajasAMMRMRPN18,
author = {Enrique Barajas and
Xavier Aragon{\`{e}}s and
Diego Mateo and
Francesc Moll and
Antonio Rubio and
Javier Mart{\'{\i}}n{-}Mart{\'{\i}}nez and
Rosana Rodr{\'{\i}}guez and
Marc Porti and
Montserrat Nafr{\'{\i}}a and
Rafael Castro{-}L{\'{o}}pez and
Elisenda Roca and
Francisco V. Fern{\'{a}}ndez},
title = {Analysis of Body Bias and RTN-Induced Frequency Shift of Low Voltage
Ring Oscillators in {FDSOI} Technology},
booktitle = {28th International Symposium on Power and Timing Modeling, Optimization
and Simulation, {PATMOS} 2018, Platja d'Aro, Spain, July 2-4, 2018},
pages = {82--87},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/PATMOS.2018.8464145},
doi = {10.1109/PATMOS.2018.8464145},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/BarajasAMMRMRPN18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/BelloHEZ18,
author = {Ibrahim A. Bello and
Basel Halak and
Mohammed El{-}Hajjar and
Mark Zwolinski},
title = {Hardware Implementation of a Low-Power K-Best {MIMO} Detector Based
on a Hybrid Merge Network},
booktitle = {28th International Symposium on Power and Timing Modeling, Optimization
and Simulation, {PATMOS} 2018, Platja d'Aro, Spain, July 2-4, 2018},
pages = {191--197},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/PATMOS.2018.8464169},
doi = {10.1109/PATMOS.2018.8464169},
timestamp = {Wed, 25 Sep 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/BelloHEZ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/BlancoMCM18,
author = {Roberto Blanco and
Pedro Malag{\'{o}}n and
Juan J. Cilla and
Jos{\'{e}} Manuel Moya},
title = {Multiclass Network Attack Classifier Using {CNN} Tuned with Genetic
Algorithms},
booktitle = {28th International Symposium on Power and Timing Modeling, Optimization
and Simulation, {PATMOS} 2018, Platja d'Aro, Spain, July 2-4, 2018},
pages = {177--182},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/PATMOS.2018.8463997},
doi = {10.1109/PATMOS.2018.8463997},
timestamp = {Sat, 05 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/BlancoMCM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/BuffeteauMJ18,
author = {David Buffeteau and
Dominique Morche and
Jose{-}Luis Gonzalez Jimenez},
title = {{VCO} Verilog {AMS} Model for Fast Simulation in VCO-Based {ADC}},
booktitle = {28th International Symposium on Power and Timing Modeling, Optimization
and Simulation, {PATMOS} 2018, Platja d'Aro, Spain, July 2-4, 2018},
pages = {19--22},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/PATMOS.2018.8463999},
doi = {10.1109/PATMOS.2018.8463999},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/patmos/BuffeteauMJ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/CabaRDBAL18,
author = {Juli{\'{a}}n Caba and
Fernando Rinc{\'{o}}n and
Julio Dondo and
Jes{\'{u}}s Barba and
Manuel J. Abaldea and
Juan Carlos L{\'{o}}pez},
title = {Testing Framework for in-Hardware Verification of the Hardware Modules
Generated Using {HLS}},
booktitle = {28th International Symposium on Power and Timing Modeling, Optimization
and Simulation, {PATMOS} 2018, Platja d'Aro, Spain, July 2-4, 2018},
pages = {103--110},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/PATMOS.2018.8464157},
doi = {10.1109/PATMOS.2018.8464157},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/patmos/CabaRDBAL18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/DekimpeXSFB18,
author = {Remi Dekimpe and
Pengcheng Xu and
Maxime Schramme and
Denis Flandre and
David Bol},
title = {A Battery-Less {BLE} IoT Motion Detector Supplied by 2.45-GHz Wireless
Power Transfer},
booktitle = {28th International Symposium on Power and Timing Modeling, Optimization
and Simulation, {PATMOS} 2018, Platja d'Aro, Spain, July 2-4, 2018},
pages = {68--75},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/PATMOS.2018.8464144},
doi = {10.1109/PATMOS.2018.8464144},
timestamp = {Wed, 25 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/DekimpeXSFB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/GardeLOR18,
author = {M. Pilar Garde and
Antonio J. L{\'{o}}pez{-}Mart{\'{\i}}n and
Daniel Orradre and
Jaime Ram{\'{\i}}rez{-}Angulo},
title = {Ultra-Low Power Subthreshold Quasi Floating Gate {CMOS} Logic Family
for Energy Harvesting},
booktitle = {28th International Symposium on Power and Timing Modeling, Optimization
and Simulation, {PATMOS} 2018, Platja d'Aro, Spain, July 2-4, 2018},
pages = {118--122},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/PATMOS.2018.8463995},
doi = {10.1109/PATMOS.2018.8463995},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/GardeLOR18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/Georgoulopoulos18,
author = {Nikolaos Georgoulopoulos and
Ioannis Giannou and
Alkiviadis A. Hatzopoulos},
title = {UVM-Based Verification of a Mixed-Signal Design Using SystemVerilog},
booktitle = {28th International Symposium on Power and Timing Modeling, Optimization
and Simulation, {PATMOS} 2018, Platja d'Aro, Spain, July 2-4, 2018},
pages = {97--102},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/PATMOS.2018.8464148},
doi = {10.1109/PATMOS.2018.8464148},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/Georgoulopoulos18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/GoldbrunnerWH18,
author = {Thomas Goldbrunner and
Thomas Wild and
Andreas Herkersdorf},
title = {Memory Access Pattern Profiling for Streaming Applications Based on
{MATLAB} Models},
booktitle = {28th International Symposium on Power and Timing Modeling, Optimization
and Simulation, {PATMOS} 2018, Platja d'Aro, Spain, July 2-4, 2018},
pages = {32--38},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/PATMOS.2018.8464151},
doi = {10.1109/PATMOS.2018.8464151},
timestamp = {Tue, 18 Sep 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/GoldbrunnerWH18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/GoudosKNMN18,
author = {Sotirios K. Goudos and
Nikolaos Karagiorgos and
Maria Ntogramatzi and
Ioannis Messaris and
Spyridon Nikolaidis},
title = {Evaluation of an Artificial Neural Network Approach for Timing Modeling
of {CMOS} Gates},
booktitle = {28th International Symposium on Power and Timing Modeling, Optimization
and Simulation, {PATMOS} 2018, Platja d'Aro, Spain, July 2-4, 2018},
pages = {169--176},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/PATMOS.2018.8464162},
doi = {10.1109/PATMOS.2018.8464162},
timestamp = {Tue, 04 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/GoudosKNMN18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/HerreraWB18,
author = {Mois{\'{e}}s Herrera and
Tingyu Wang and
Peter A. Beerel},
title = {Blade-OC Asynchronous Resilient Template {\textdaggerdbl} This research
has been supported in part by {NSF} Grant {\#}1619415},
booktitle = {28th International Symposium on Power and Timing Modeling, Optimization
and Simulation, {PATMOS} 2018, Platja d'Aro, Spain, July 2-4, 2018},
pages = {147--154},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/PATMOS.2018.8463998},
doi = {10.1109/PATMOS.2018.8463998},
timestamp = {Tue, 18 Sep 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/HerreraWB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/IslamO18,
author = {A. K. M. Mahfuzul Islam and
Hidetoshi Onodera},
title = {Worst-Case Performance Analysis Under Random Telegraph Noise Induced
Threshold Voltage Variability},
booktitle = {28th International Symposium on Power and Timing Modeling, Optimization
and Simulation, {PATMOS} 2018, Platja d'Aro, Spain, July 2-4, 2018},
pages = {140--146},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/PATMOS.2018.8464147},
doi = {10.1109/PATMOS.2018.8464147},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/patmos/IslamO18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/JevticYK18,
author = {Ruzica Jevtic and
Marko Ylitolva and
Lauri Koskinen},
title = {Reconfigurable Switched Capacitor {DC-DC} Converter for Improved Security
in IoT Devices},
booktitle = {28th International Symposium on Power and Timing Modeling, Optimization
and Simulation, {PATMOS} 2018, Platja d'Aro, Spain, July 2-4, 2018},
pages = {243--247},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/PATMOS.2018.8464158},
doi = {10.1109/PATMOS.2018.8464158},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/patmos/JevticYK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/JurimagiUJRDK18,
author = {Lembit Jurimagi and
Raimund Ubar and
Maksim Jenihhin and
Jaan Raik and
Sergei Devadze and
Sergei Kostin},
title = {Hierarchical Timing-Critical Paths Analysis in Sequential Circuits},
booktitle = {28th International Symposium on Power and Timing Modeling, Optimization
and Simulation, {PATMOS} 2018, Platja d'Aro, Spain, July 2-4, 2018},
pages = {1--6},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/PATMOS.2018.8464176},
doi = {10.1109/PATMOS.2018.8464176},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/JurimagiUJRDK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/KheirallahGAD18,
author = {Rida Kheirallah and
Jean{-}Marc Galli{\`{e}}re and
Nadine Az{\'{e}}mard and
Gilles R. Ducharme},
title = {Combined Analysis of Supply Voltage and Body-Bias Voltage for Energy
Management},
booktitle = {28th International Symposium on Power and Timing Modeling, Optimization
and Simulation, {PATMOS} 2018, Platja d'Aro, Spain, July 2-4, 2018},
pages = {88--91},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/PATMOS.2018.8464159},
doi = {10.1109/PATMOS.2018.8464159},
timestamp = {Fri, 19 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/KheirallahGAD18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/KnodtelSLRF18,
author = {Johannes Kn{\"{o}}dtel and
Wolffhardt Schwabe and
Tobias Lieske and
Marc Reichenbach and
Dietmar Fey},
title = {A Novel Methodology for Evaluating the Energy Consumption of {IP}
Blocks in System-Level Designs},
booktitle = {28th International Symposium on Power and Timing Modeling, Optimization
and Simulation, {PATMOS} 2018, Platja d'Aro, Spain, July 2-4, 2018},
pages = {46--53},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/PATMOS.2018.8464149},
doi = {10.1109/PATMOS.2018.8464149},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/KnodtelSLRF18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/MaheshwariBK18,
author = {Sachin Maheshwari and
Vivian A. Bartlett and
Izzet Kale},
title = {VHDL-Based Modelling Approach for the Digital Simulation of 4-Phase
Adiabatic Logic Design},
booktitle = {28th International Symposium on Power and Timing Modeling, Optimization
and Simulation, {PATMOS} 2018, Platja d'Aro, Spain, July 2-4, 2018},
pages = {111--117},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/PATMOS.2018.8464140},
doi = {10.1109/PATMOS.2018.8464140},
timestamp = {Tue, 18 Sep 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/MaheshwariBK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/MispanDHZ18,
author = {Mohd Syafiq Mispan and
Shengyu Duan and
Basel Halak and
Mark Zwolinski},
title = {A Reliable {PUF} in a Dual Function {SRAM}},
booktitle = {28th International Symposium on Power and Timing Modeling, Optimization
and Simulation, {PATMOS} 2018, Platja d'Aro, Spain, July 2-4, 2018},
pages = {76--81},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/PATMOS.2018.8464143},
doi = {10.1109/PATMOS.2018.8464143},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/MispanDHZ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/OikonomouTKT18,
author = {Konstantinos Oikonomou and
Orestis Theodorakopoulos and
Georgios Keramidas and
Georgios Theodoridis},
title = {Backlight Compensation Algorithms to Improve Power Consumption in
{LED-} {LCD} Displays},
booktitle = {28th International Symposium on Power and Timing Modeling, Optimization
and Simulation, {PATMOS} 2018, Platja d'Aro, Spain, July 2-4, 2018},
pages = {254--260},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/PATMOS.2018.8464154},
doi = {10.1109/PATMOS.2018.8464154},
timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/OikonomouTKT18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/PaliourasKO18,
author = {Vassilis Paliouras and
Konstantina Karagianni and
Yann Oster},
title = {Quantitative Evaluation of Certain {SET} Mitigation Techniques for
Multiply-Accumulate Circuits and State Machines},
booktitle = {28th International Symposium on Power and Timing Modeling, Optimization
and Simulation, {PATMOS} 2018, Platja d'Aro, Spain, July 2-4, 2018},
pages = {183--190},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/PATMOS.2018.8464165},
doi = {10.1109/PATMOS.2018.8464165},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/PaliourasKO18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/PatrigeonBT18,
author = {Guillaume Patrigeon and
Pascal Benoit and
Lionel Torres},
title = {FPGA-Based Platform for Fast Accurate Evaluation of Ultra Low Power
SoC},
booktitle = {28th International Symposium on Power and Timing Modeling, Optimization
and Simulation, {PATMOS} 2018, Platja d'Aro, Spain, July 2-4, 2018},
pages = {123--128},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/PATMOS.2018.8464173},
doi = {10.1109/PATMOS.2018.8464173},
timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/PatrigeonBT18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/RaghavBK18,
author = {Himadri Singh Raghav and
Vivian A. Bartlett and
Izzet Kale},
title = {Symmetric Power Analysis Attack Resilient Adiabatic Logic for Smartcard
Applications},
booktitle = {28th International Symposium on Power and Timing Modeling, Optimization
and Simulation, {PATMOS} 2018, Platja d'Aro, Spain, July 2-4, 2018},
pages = {39--45},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/PATMOS.2018.8463996},
doi = {10.1109/PATMOS.2018.8463996},
timestamp = {Tue, 18 Sep 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/RaghavBK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/SegmanovicRMJS18,
author = {Filip Segmanovic and
Frederic Roger and
Gerald Meinhard and
Ingrid Jonak{-}Auer and
Tomislav Suligoj},
title = {Optical and Electrical Simulations of Radiation-Hard Photodiode in
0.35{\(\mu\)}M High-Voltage {CMOS} Technology},
booktitle = {28th International Symposium on Power and Timing Modeling, Optimization
and Simulation, {PATMOS} 2018, Platja d'Aro, Spain, July 2-4, 2018},
pages = {92--96},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/PATMOS.2018.8464156},
doi = {10.1109/PATMOS.2018.8464156},
timestamp = {Tue, 18 Sep 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/SegmanovicRMJS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/SierraCC18,
author = {Roberto Sierra and
Carlos Carreras and
Gabriel Caffarena},
title = {Automated Timing Characterization of High-Performance Macroblocks
for Latency Insensitive {FPGA} Designs},
booktitle = {28th International Symposium on Power and Timing Modeling, Optimization
and Simulation, {PATMOS} 2018, Platja d'Aro, Spain, July 2-4, 2018},
pages = {7--12},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/PATMOS.2018.8464170},
doi = {10.1109/PATMOS.2018.8464170},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/patmos/SierraCC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/Skibinsky-Gitlin18,
author = {Erik S. Skibinsky{-}Gitlin and
Miquel L. Alomar and
Eugeni Isern and
Miquel Roca and
Vincent Canals and
Josep L. Rossell{\'{o}}},
title = {Reservoir Computing Hardware for Time Series Forecasting},
booktitle = {28th International Symposium on Power and Timing Modeling, Optimization
and Simulation, {PATMOS} 2018, Platja d'Aro, Spain, July 2-4, 2018},
pages = {133--139},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/PATMOS.2018.8463994},
doi = {10.1109/PATMOS.2018.8463994},
timestamp = {Wed, 20 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/Skibinsky-Gitlin18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/Terra-SanchezA18,
author = {Erica Tena{-}S{\'{a}}nchez and
Antonio J. Acosta},
title = {Effect of Temperature Variation in Experimental {DPA} and {DEMA} Attacks},
booktitle = {28th International Symposium on Power and Timing Modeling, Optimization
and Simulation, {PATMOS} 2018, Platja d'Aro, Spain, July 2-4, 2018},
pages = {163--168},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/PATMOS.2018.8463993},
doi = {10.1109/PATMOS.2018.8463993},
timestamp = {Fri, 03 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/Terra-SanchezA18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/VandenabeeleUDM18,
author = {Thomas Vandenabeele and
Roel Uytterhoeven and
Wim Dehaene and
Nele Mentens},
title = {A Systematic Performance Comparison of Ultra Low-Power {AES} S-Boxes},
booktitle = {28th International Symposium on Power and Timing Modeling, Optimization
and Simulation, {PATMOS} 2018, Platja d'Aro, Spain, July 2-4, 2018},
pages = {248--253},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/PATMOS.2018.8464160},
doi = {10.1109/PATMOS.2018.8464160},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/VandenabeeleUDM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/XuSIO18,
author = {Hongjie Xu and
Jun Shiomi and
Tohru Ishihara and
Hidetoshi Onodera},
title = {Maximizing Energy Efficiency of on-Chip Caches Exploiting Hybrid Memory
Structure},
booktitle = {28th International Symposium on Power and Timing Modeling, Optimization
and Simulation, {PATMOS} 2018, Platja d'Aro, Spain, July 2-4, 2018},
pages = {237--242},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/PATMOS.2018.8464141},
doi = {10.1109/PATMOS.2018.8464141},
timestamp = {Tue, 18 Sep 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/XuSIO18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/ZamanSCM18,
author = {Monir Zaman and
Mustafa M. Shihab and
Ayse K. Coskun and
Yiorgos Makris},
title = {Towards a Cross-Layer Framework for Accurate Power Modeling of Microprocessor
Designs},
booktitle = {28th International Symposium on Power and Timing Modeling, Optimization
and Simulation, {PATMOS} 2018, Platja d'Aro, Spain, July 2-4, 2018},
pages = {229--236},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/PATMOS.2018.8464153},
doi = {10.1109/PATMOS.2018.8464153},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/ZamanSCM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/ZhaoHY18,
author = {Yi Zhao and
Cong Hao and
Takeshi Yoshimura},
title = {{TSV} Assignment of Thermal and Wirelength Optimization for 3D-IC
Routing},
booktitle = {28th International Symposium on Power and Timing Modeling, Optimization
and Simulation, {PATMOS} 2018, Platja d'Aro, Spain, July 2-4, 2018},
pages = {155--162},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/PATMOS.2018.8464161},
doi = {10.1109/PATMOS.2018.8464161},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/ZhaoHY18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/patmos/2018,
title = {28th International Symposium on Power and Timing Modeling, Optimization
and Simulation, {PATMOS} 2018, Platja d'Aro, Spain, July 2-4, 2018},
publisher = {{IEEE}},
year = {2018},
url = {https://ieeexplore.ieee.org/xpl/conhome/8450936/proceeding},
isbn = {978-1-5386-6365-3},
timestamp = {Wed, 16 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/2018.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
a service of 
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
retrieved on 2024-04-24 18:57 CEST from data curated by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
