Stop the war!Остановите войну!
for scientists:
default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDSearch dblp for Publications
export results for "toc:db/conf/patmos/patmos2008.bht:"
download as .bib file
@proceedings{DBLP:conf/patmos/2008,
editor = {Lars Svensson and
Jos{\'{e}} Monteiro},
title = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization
and Simulation, 18th International Workshop, {PATMOS} 2008, Lisbon,
Portugal, September 10-12, 2008. Revised Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {5349},
publisher = {Springer},
year = {2009},
url = {https://doi.org/10.1007/978-3-540-95948-9},
doi = {10.1007/978-3-540-95948-9},
isbn = {978-3-540-95947-2},
timestamp = {Wed, 23 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/patmos/2008.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/AgostinelliAES08,
author = {Matteo Agostinelli and
Massimo Alioto and
David Esseni and
Luca Selmi},
editor = {Lars Svensson and
Jos{\'{e}} Monteiro},
title = {Design and Evaluation of Mixed 3T-4T FinFET Stacks for Leakage Reduction},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization
and Simulation, 18th International Workshop, {PATMOS} 2008, Lisbon,
Portugal, September 10-12, 2008. Revised Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {5349},
pages = {31--41},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-95948-9\_4},
doi = {10.1007/978-3-540-95948-9\_4},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/AgostinelliAES08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/AizikKZRA08,
author = {Yoni Aizik and
Gila Kamhi and
Yael Zbar and
Hadas Ronen and
Muhammad Abozaed},
editor = {Lars Svensson and
Jos{\'{e}} Monteiro},
title = {Power-Aware Design via Micro-architectural Link to Implementation},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization
and Simulation, 18th International Workshop, {PATMOS} 2008, Lisbon,
Portugal, September 10-12, 2008. Revised Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {5349},
pages = {72--81},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-95948-9\_8},
doi = {10.1007/978-3-540-95948-9\_8},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/AizikKZRA08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/AliotoPP08,
author = {Massimo Alioto and
Gaetano Palumbo and
Melita Pennisi},
editor = {Lars Svensson and
Jos{\'{e}} Monteiro},
title = {Understanding the Effect of Intradie Random Process Variations in
Nanometer Domino Logic},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization
and Simulation, 18th International Workshop, {PATMOS} 2008, Lisbon,
Portugal, September 10-12, 2008. Revised Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {5349},
pages = {136--145},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-95948-9\_14},
doi = {10.1007/978-3-540-95948-9\_14},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/AliotoPP08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/BauerGS08,
author = {Florian Bauer and
Georg Georgakos and
Doris Schmitt{-}Landsiedel},
editor = {Lars Svensson and
Jos{\'{e}} Monteiro},
title = {A Design Space Comparison of 6T and 8T {SRAM} Core-Cells},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization
and Simulation, 18th International Workshop, {PATMOS} 2008, Lisbon,
Portugal, September 10-12, 2008. Revised Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {5349},
pages = {116--125},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-95948-9\_12},
doi = {10.1007/978-3-540-95948-9\_12},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/BauerGS08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/BerekovicBAV08,
author = {Mladen Berekovic and
Frank Bouwens and
Tom Vander Aa and
Diederik Verkest},
editor = {Lars Svensson and
Jos{\'{e}} Monteiro},
title = {Interconnect Power Analysis for a Coarse-Grained Reconfigurable Array
Processor},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization
and Simulation, 18th International Workshop, {PATMOS} 2008, Lisbon,
Portugal, September 10-12, 2008. Revised Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {5349},
pages = {449--457},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-95948-9\_45},
doi = {10.1007/978-3-540-95948-9\_45},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/BerekovicBAV08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/BoroujeniPL08,
author = {Bahman Kheradmand Boroujeni and
Christian Piguet and
Yusuf Leblebici},
editor = {Lars Svensson and
Jos{\'{e}} Monteiro},
title = {Reverse Vgs Static {CMOS} (RVGS-SCMOS); {A} New Technique for Dynamically
Compensating the Process Variations in Sub-threshold Designs},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization
and Simulation, 18th International Workshop, {PATMOS} 2008, Lisbon,
Portugal, September 10-12, 2008. Revised Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {5349},
pages = {11--20},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-95948-9\_2},
doi = {10.1007/978-3-540-95948-9\_2},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/BoroujeniPL08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/BoselliCLT08,
author = {Giorgio Boselli and
Valentina Ciriani and
Valentino Liberali and
Gabriella Trucco},
editor = {Lars Svensson and
Jos{\'{e}} Monteiro},
title = {A Comparison between Two Logic Synthesis Forms from Digital Switching
Noise Viewpoint},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization
and Simulation, 18th International Workshop, {PATMOS} 2008, Lisbon,
Portugal, September 10-12, 2008. Revised Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {5349},
pages = {237--246},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-95948-9\_24},
doi = {10.1007/978-3-540-95948-9\_24},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/BoselliCLT08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/BucciLSST08,
author = {Marco Bucci and
Raimondo Luzzi and
Giuseppe Scotti and
Andrea Simonetti and
Alessandro Trifiletti},
editor = {Lars Svensson and
Jos{\'{e}} Monteiro},
title = {Differential Capacitance Analysis},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization
and Simulation, 18th International Workshop, {PATMOS} 2008, Lisbon,
Portugal, September 10-12, 2008. Revised Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {5349},
pages = {338--347},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-95948-9\_34},
doi = {10.1007/978-3-540-95948-9\_34},
timestamp = {Thu, 15 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/BucciLSST08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/CallouMANTO08,
author = {Gustavo Rau de Almeida Callou and
Paulo Romero Martins Maciel and
Ermeson Carneiro de Andrade and
Bruno Costa e Silva Nogueira and
Eduardo Tavares and
Meuse N. Oliveira Jr.},
editor = {Lars Svensson and
Jos{\'{e}} Monteiro},
title = {A Formal Approach for Estimating Embedded System Execution Time and
Energy Consumption},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization
and Simulation, 18th International Workshop, {PATMOS} 2008, Lisbon,
Portugal, September 10-12, 2008. Revised Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {5349},
pages = {379--388},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-95948-9\_38},
doi = {10.1007/978-3-540-95948-9\_38},
timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/CallouMANTO08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/ChenNXZV08,
author = {Howard Chen and
Scott Neely and
Jinjun Xiong and
Vladimir Zolotov and
Chandu Visweswariah},
editor = {Lars Svensson and
Jos{\'{e}} Monteiro},
title = {Statistical Modeling and Analysis of Static Leakage and Dynamic Switching
Power},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization
and Simulation, 18th International Workshop, {PATMOS} 2008, Lisbon,
Portugal, September 10-12, 2008. Revised Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {5349},
pages = {178--187},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-95948-9\_18},
doi = {10.1007/978-3-540-95948-9\_18},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/patmos/ChenNXZV08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/CourtayLSJ08,
author = {Antoine Courtay and
Johann Laurent and
Olivier Sentieys and
Nathalie Julien},
editor = {Lars Svensson and
Jos{\'{e}} Monteiro},
title = {Novel Cross-Transition Elimination Technique Improving Delay and Power
Consumption for On-Chip Buses},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization
and Simulation, 18th International Workshop, {PATMOS} 2008, Lisbon,
Portugal, September 10-12, 2008. Revised Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {5349},
pages = {359--368},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-95948-9\_36},
doi = {10.1007/978-3-540-95948-9\_36},
timestamp = {Mon, 05 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/CourtayLSJ08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/DiasSLBP08,
author = {Nuno Dias and
Marcelino B. Santos and
Floriberto A. Lima and
Beatriz Vieira Borges and
J{\'{u}}lio Paisana},
editor = {Lars Svensson and
Jos{\'{e}} Monteiro},
title = {Monolithic Multi-mode {DC-DC} Converter with Gate Voltage Optimization},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization
and Simulation, 18th International Workshop, {PATMOS} 2008, Lisbon,
Portugal, September 10-12, 2008. Revised Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {5349},
pages = {258--267},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-95948-9\_26},
doi = {10.1007/978-3-540-95948-9\_26},
timestamp = {Tue, 08 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/DiasSLBP08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/DobkinG08,
author = {Rostislav (Reuven) Dobkin and
Ran Ginosar},
editor = {Lars Svensson and
Jos{\'{e}} Monteiro},
title = {Fast Universal Synchronizers},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization
and Simulation, 18th International Workshop, {PATMOS} 2008, Lisbon,
Portugal, September 10-12, 2008. Revised Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {5349},
pages = {199--208},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-95948-9\_20},
doi = {10.1007/978-3-540-95948-9\_20},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/DobkinG08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/Fernandez-NogueiraC08,
author = {Francisco Fern{\'{a}}ndez{-}Nogueira and
Josep Carmona},
editor = {Lars Svensson and
Jos{\'{e}} Monteiro},
title = {Logic Synthesis of Handshake Components Using Structural Clustering
Techniques},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization
and Simulation, 18th International Workshop, {PATMOS} 2008, Lisbon,
Portugal, September 10-12, 2008. Revised Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {5349},
pages = {188--198},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-95948-9\_19},
doi = {10.1007/978-3-540-95948-9\_19},
timestamp = {Thu, 09 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/patmos/Fernandez-NogueiraC08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/FigueiredoA08,
author = {Monica Figueiredo and
Rui L. Aguiar},
editor = {Lars Svensson and
Jos{\'{e}} Monteiro},
title = {A Study on {CMOS} Time Uncertainty with Technology Scaling},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization
and Simulation, 18th International Workshop, {PATMOS} 2008, Lisbon,
Portugal, September 10-12, 2008. Revised Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {5349},
pages = {146--155},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-95948-9\_15},
doi = {10.1007/978-3-540-95948-9\_15},
timestamp = {Thu, 19 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/FigueiredoA08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/FrustaciCPC08,
author = {Fabio Frustaci and
Pasquale Corsonello and
Stefania Perri and
Giuseppe Cocorullo},
editor = {Lars Svensson and
Jos{\'{e}} Monteiro},
title = {A New Dynamic Logic Circuit Design for an Effective Trade-Off between
Noise-Immunity, Performance and Energy Dissipation},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization
and Simulation, 18th International Workshop, {PATMOS} 2008, Lisbon,
Portugal, September 10-12, 2008. Revised Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {5349},
pages = {277--286},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-95948-9\_28},
doi = {10.1007/978-3-540-95948-9\_28},
timestamp = {Mon, 05 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/FrustaciCPC08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/GiacomottoSVO08,
author = {Christophe Giacomotto and
Mandeep Singh and
Milena Vratonjic and
Vojin G. Oklobdzija},
editor = {Lars Svensson and
Jos{\'{e}} Monteiro},
title = {Energy Efficiency of Power-Gating in Low-Power Clocked Storage Elements},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization
and Simulation, 18th International Workshop, {PATMOS} 2008, Lisbon,
Portugal, September 10-12, 2008. Revised Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {5349},
pages = {268--276},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-95948-9\_27},
doi = {10.1007/978-3-540-95948-9\_27},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/GiacomottoSVO08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/Ho08,
author = {Tsung{-}Yi Ho},
editor = {Lars Svensson and
Jos{\'{e}} Monteiro},
title = {A Performance-Driven Multilevel Framework for the X-Based Full-Chip
Router},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization
and Simulation, 18th International Workshop, {PATMOS} 2008, Lisbon,
Portugal, September 10-12, 2008. Revised Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {5349},
pages = {209--218},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-95948-9\_21},
doi = {10.1007/978-3-540-95948-9\_21},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/Ho08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/JevticC08,
author = {Ruzica Jevtic and
Carlos Carreras},
editor = {Lars Svensson and
Jos{\'{e}} Monteiro},
title = {Analytical High-Level Power Model for LUT-Based Components},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization
and Simulation, 18th International Workshop, {PATMOS} 2008, Lisbon,
Portugal, September 10-12, 2008. Revised Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {5349},
pages = {369--378},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-95948-9\_37},
doi = {10.1007/978-3-540-95948-9\_37},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/JevticC08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/KellerM08,
author = {Maurice Keller and
William P. Marnane},
editor = {Lars Svensson and
Jos{\'{e}} Monteiro},
title = {Energy Efficient Elliptic Curve Processor},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization
and Simulation, 18th International Workshop, {PATMOS} 2008, Lisbon,
Portugal, September 10-12, 2008. Revised Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {5349},
pages = {287--296},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-95948-9\_29},
doi = {10.1007/978-3-540-95948-9\_29},
timestamp = {Mon, 05 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/KellerM08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/KisslerSHT08,
author = {Dmitrij Kissler and
Andreas Strawetz and
Frank Hannig and
J{\"{u}}rgen Teich},
editor = {Lars Svensson and
Jos{\'{e}} Monteiro},
title = {Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically
Reconfigurable Architectures},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization
and Simulation, 18th International Workshop, {PATMOS} 2008, Lisbon,
Portugal, September 10-12, 2008. Revised Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {5349},
pages = {307--317},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-95948-9\_31},
doi = {10.1007/978-3-540-95948-9\_31},
timestamp = {Mon, 05 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/KisslerSHT08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/KouretasP08,
author = {Ioannis Kouretas and
Vassilis Paliouras},
editor = {Lars Svensson and
Jos{\'{e}} Monteiro},
title = {Mixed Radix-2 and High-Radix {RNS} Bases for Low-Power Multiplication},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization
and Simulation, 18th International Workshop, {PATMOS} 2008, Lisbon,
Portugal, September 10-12, 2008. Revised Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {5349},
pages = {93--102},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-95948-9\_10},
doi = {10.1007/978-3-540-95948-9\_10},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/KouretasP08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/LanuzzaPCM08,
author = {Marco Lanuzza and
Stefania Perri and
Pasquale Corsonello and
Martin Margala},
editor = {Lars Svensson and
Jos{\'{e}} Monteiro},
title = {Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating
Digital Signal Processing},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization
and Simulation, 18th International Workshop, {PATMOS} 2008, Lisbon,
Portugal, September 10-12, 2008. Revised Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {5349},
pages = {297--306},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-95948-9\_30},
doi = {10.1007/978-3-540-95948-9\_30},
timestamp = {Wed, 25 Sep 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/LanuzzaPCM08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/LiKSSS08,
author = {Bing Li and
Christoph Knoth and
Walter Schneider and
Manuel Schmidt and
Ulf Schlichtmann},
editor = {Lars Svensson and
Jos{\'{e}} Monteiro},
title = {Static Timing Model Extraction for Combinational Circuits},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization
and Simulation, 18th International Workshop, {PATMOS} 2008, Lisbon,
Portugal, September 10-12, 2008. Revised Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {5349},
pages = {156--166},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-95948-9\_16},
doi = {10.1007/978-3-540-95948-9\_16},
timestamp = {Wed, 13 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/LiKSSS08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/LiSSTS08,
author = {Yan Li and
Helmut Schneider and
Florian Schnabel and
Roland Thewes and
Doris Schmitt{-}Landsiedel},
editor = {Lars Svensson and
Jos{\'{e}} Monteiro},
title = {Latched {CMOS} {DRAM} Sense Amplifier Yield Analysis and Optimization},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization
and Simulation, 18th International Workshop, {PATMOS} 2008, Lisbon,
Portugal, September 10-12, 2008. Revised Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {5349},
pages = {126--135},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-95948-9\_13},
doi = {10.1007/978-3-540-95948-9\_13},
timestamp = {Thu, 26 Jul 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/LiSSTS08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/Lima08,
author = {Floriberto A. Lima},
editor = {Lars Svensson and
Jos{\'{e}} Monteiro},
title = {Integration of Power Management Units onto the SoC},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization
and Simulation, 18th International Workshop, {PATMOS} 2008, Lisbon,
Portugal, September 10-12, 2008. Revised Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {5349},
pages = {458},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-95948-9\_46},
doi = {10.1007/978-3-540-95948-9\_46},
timestamp = {Tue, 26 Jun 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/Lima08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/MachadoRT08,
author = {Felipe Machado and
Teresa Riesgo and
Yago Torroja},
editor = {Lars Svensson and
Jos{\'{e}} Monteiro},
title = {Disjoint Region Partitioning for Probabilistic Switching Activity
Estimation at Register Transfer Level},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization
and Simulation, 18th International Workshop, {PATMOS} 2008, Lisbon,
Portugal, September 10-12, 2008. Revised Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {5349},
pages = {399--408},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-95948-9\_40},
doi = {10.1007/978-3-540-95948-9\_40},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/MachadoRT08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/MillanJBGRV08,
author = {Alejandro Mill{\'{a}}n and
Jorge Juan and
Manuel J. Bellido and
David Guerrero Martos and
Paulino Ruiz{-}de{-}Clavijo and
Julian Viejo},
editor = {Lars Svensson and
Jos{\'{e}} Monteiro},
title = {Power Dissipation Associated to Internal Effect Transitions in Static
{CMOS} Gates},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization
and Simulation, 18th International Workshop, {PATMOS} 2008, Lisbon,
Portugal, September 10-12, 2008. Revised Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {5349},
pages = {389--398},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-95948-9\_39},
doi = {10.1007/978-3-540-95948-9\_39},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/patmos/MillanJBGRV08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/MirmotahariB08,
author = {Omid Mirmotahari and
Yngvar Berg},
editor = {Lars Svensson and
Jos{\'{e}} Monteiro},
title = {Ultra Low Voltage High Speed Differential {CMOS} Inverter},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization
and Simulation, 18th International Workshop, {PATMOS} 2008, Lisbon,
Portugal, September 10-12, 2008. Revised Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {5349},
pages = {328--337},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-95948-9\_33},
doi = {10.1007/978-3-540-95948-9\_33},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/MirmotahariB08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/MishraA08,
author = {Biswajit Mishra and
Bashir M. Al{-}Hashimi},
editor = {Lars Svensson and
Jos{\'{e}} Monteiro},
title = {Subthreshold {FIR} Filter Architecture for Ultra Low Power Applications},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization
and Simulation, 18th International Workshop, {PATMOS} 2008, Lisbon,
Portugal, September 10-12, 2008. Revised Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {5349},
pages = {1--10},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-95948-9\_1},
doi = {10.1007/978-3-540-95948-9\_1},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/MishraA08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/MollFR08,
author = {Francesc Moll and
Joan Figueras and
Antonio Rubio},
editor = {Lars Svensson and
Jos{\'{e}} Monteiro},
title = {Data Dependence of Delay Distribution for a Planar Bus},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization
and Simulation, 18th International Workshop, {PATMOS} 2008, Lisbon,
Portugal, September 10-12, 2008. Revised Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {5349},
pages = {409--418},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-95948-9\_41},
doi = {10.1007/978-3-540-95948-9\_41},
timestamp = {Thu, 06 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/MollFR08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/MorgadoFMS08,
author = {Pedro Marques Morgado and
Paulo F. Flores and
Jos{\'{e}} C. Monteiro and
Lu{\'{\i}}s Miguel Silveira},
editor = {Lars Svensson and
Jos{\'{e}} Monteiro},
title = {Generating Worst-Case Stimuli for Accurate Power Grid Analysis},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization
and Simulation, 18th International Workshop, {PATMOS} 2008, Lisbon,
Portugal, September 10-12, 2008. Revised Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {5349},
pages = {247--257},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-95948-9\_25},
doi = {10.1007/978-3-540-95948-9\_25},
timestamp = {Wed, 08 Feb 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/patmos/MorgadoFMS08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/Moshnyaga08,
author = {Vasily G. Moshnyaga},
editor = {Lars Svensson and
Jos{\'{e}} Monteiro},
title = {Untraditional Approach to Computer Energy Reduction},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization
and Simulation, 18th International Workshop, {PATMOS} 2008, Lisbon,
Portugal, September 10-12, 2008. Revised Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {5349},
pages = {82--92},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-95948-9\_9},
doi = {10.1007/978-3-540-95948-9\_9},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/Moshnyaga08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/MuroyamaIY08,
author = {Masanori Muroyama and
Tohru Ishihara and
Hiroto Yasuura},
editor = {Lars Svensson and
Jos{\'{e}} Monteiro},
title = {Analysis of Effects of Input Arrival Time Variations on On-Chip Bus
Power Consumption},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization
and Simulation, 18th International Workshop, {PATMOS} 2008, Lisbon,
Portugal, September 10-12, 2008. Revised Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {5349},
pages = {62--71},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-95948-9\_7},
doi = {10.1007/978-3-540-95948-9\_7},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/MuroyamaIY08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/Nassif08,
author = {Sani R. Nassif},
editor = {Lars Svensson and
Jos{\'{e}} Monteiro},
title = {Model to Hardware Matching for nm Scale Technologies},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization
and Simulation, 18th International Workshop, {PATMOS} 2008, Lisbon,
Portugal, September 10-12, 2008. Revised Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {5349},
pages = {459},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-95948-9\_47},
doi = {10.1007/978-3-540-95948-9\_47},
timestamp = {Tue, 26 Jun 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/Nassif08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/NogueraEPHB08,
author = {Juanjo Noguera and
Robert Esser and
Katarina Paulsson and
Michael H{\"{u}}bner and
J{\"{u}}rgen Becker},
editor = {Lars Svensson and
Jos{\'{e}} Monteiro},
title = {Towards Novel Approaches in Design Automation for {FPGA} Power Optimization},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization
and Simulation, 18th International Workshop, {PATMOS} 2008, Lisbon,
Portugal, September 10-12, 2008. Revised Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {5349},
pages = {419--428},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-95948-9\_42},
doi = {10.1007/978-3-540-95948-9\_42},
timestamp = {Wed, 28 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/NogueraEPHB08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/OrdasLSMT08,
author = {Thomas Ordas and
Mathieu Lisart and
Etienne Sicard and
Philippe Maurine and
Lionel Torres},
editor = {Lars Svensson and
Jos{\'{e}} Monteiro},
title = {Near-Field Mapping System to Scan in Time Domain the Magnetic Emissions
of Integrated Circuits},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization
and Simulation, 18th International Workshop, {PATMOS} 2008, Lisbon,
Portugal, September 10-12, 2008. Revised Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {5349},
pages = {229--236},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-95948-9\_23},
doi = {10.1007/978-3-540-95948-9\_23},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/OrdasLSMT08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/OrtizIMG08,
author = {Alberto Garc{\'{\i}}a Ortiz and
Leandro Soares Indrusiak and
Tudor Murgan and
Manfred Glesner},
editor = {Lars Svensson and
Jos{\'{e}} Monteiro},
title = {{PMD:} {A} Low-Power Code for Networks-on-Chip Based on Virtual Channels},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization
and Simulation, 18th International Workshop, {PATMOS} 2008, Lisbon,
Portugal, September 10-12, 2008. Revised Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {5349},
pages = {219--228},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-95948-9\_22},
doi = {10.1007/978-3-540-95948-9\_22},
timestamp = {Fri, 02 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/patmos/OrtizIMG08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/OskuiiKLH08,
author = {Saeeid Tahmasbi Oskuii and
Per Gunnar Kjeldsberg and
Lars Lundheim and
Asghar Havashki},
editor = {Lars Svensson and
Jos{\'{e}} Monteiro},
title = {Power Optimization of Parallel Multipliers in Systems with Variable
Word-Length},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization
and Simulation, 18th International Workshop, {PATMOS} 2008, Lisbon,
Portugal, September 10-12, 2008. Revised Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {5349},
pages = {103--115},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-95948-9\_11},
doi = {10.1007/978-3-540-95948-9\_11},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/OskuiiKLH08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/PuglieseACC08,
author = {Andrea Pugliese and
Francesco A. Amoroso and
Gregorio Cappuccino and
Giuseppe Cocorullo},
editor = {Lars Svensson and
Jos{\'{e}} Monteiro},
title = {Settling-Optimization-Based Design Approach for Three-Stage Nested-Miller
Amplifiers},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization
and Simulation, 18th International Workshop, {PATMOS} 2008, Lisbon,
Portugal, September 10-12, 2008. Revised Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {5349},
pages = {318--327},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-95948-9\_32},
doi = {10.1007/978-3-540-95948-9\_32},
timestamp = {Mon, 05 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/PuglieseACC08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/SathanurBMMP08,
author = {Ashoka Visweswara Sathanur and
Luca Benini and
Alberto Macii and
Enrico Macii and
Massimo Poncino},
editor = {Lars Svensson and
Jos{\'{e}} Monteiro},
title = {Temporal Discharge Current Driven Clustering for Improved Leakage
Power Reduction in Row-Based Power-Gating},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization
and Simulation, 18th International Workshop, {PATMOS} 2008, Lisbon,
Portugal, September 10-12, 2008. Revised Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {5349},
pages = {42--51},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-95948-9\_5},
doi = {10.1007/978-3-540-95948-9\_5},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/SathanurBMMP08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/SchneiderSLS08,
author = {Walter Schneider and
Manuel Schmidt and
Bing Li and
Ulf Schlichtmann},
editor = {Lars Svensson and
Jos{\'{e}} Monteiro},
title = {A New Bounding Technique for Handling Arbitrary Correlations in Path-Based
{SSTA}},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization
and Simulation, 18th International Workshop, {PATMOS} 2008, Lisbon,
Portugal, September 10-12, 2008. Revised Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {5349},
pages = {167--177},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-95948-9\_17},
doi = {10.1007/978-3-540-95948-9\_17},
timestamp = {Wed, 13 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/SchneiderSLS08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/SimlastikS08,
author = {Martin Simlast{\'{\i}}k and
Viera Stopjakov{\'{a}}},
editor = {Lars Svensson and
Jos{\'{e}} Monteiro},
title = {Automated Synchronous-to-Asynchronous Circuits Conversion: {A} Survey},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization
and Simulation, 18th International Workshop, {PATMOS} 2008, Lisbon,
Portugal, September 10-12, 2008. Revised Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {5349},
pages = {348--358},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-95948-9\_35},
doi = {10.1007/978-3-540-95948-9\_35},
timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/SimlastikS08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/SioziosS08,
author = {Kostas Siozios and
Dimitrios Soudris},
editor = {Lars Svensson and
Jos{\'{e}} Monteiro},
title = {An Efficient Approach for Managing Power Consumption Hotspots Distribution
on 3D FPGAs},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization
and Simulation, 18th International Workshop, {PATMOS} 2008, Lisbon,
Portugal, September 10-12, 2008. Revised Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {5349},
pages = {439--448},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-95948-9\_44},
doi = {10.1007/978-3-540-95948-9\_44},
timestamp = {Mon, 05 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/SioziosS08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/TajalliABL08,
author = {Armin Tajalli and
Massimo Alioto and
Elizabeth J. Brauer and
Yusuf Leblebici},
editor = {Lars Svensson and
Jos{\'{e}} Monteiro},
title = {Improving the Power-Delay Performance in Subthreshold Source-Coupled
Logic Circuits},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization
and Simulation, 18th International Workshop, {PATMOS} 2008, Lisbon,
Portugal, September 10-12, 2008. Revised Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {5349},
pages = {21--30},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-95948-9\_3},
doi = {10.1007/978-3-540-95948-9\_3},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/TajalliABL08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/TodmanFTML08,
author = {Tim Todman and
Haohuan Fu and
Brittle Tsoi and
Oskar Mencer and
Wayne Luk},
editor = {Lars Svensson and
Jos{\'{e}} Monteiro},
title = {Smart Enumeration: {A} Systematic Approach to Exhaustive Search},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization
and Simulation, 18th International Workshop, {PATMOS} 2008, Lisbon,
Portugal, September 10-12, 2008. Revised Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {5349},
pages = {429--438},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-95948-9\_43},
doi = {10.1007/978-3-540-95948-9\_43},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/TodmanFTML08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/Vucurevic08,
author = {Ted Vucurevic},
editor = {Lars Svensson and
Jos{\'{e}} Monteiro},
title = {Power and Profit: Engineering in the Envelope},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization
and Simulation, 18th International Workshop, {PATMOS} 2008, Lisbon,
Portugal, September 10-12, 2008. Revised Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {5349},
pages = {460},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-95948-9\_48},
doi = {10.1007/978-3-540-95948-9\_48},
timestamp = {Tue, 26 Jun 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/Vucurevic08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/WienerKV08,
author = {Roni Wiener and
Gila Kamhi and
Moshe Y. Vardi},
editor = {Lars Svensson and
Jos{\'{e}} Monteiro},
title = {Intelligate: Scalable Dynamic Invariant Learning for Power Reduction},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization
and Simulation, 18th International Workshop, {PATMOS} 2008, Lisbon,
Portugal, September 10-12, 2008. Revised Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {5349},
pages = {52--61},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-95948-9\_6},
doi = {10.1007/978-3-540-95948-9\_6},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/WienerKV08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
a service of 
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
retrieved on 2024-04-25 08:11 CEST from data curated by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
