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@inproceedings{DBLP:conf/fpga/0001YCW24,
author = {Hui Wei and
Jingyong Ye and
Yutong Chen and
Heng Wu},
editor = {Zhiru Zhang and
Andrew Putnam},
title = {Design and Implementation of a Primary Visual Cortex Pathway Model
Based on Opponent-process Theory},
booktitle = {Proceedings of the 2024 {ACM/SIGDA} International Symposium on Field
Programmable Gate Arrays, {FPGA} 2024, Monterey, CA, USA, March 3-5,
2024},
pages = {40},
publisher = {{ACM}},
year = {2024},
url = {https://doi.org/10.1145/3626202.3637583},
doi = {10.1145/3626202.3637583},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/0001YCW24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/AbbaszadehH24,
author = {Mahdi Abbaszadeh and
Dana L. How},
editor = {Zhiru Zhang and
Andrew Putnam},
title = {From Topology to Realization in {FPGA/VPR} Routing},
booktitle = {Proceedings of the 2024 {ACM/SIGDA} International Symposium on Field
Programmable Gate Arrays, {FPGA} 2024, Monterey, CA, USA, March 3-5,
2024},
pages = {85--96},
publisher = {{ACM}},
year = {2024},
url = {https://doi.org/10.1145/3626202.3637572},
doi = {10.1145/3626202.3637572},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/AbbaszadehH24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/AhmedB24,
author = {Muhammed Kawser Ahmed and
Christophe Bobda},
editor = {Zhiru Zhang and
Andrew Putnam},
title = {{ISO-TENANT:} Rethinking {FPGA} Power Distribution Network {(PDN):}
{A} Hardware Based Solution for Remote Power Side Channel Attacks
in {FPGA}},
booktitle = {Proceedings of the 2024 {ACM/SIGDA} International Symposium on Field
Programmable Gate Arrays, {FPGA} 2024, Monterey, CA, USA, March 3-5,
2024},
pages = {42},
publisher = {{ACM}},
year = {2024},
url = {https://doi.org/10.1145/3626202.3637591},
doi = {10.1145/3626202.3637591},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/AhmedB24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/ChenT24,
author = {Yan Chen and
Kiyofumi Tanaka},
editor = {Zhiru Zhang and
Andrew Putnam},
title = {A Flexible, Fast, Low Bandwidth Block-based Acceleration Architecture
for {CNN} Inference on FPGAs},
booktitle = {Proceedings of the 2024 {ACM/SIGDA} International Symposium on Field
Programmable Gate Arrays, {FPGA} 2024, Monterey, CA, USA, March 3-5,
2024},
pages = {183},
publisher = {{ACM}},
year = {2024},
url = {https://doi.org/10.1145/3626202.3637582},
doi = {10.1145/3626202.3637582},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/ChenT24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/ChenZDXYZCZ24,
author = {Hongzheng Chen and
Jiahao Zhang and
Yixiao Du and
Shaojie Xiang and
Zichao Yue and
Niansong Zhang and
Yaohui Cai and
Zhiru Zhang},
editor = {Zhiru Zhang and
Andrew Putnam},
title = {A Comprehensive Evaluation of FPGA-Based Spatial Acceleration of LLMs},
booktitle = {Proceedings of the 2024 {ACM/SIGDA} International Symposium on Field
Programmable Gate Arrays, {FPGA} 2024, Monterey, CA, USA, March 3-5,
2024},
pages = {185},
publisher = {{ACM}},
year = {2024},
url = {https://doi.org/10.1145/3626202.3637600},
doi = {10.1145/3626202.3637600},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/ChenZDXYZCZ24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/ElakhrasGJI24,
author = {Ayatallah Elakhras and
Andrea Guerrieri and
Lana Josipovic and
Paolo Ienne},
editor = {Zhiru Zhang and
Andrew Putnam},
title = {Survival of the Fastest: Enabling More Out-of-Order Execution in Dataflow
Circuits},
booktitle = {Proceedings of the 2024 {ACM/SIGDA} International Symposium on Field
Programmable Gate Arrays, {FPGA} 2024, Monterey, CA, USA, March 3-5,
2024},
pages = {44--54},
publisher = {{ACM}},
year = {2024},
url = {https://doi.org/10.1145/3626202.3637556},
doi = {10.1145/3626202.3637556},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/ElakhrasGJI24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/GaoZDS24,
author = {Yizhao Gao and
Baoheng Zhang and
Yuhao Ding and
Hayden Kwok{-}Hay So},
editor = {Zhiru Zhang and
Andrew Putnam},
title = {A Composable Dynamic Sparse Dataflow Architecture for Efficient Event-based
Vision Processing on {FPGA}},
booktitle = {Proceedings of the 2024 {ACM/SIGDA} International Symposium on Field
Programmable Gate Arrays, {FPGA} 2024, Monterey, CA, USA, March 3-5,
2024},
pages = {246--257},
publisher = {{ACM}},
year = {2024},
url = {https://doi.org/10.1145/3626202.3637558},
doi = {10.1145/3626202.3637558},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/GaoZDS24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/GerlachKBEHP24,
author = {Thore Gerlach and
Stefan Knipp and
David Biesner and
Stelios Emmanouilidis and
Klaus Hauber and
Nico Piatkowski},
editor = {Zhiru Zhang and
Andrew Putnam},
title = {FPGA-Placement via Quantum Annealing},
booktitle = {Proceedings of the 2024 {ACM/SIGDA} International Symposium on Field
Programmable Gate Arrays, {FPGA} 2024, Monterey, CA, USA, March 3-5,
2024},
pages = {43},
publisher = {{ACM}},
year = {2024},
url = {https://doi.org/10.1145/3626202.3637619},
doi = {10.1145/3626202.3637619},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/GerlachKBEHP24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/GerlinghoffCGW024,
author = {Daniel Gerlinghoff and
Benjamin Chen Ming Choong and
Rick Siow Mong Goh and
Weng{-}Fai Wong and
Tao Luo},
editor = {Zhiru Zhang and
Andrew Putnam},
title = {Table-Lookup {MAC:} Scalable Processing of Quantised Neural Networks
in {FPGA} Soft Logic},
booktitle = {Proceedings of the 2024 {ACM/SIGDA} International Symposium on Field
Programmable Gate Arrays, {FPGA} 2024, Monterey, CA, USA, March 3-5,
2024},
pages = {235--245},
publisher = {{ACM}},
year = {2024},
url = {https://doi.org/10.1145/3626202.3637576},
doi = {10.1145/3626202.3637576},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/GerlinghoffCGW024.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/GuerrieriGJI24,
author = {Andrea Guerrieri and
Srijeet Guha and
Lana Josipovic and
Paolo Ienne},
editor = {Zhiru Zhang and
Andrew Putnam},
title = {DynaRapid: From {C} to {FPGA} in a Few Seconds},
booktitle = {Proceedings of the 2024 {ACM/SIGDA} International Symposium on Field
Programmable Gate Arrays, {FPGA} 2024, Monterey, CA, USA, March 3-5,
2024},
pages = {40},
publisher = {{ACM}},
year = {2024},
url = {https://doi.org/10.1145/3626202.3637580},
doi = {10.1145/3626202.3637580},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/GuerrieriGJI24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/Gupta24,
author = {Prabhat K. Gupta},
editor = {Zhiru Zhang and
Andrew Putnam},
title = {My Fifteen Year Journey of Deploying {FPGA} Accelerated Solutions},
booktitle = {Proceedings of the 2024 {ACM/SIGDA} International Symposium on Field
Programmable Gate Arrays, {FPGA} 2024, Monterey, CA, USA, March 3-5,
2024},
pages = {142},
publisher = {{ACM}},
year = {2024},
url = {https://doi.org/10.1145/3626202.3644813},
doi = {10.1145/3626202.3644813},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/Gupta24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/HaoRZSJ024,
author = {Xiaochen Hao and
Hongbo Rong and
Mingzhe Zhang and
Ce Sun and
Hong H. Jiang and
Yun Liang},
editor = {Zhiru Zhang and
Andrew Putnam},
title = {{POPA:} Expressing High and Portable Performance across Spatial and
Vector Architectures for Tensor Computations},
booktitle = {Proceedings of the 2024 {ACM/SIGDA} International Symposium on Field
Programmable Gate Arrays, {FPGA} 2024, Monterey, CA, USA, March 3-5,
2024},
pages = {199--210},
publisher = {{ACM}},
year = {2024},
url = {https://doi.org/10.1145/3626202.3637566},
doi = {10.1145/3626202.3637566},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/HaoRZSJ024.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/HeSLC24,
author = {Zifan He and
Linghao Song and
Robert F. Lucas and
Jason Cong},
editor = {Zhiru Zhang and
Andrew Putnam},
title = {LevelST: Stream-based Accelerator for Sparse Triangular Solver},
booktitle = {Proceedings of the 2024 {ACM/SIGDA} International Symposium on Field
Programmable Gate Arrays, {FPGA} 2024, Monterey, CA, USA, March 3-5,
2024},
pages = {67--77},
publisher = {{ACM}},
year = {2024},
url = {https://doi.org/10.1145/3626202.3637568},
doi = {10.1145/3626202.3637568},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/HeSLC24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/JiangVDL24,
author = {Yiyue Jiang and
Andrius Vaicaitis and
John Dooley and
Miriam Leeser},
editor = {Zhiru Zhang and
Andrew Putnam},
title = {Efficient Neural Networks on the Edge with FPGAs by Optimizing an
Adaptive Activation Function},
booktitle = {Proceedings of the 2024 {ACM/SIGDA} International Symposium on Field
Programmable Gate Arrays, {FPGA} 2024, Monterey, CA, USA, March 3-5,
2024},
pages = {184},
publisher = {{ACM}},
year = {2024},
url = {https://doi.org/10.1145/3626202.3637594},
doi = {10.1145/3626202.3637594},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/JiangVDL24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/KashaniEKPRL24,
author = {Sahand Kashani and
Mahyar Emami and
Keisuke Kamahori and
Mohammad Sepehr Pourghannad and
Ritik Raj and
James R. Larus},
editor = {Zhiru Zhang and
Andrew Putnam},
title = {A 475 MHz Manycore {FPGA} Accelerator for {RTL} Simulation},
booktitle = {Proceedings of the 2024 {ACM/SIGDA} International Symposium on Field
Programmable Gate Arrays, {FPGA} 2024, Monterey, CA, USA, March 3-5,
2024},
pages = {78--84},
publisher = {{ACM}},
year = {2024},
url = {https://doi.org/10.1145/3626202.3637579},
doi = {10.1145/3626202.3637579},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/KashaniEKPRL24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/KhataeiB24,
author = {Alireza Khataei and
Kia Bazargan},
editor = {Zhiru Zhang and
Andrew Putnam},
title = {CompressedLUT: An Open Source Tool for Lossless Compression of Lookup
Tables for Function Evaluation and Beyond},
booktitle = {Proceedings of the 2024 {ACM/SIGDA} International Symposium on Field
Programmable Gate Arrays, {FPGA} 2024, Monterey, CA, USA, March 3-5,
2024},
pages = {2--11},
publisher = {{ACM}},
year = {2024},
url = {https://doi.org/10.1145/3626202.3637575},
doi = {10.1145/3626202.3637575},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/KhataeiB24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/Klaisoongnoen0D24,
author = {Mark Klaisoongnoen and
Nick Brown and
Tim Dykes and
Jessica R. Jones and
Utz{-}Uwe Haus},
editor = {Zhiru Zhang and
Andrew Putnam},
title = {Evaluating Versal {AI} Engines for Option Price Discovery in Market
Risk Analysis},
booktitle = {Proceedings of the 2024 {ACM/SIGDA} International Symposium on Field
Programmable Gate Arrays, {FPGA} 2024, Monterey, CA, USA, March 3-5,
2024},
pages = {176--182},
publisher = {{ACM}},
year = {2024},
url = {https://doi.org/10.1145/3626202.3637578},
doi = {10.1145/3626202.3637578},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/Klaisoongnoen0D24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/LanghammerC24,
author = {Martin Langhammer and
George A. Constantinides},
editor = {Zhiru Zhang and
Andrew Putnam},
title = {A Statically and Dynamically Scalable Soft {GPGPU}},
booktitle = {Proceedings of the 2024 {ACM/SIGDA} International Symposium on Field
Programmable Gate Arrays, {FPGA} 2024, Monterey, CA, USA, March 3-5,
2024},
pages = {165--175},
publisher = {{ACM}},
year = {2024},
url = {https://doi.org/10.1145/3626202.3637567},
doi = {10.1145/3626202.3637567},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/LanghammerC24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/LinSKK024,
author = {Will Lin and
Yizhou Shan and
Ryan Kosta and
Arvind Krishnamurthy and
Yiying Zhang},
editor = {Zhiru Zhang and
Andrew Putnam},
title = {SuperNIC: An FPGA-Based, Cloud-Oriented SmartNIC},
booktitle = {Proceedings of the 2024 {ACM/SIGDA} International Symposium on Field
Programmable Gate Arrays, {FPGA} 2024, Monterey, CA, USA, March 3-5,
2024},
pages = {130--141},
publisher = {{ACM}},
year = {2024},
url = {https://doi.org/10.1145/3626202.3637564},
doi = {10.1145/3626202.3637564},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/LinSKK024.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/NassarMGBTH24,
author = {Hassan Nassar and
Philipp Machauer and
Dennis R. E. Gnad and
Lars Bauer and
Mehdi B. Tahoori and
J{\"{o}}rg Henkel},
editor = {Zhiru Zhang and
Andrew Putnam},
title = {Covert-Hammer: Coordinating Power-Hammering on Multi-tenant FPGAs
via Covert Channels},
booktitle = {Proceedings of the 2024 {ACM/SIGDA} International Symposium on Field
Programmable Gate Arrays, {FPGA} 2024, Monterey, CA, USA, March 3-5,
2024},
pages = {43},
publisher = {{ACM}},
year = {2024},
url = {https://doi.org/10.1145/3626202.3637613},
doi = {10.1145/3626202.3637613},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/NassarMGBTH24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/NiuZZTYLH24,
author = {Xiaoyu Niu and
Yanjun Zhang and
Yifan Zhang and
Hongzheng Tian and
Bo Yu and
Shaoshan Liu and
Sitao Huang},
editor = {Zhiru Zhang and
Andrew Putnam},
title = {Accelerating Autonomous Path Planning on FPGAs with Sparsity-Aware
{HW/SW} Co-Optimizations},
booktitle = {Proceedings of the 2024 {ACM/SIGDA} International Symposium on Field
Programmable Gate Arrays, {FPGA} 2024, Monterey, CA, USA, March 3-5,
2024},
pages = {42},
publisher = {{ACM}},
year = {2024},
url = {https://doi.org/10.1145/3626202.3637597},
doi = {10.1145/3626202.3637597},
timestamp = {Tue, 16 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/NiuZZTYLH24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/ParkD24,
author = {Dongjoon Park and
Andr{\'{e}} DeHon},
editor = {Zhiru Zhang and
Andrew Putnam},
title = {{REFINE:} Runtime Execution Feedback for INcremental Evolution on
{FPGA} Designs},
booktitle = {Proceedings of the 2024 {ACM/SIGDA} International Symposium on Field
Programmable Gate Arrays, {FPGA} 2024, Monterey, CA, USA, March 3-5,
2024},
pages = {108--118},
publisher = {{ACM}},
year = {2024},
url = {https://doi.org/10.1145/3626202.3637560},
doi = {10.1145/3626202.3637560},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/ParkD24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/PouchetTZCP0Z24,
author = {Louis{-}No{\"{e}}l Pouchet and
Emily Tucker and
Niansong Zhang and
Hongzheng Chen and
Debjit Pal and
Gabriel Rodr{\'{\i}}guez and
Zhiru Zhang},
editor = {Zhiru Zhang and
Andrew Putnam},
title = {Formal Verification of Source-to-Source Transformations for {HLS}},
booktitle = {Proceedings of the 2024 {ACM/SIGDA} International Symposium on Field
Programmable Gate Arrays, {FPGA} 2024, Monterey, CA, USA, March 3-5,
2024},
pages = {97--107},
publisher = {{ACM}},
year = {2024},
url = {https://doi.org/10.1145/3626202.3637563},
doi = {10.1145/3626202.3637563},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/PouchetTZCP0Z24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/PougetPC24,
author = {St{\'{e}}phane Pouget and
Louis{-}No{\"{e}}l Pouchet and
Jason Cong},
editor = {Zhiru Zhang and
Andrew Putnam},
title = {Automatic Hardware Pragma Insertion in High-Level Synthesis: {A} Non-Linear
Programming Approach},
booktitle = {Proceedings of the 2024 {ACM/SIGDA} International Symposium on Field
Programmable Gate Arrays, {FPGA} 2024, Monterey, CA, USA, March 3-5,
2024},
pages = {184},
publisher = {{ACM}},
year = {2024},
url = {https://doi.org/10.1145/3626202.3637593},
doi = {10.1145/3626202.3637593},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/PougetPC24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/QianLL0ZC024,
author = {Kai Qian and
Zheng Liu and
Yinqiu Liu and
Haodong Lu and
Zexu Zhang and
Ruiqiu Chen and
Kun Wang},
editor = {Zhiru Zhang and
Andrew Putnam},
title = {AutoHammer: Breaking the Compilation Wall Between Deep Neural Network
and Overlay-based {FPGA} Accelerator},
booktitle = {Proceedings of the 2024 {ACM/SIGDA} International Symposium on Field
Programmable Gate Arrays, {FPGA} 2024, Monterey, CA, USA, March 3-5,
2024},
pages = {185},
publisher = {{ACM}},
year = {2024},
url = {https://doi.org/10.1145/3626202.3637595},
doi = {10.1145/3626202.3637595},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/QianLL0ZC024.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/RajashekarTF24,
author = {Manoj B. Rajashekar and
Xingyu Tian and
Zhenman Fang},
editor = {Zhiru Zhang and
Andrew Putnam},
title = {HiSpMV: Hybrid Row Distribution and Vector Buffering for Imbalanced
SpMV Acceleration on FPGAs},
booktitle = {Proceedings of the 2024 {ACM/SIGDA} International Symposium on Field
Programmable Gate Arrays, {FPGA} 2024, Monterey, CA, USA, March 3-5,
2024},
pages = {154--164},
publisher = {{ACM}},
year = {2024},
url = {https://doi.org/10.1145/3626202.3637557},
doi = {10.1145/3626202.3637557},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/RajashekarTF24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/RayDQY24,
author = {Andy Ray and
Benjamin Devlin and
Fu Yong Quah and
Rahul Yesantharao},
editor = {Zhiru Zhang and
Andrew Putnam},
title = {Hardcaml {MSM:} {A} High-Performance Split {CPU-FPGA} Multi-Scalar
Multiplication Engine},
booktitle = {Proceedings of the 2024 {ACM/SIGDA} International Symposium on Field
Programmable Gate Arrays, {FPGA} 2024, Monterey, CA, USA, March 3-5,
2024},
pages = {33--39},
publisher = {{ACM}},
year = {2024},
url = {https://doi.org/10.1145/3626202.3637577},
doi = {10.1145/3626202.3637577},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/RayDQY24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/RayDQY24a,
author = {Andy Ray and
Benjamin Devlin and
Fu Yong Quah and
Rahul Yesantharao},
editor = {Zhiru Zhang and
Andrew Putnam},
title = {Hardcaml: An OCaml Hardware Domain-Specific Language for Efficient
and Robust Design},
booktitle = {Proceedings of the 2024 {ACM/SIGDA} International Symposium on Field
Programmable Gate Arrays, {FPGA} 2024, Monterey, CA, USA, March 3-5,
2024},
pages = {41},
publisher = {{ACM}},
year = {2024},
url = {https://doi.org/10.1145/3626202.3637586},
doi = {10.1145/3626202.3637586},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/RayDQY24a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/Sherwood24,
author = {Timothy Sherwood},
editor = {Zhiru Zhang and
Andrew Putnam},
title = {Security, Synapses, Sustainability, and Superconducting: {A} Look
at Possible Futures for the {FPGA}},
booktitle = {Proceedings of the 2024 {ACM/SIGDA} International Symposium on Field
Programmable Gate Arrays, {FPGA} 2024, Monterey, CA, USA, March 3-5,
2024},
pages = {1},
publisher = {{ACM}},
year = {2024},
url = {https://doi.org/10.1145/3626202.3644812},
doi = {10.1145/3626202.3644812},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/Sherwood24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/StittPC24,
author = {Greg Stitt and
Wesley Piard and
Christopher Crary},
editor = {Zhiru Zhang and
Andrew Putnam},
title = {Low-Latency, Line-Rate Variable-Length Field Parsing for 100+ Gb/s
Ethernet},
booktitle = {Proceedings of the 2024 {ACM/SIGDA} International Symposium on Field
Programmable Gate Arrays, {FPGA} 2024, Monterey, CA, USA, March 3-5,
2024},
pages = {12--21},
publisher = {{ACM}},
year = {2024},
url = {https://doi.org/10.1145/3626202.3637559},
doi = {10.1145/3626202.3637559},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/StittPC24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/SuDLLWS024,
author = {Chunyou Su and
Linfeng Du and
Tingyuan Liang and
Zhe Lin and
Maolin Wang and
Sharad Sinha and
Wei Zhang},
editor = {Zhiru Zhang and
Andrew Putnam},
title = {GraFlex: Flexible Graph Processing on FPGAs through Customized Scalable
Interconnection Network},
booktitle = {Proceedings of the 2024 {ACM/SIGDA} International Symposium on Field
Programmable Gate Arrays, {FPGA} 2024, Monterey, CA, USA, March 3-5,
2024},
pages = {143--153},
publisher = {{ACM}},
year = {2024},
url = {https://doi.org/10.1145/3626202.3637573},
doi = {10.1145/3626202.3637573},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/SuDLLWS024.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/WangZLC0024,
author = {Zelin Wang and
Guiyuan Zhu and
Yunhai Liu and
Yisong Chang and
Ke Zhang and
Mingyu Chen},
editor = {Zhiru Zhang and
Andrew Putnam},
title = {{XUNI:} Virtual Machine Abstraction for Self-contained and Multi-tenant
Cloud FPGAs},
booktitle = {Proceedings of the 2024 {ACM/SIGDA} International Symposium on Field
Programmable Gate Arrays, {FPGA} 2024, Monterey, CA, USA, March 3-5,
2024},
pages = {41},
publisher = {{ACM}},
year = {2024},
url = {https://doi.org/10.1145/3626202.3637587},
doi = {10.1145/3626202.3637587},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/WangZLC0024.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/WeiASJ24,
author = {Zhigang Wei and
Aman Arora and
Emily Shriver and
Lizy Kurian John},
editor = {Zhiru Zhang and
Andrew Putnam},
title = {Cross-FPGA Power Estimation from High Level Synthesis via Transfer-Learning},
booktitle = {Proceedings of the 2024 {ACM/SIGDA} International Symposium on Field
Programmable Gate Arrays, {FPGA} 2024, Monterey, CA, USA, March 3-5,
2024},
pages = {187},
publisher = {{ACM}},
year = {2024},
url = {https://doi.org/10.1145/3626202.3637621},
doi = {10.1145/3626202.3637621},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/WeiASJ24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/WuZGLW024,
author = {Qizhe Wu and
Letian Zhao and
Yuchen Gui and
Huawen Liang and
Xiaotian Wang and
Xi Jin},
editor = {Zhiru Zhang and
Andrew Putnam},
title = {Efficient Message Passing Architecture for {GCN} Training on HBM-based
FPGAs with Orthogonal Topology On-Chip Networks},
booktitle = {Proceedings of the 2024 {ACM/SIGDA} International Symposium on Field
Programmable Gate Arrays, {FPGA} 2024, Monterey, CA, USA, March 3-5,
2024},
pages = {187},
publisher = {{ACM}},
year = {2024},
url = {https://doi.org/10.1145/3626202.3637608},
doi = {10.1145/3626202.3637608},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/WuZGLW024.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/XiaoLZ024,
author = {Youwei Xiao and
Zizhang Luo and
Kexing Zhou and
Yun Liang},
editor = {Zhiru Zhang and
Andrew Putnam},
title = {Cement: Streamlining {FPGA} Hardware Design with Cycle-Deterministic
eHDL and Synthesis},
booktitle = {Proceedings of the 2024 {ACM/SIGDA} International Symposium on Field
Programmable Gate Arrays, {FPGA} 2024, Monterey, CA, USA, March 3-5,
2024},
pages = {211--222},
publisher = {{ACM}},
year = {2024},
url = {https://doi.org/10.1145/3626202.3637561},
doi = {10.1145/3626202.3637561},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/XiaoLZ024.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/XuJ24,
author = {Jiahui Xu and
Lana Josipovic},
editor = {Zhiru Zhang and
Andrew Putnam},
title = {Suppressing Spurious Dynamism of Dataflow Circuits via Latency and
Occupancy Balancing},
booktitle = {Proceedings of the 2024 {ACM/SIGDA} International Symposium on Field
Programmable Gate Arrays, {FPGA} 2024, Monterey, CA, USA, March 3-5,
2024},
pages = {188--198},
publisher = {{ACM}},
year = {2024},
url = {https://doi.org/10.1145/3626202.3637570},
doi = {10.1145/3626202.3637570},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/XuJ24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/XuL024,
author = {Ruifan Xu and
Jin Luo and
Yun Liang},
editor = {Zhiru Zhang and
Andrew Putnam},
title = {Hermes: Enhancing Extensibility in High-Level Synthesis through Multi-Level
IRs},
booktitle = {Proceedings of the 2024 {ACM/SIGDA} International Symposium on Field
Programmable Gate Arrays, {FPGA} 2024, Monterey, CA, USA, March 3-5,
2024},
pages = {186},
publisher = {{ACM}},
year = {2024},
url = {https://doi.org/10.1145/3626202.3637606},
doi = {10.1145/3626202.3637606},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/XuL024.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/XuLSL024,
author = {Shaoxian Xu and
Sitong Lu and
Zhiyuan Shao and
Xiaofei Liao and
Hai Jin},
editor = {Zhiru Zhang and
Andrew Putnam},
title = {MiCache: An MSHR-inclusive Non-blocking Cache Design for FPGAs},
booktitle = {Proceedings of the 2024 {ACM/SIGDA} International Symposium on Field
Programmable Gate Arrays, {FPGA} 2024, Monterey, CA, USA, March 3-5,
2024},
pages = {22--32},
publisher = {{ACM}},
year = {2024},
url = {https://doi.org/10.1145/3626202.3637571},
doi = {10.1145/3626202.3637571},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/XuLSL024.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/XuPHL024,
author = {Shengjun Xu and
Wenlu Peng and
Wenjin Huang and
Qi Liu and
Yihua Huang},
editor = {Zhiru Zhang and
Andrew Putnam},
title = {{HR-GCN:} An Efficient {GCN} Accelerator for Heterogeneous Graph Data
and {R-GCN} Model},
booktitle = {Proceedings of the 2024 {ACM/SIGDA} International Symposium on Field
Programmable Gate Arrays, {FPGA} 2024, Monterey, CA, USA, March 3-5,
2024},
pages = {186},
publisher = {{ACM}},
year = {2024},
url = {https://doi.org/10.1145/3626202.3637602},
doi = {10.1145/3626202.3637602},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/XuPHL024.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/XuYCGRYW24,
author = {Zhenyu Xu and
Miaoxiang Yu and
Jillian Cai and
Saddam Gafsi and
Judson Douglas Ryckman and
Qing Yang and
Tao Wei},
editor = {Zhiru Zhang and
Andrew Putnam},
title = {An FPGA-Enabled Framework for Rapid Automated Design of Photonic Integrated
Circuits},
booktitle = {Proceedings of the 2024 {ACM/SIGDA} International Symposium on Field
Programmable Gate Arrays, {FPGA} 2024, Monterey, CA, USA, March 3-5,
2024},
pages = {119--129},
publisher = {{ACM}},
year = {2024},
url = {https://doi.org/10.1145/3626202.3637565},
doi = {10.1145/3626202.3637565},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/XuYCGRYW24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/Yang0FZZXL24,
author = {Geng Yang and
Jie Lei and
Zhenman Fang and
Jiaqing Zhang and
Junrong Zhang and
Weiying Xie and
Yunsong Li},
editor = {Zhiru Zhang and
Andrew Putnam},
title = {{E4SA:} An Ultra-Efficient Systolic Array Architecture for 4-Bit Convolutional
Neural Networks},
booktitle = {Proceedings of the 2024 {ACM/SIGDA} International Symposium on Field
Programmable Gate Arrays, {FPGA} 2024, Monterey, CA, USA, March 3-5,
2024},
pages = {183},
publisher = {{ACM}},
year = {2024},
url = {https://doi.org/10.1145/3626202.3637585},
doi = {10.1145/3626202.3637585},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/Yang0FZZXL24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/ZengLDY0WMSLHDL24,
author = {Shulin Zeng and
Jun Liu and
Guohao Dai and
Xinhao Yang and
Tianyu Fu and
Hongyi Wang and
Wenheng Ma and
Hanbo Sun and
Shiyao Li and
Zixiao Huang and
Yadong Dai and
Jintao Li and
Zehao Wang and
Ruoyu Zhang and
Kairui Wen and
Xuefei Ning and
Yu Wang},
editor = {Zhiru Zhang and
Andrew Putnam},
title = {FlightLLM: Efficient Large Language Model Inference with a Complete
Mapping Flow on FPGAs},
booktitle = {Proceedings of the 2024 {ACM/SIGDA} International Symposium on Field
Programmable Gate Arrays, {FPGA} 2024, Monterey, CA, USA, March 3-5,
2024},
pages = {223--234},
publisher = {{ACM}},
year = {2024},
url = {https://doi.org/10.1145/3626202.3637562},
doi = {10.1145/3626202.3637562},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/ZengLDY0WMSLHDL24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/ZhuangYJHJH0024,
author = {Jinming Zhuang and
Zhuoping Yang and
Shixin Ji and
Heng Huang and
Alex K. Jones and
Jingtong Hu and
Yiyu Shi and
Peipei Zhou},
editor = {Zhiru Zhang and
Andrew Putnam},
title = {{SSR:} Spatial Sequential Hybrid Architecture for Latency Throughput
Tradeoff in Transformer Acceleration},
booktitle = {Proceedings of the 2024 {ACM/SIGDA} International Symposium on Field
Programmable Gate Arrays, {FPGA} 2024, Monterey, CA, USA, March 3-5,
2024},
pages = {55--66},
publisher = {{ACM}},
year = {2024},
url = {https://doi.org/10.1145/3626202.3637569},
doi = {10.1145/3626202.3637569},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/ZhuangYJHJH0024.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/fpga/2024,
editor = {Zhiru Zhang and
Andrew Putnam},
title = {Proceedings of the 2024 {ACM/SIGDA} International Symposium on Field
Programmable Gate Arrays, {FPGA} 2024, Monterey, CA, USA, March 3-5,
2024},
publisher = {{ACM}},
year = {2024},
url = {https://doi.org/10.1145/3626202},
doi = {10.1145/3626202},
timestamp = {Thu, 04 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/2024.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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