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@inproceedings{DBLP:conf/fpga/AhmedKATA08,
author = {Taneem Ahmed and
Paul D. Kundarewich and
Jason Helge Anderson and
Brad L. Taylor and
Rajat Aggarwal},
editor = {Mike Hutton and
Paul Chow},
title = {Architecture-specific packing for virtex-5 FPGAs},
booktitle = {Proceedings of the {ACM/SIGDA} 16th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2008, Monterey, California, USA,
February 24-26, 2008},
pages = {5--13},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1344671.1344675},
doi = {10.1145/1344671.1344675},
timestamp = {Tue, 06 Nov 2018 16:58:23 +0100},
biburl = {https://dblp.org/rec/conf/fpga/AhmedKATA08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/AnsariA08,
author = {Amin Ansari and
Keyvan Amiri},
editor = {Mike Hutton and
Paul Chow},
title = {Flexible FPGA-based parallel architecture for identification of repetitive
sequences in interleaved pulse trains},
booktitle = {Proceedings of the {ACM/SIGDA} 16th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2008, Monterey, California, USA,
February 24-26, 2008},
pages = {265},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1344671.1344730},
doi = {10.1145/1344671.1344730},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/AnsariA08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/AsadiMW08,
author = {Narges Bani Asadi and
Teresa H. Meng and
Wing Hung Wong},
editor = {Mike Hutton and
Paul Chow},
title = {Reconfigurable computing for learning Bayesian networks},
booktitle = {Proceedings of the {ACM/SIGDA} 16th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2008, Monterey, California, USA,
February 24-26, 2008},
pages = {203--211},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1344671.1344702},
doi = {10.1145/1344671.1344702},
timestamp = {Sun, 08 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/AsadiMW08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/CameraB08,
author = {Kevin Camera and
Robert W. Brodersen},
editor = {Mike Hutton and
Paul Chow},
title = {An integrated debugging environment for {FPGA} computing platforms},
booktitle = {Proceedings of the {ACM/SIGDA} 16th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2008, Monterey, California, USA,
February 24-26, 2008},
pages = {260},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1344671.1344719},
doi = {10.1145/1344671.1344719},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/CameraB08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/CevreroAPVBGLI08,
author = {Alessandro Cevrero and
Panagiotis Athanasopoulos and
Hadi Parandeh{-}Afshar and
Ajay Kumar Verma and
Philip Brisk and
Frank K. G{\"{u}}rkaynak and
Yusuf Leblebici and
Paolo Ienne},
editor = {Mike Hutton and
Paul Chow},
title = {Architectural improvements for field programmable counter arrays:
enabling efficient synthesis of fast compressor trees on FPGAs},
booktitle = {Proceedings of the {ACM/SIGDA} 16th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2008, Monterey, California, USA,
February 24-26, 2008},
pages = {181--190},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1344671.1344699},
doi = {10.1145/1344671.1344699},
timestamp = {Tue, 03 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/CevreroAPVBGLI08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/ChaudhuriDHG08,
author = {Sumanta Chaudhuri and
Jean{-}Luc Danger and
Philippe Hoogvorst and
Sylvain Guilley},
editor = {Mike Hutton and
Paul Chow},
title = {Efficient tiling patterns for reconfigurable gate arrays},
booktitle = {Proceedings of the {ACM/SIGDA} 16th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2008, Monterey, California, USA,
February 24-26, 2008},
pages = {257},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1344671.1344709},
doi = {10.1145/1344671.1344709},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/ChaudhuriDHG08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/ChengLH08,
author = {Lerong Cheng and
Yan Lin and
Lei He},
editor = {Mike Hutton and
Paul Chow},
title = {Trace-based framework for concurrent development of process and {FPGA}
architecture considering process variation and reliability},
booktitle = {Proceedings of the {ACM/SIGDA} 16th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2008, Monterey, California, USA,
February 24-26, 2008},
pages = {159--168},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1344671.1344696},
doi = {10.1145/1344671.1344696},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/ChengLH08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/ChungNHFM08,
author = {Eric S. Chung and
Eriko Nurvitadhi and
James C. Hoe and
Babak Falsafi and
Ken Mai},
editor = {Mike Hutton and
Paul Chow},
title = {A complexity-effective architecture for accelerating full-system multiprocessor
simulations using FPGAs},
booktitle = {Proceedings of the {ACM/SIGDA} 16th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2008, Monterey, California, USA,
February 24-26, 2008},
pages = {77--86},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1344671.1344684},
doi = {10.1145/1344671.1344684},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/ChungNHFM08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/CongJ08,
author = {Jason Cong and
Wei Jiang},
editor = {Mike Hutton and
Paul Chow},
title = {Pattern-based behavior synthesis for {FPGA} resource reduction},
booktitle = {Proceedings of the {ACM/SIGDA} 16th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2008, Monterey, California, USA,
February 24-26, 2008},
pages = {107--116},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1344671.1344688},
doi = {10.1145/1344671.1344688},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/CongJ08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/CongZ08,
author = {Jason Cong and
Yi Zou},
editor = {Mike Hutton and
Paul Chow},
title = {Lithographic aerial image simulation with FPGA-based hardwareacceleration},
booktitle = {Proceedings of the {ACM/SIGDA} 16th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2008, Monterey, California, USA,
February 24-26, 2008},
pages = {67--76},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1344671.1344683},
doi = {10.1145/1344671.1344683},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/CongZ08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/Contreras-MedinaRRM08,
author = {Luis Miguel Contreras{-}Medina and
Ren{\'{e}} de Jes{\'{u}}s Romero{-}Troncoso and
Jose de Jesus Rangel{-}Magdaleno and
Jesus Roberto Millan{-}Almaraz},
editor = {Mike Hutton and
Paul Chow},
title = {{FPGA} based multiple-channel vibration analyzer for industrial applications
with reconfigurable post-processing capabilities for automatic failure
detection on machinery},
booktitle = {Proceedings of the {ACM/SIGDA} 16th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2008, Monterey, California, USA,
February 24-26, 2008},
pages = {263},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1344671.1344724},
doi = {10.1145/1344671.1344724},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/Contreras-MedinaRRM08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/DalalS08,
author = {Ishaan L. Dalal and
Deian Stefan},
editor = {Mike Hutton and
Paul Chow},
title = {A hardware framework for the fast generation of multiple long-period
random number streams},
booktitle = {Proceedings of the {ACM/SIGDA} 16th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2008, Monterey, California, USA,
February 24-26, 2008},
pages = {245--254},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1344671.1344707},
doi = {10.1145/1344671.1344707},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/DalalS08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/DinechinDCT08,
author = {Florent de Dinechin and
J{\'{e}}r{\'{e}}mie Detrey and
Octavian Cret and
Radu Tudoran},
editor = {Mike Hutton and
Paul Chow},
title = {When FPGAs are better at floating-point than microprocessors},
booktitle = {Proceedings of the {ACM/SIGDA} 16th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2008, Monterey, California, USA,
February 24-26, 2008},
pages = {260},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1344671.1344717},
doi = {10.1145/1344671.1344717},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/DinechinDCT08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/DinhCW08,
author = {Quang Dinh and
Deming Chen and
Martin D. F. Wong},
editor = {Mike Hutton and
Paul Chow},
title = {Efficient {ASIP} design for configurable processors with fine-grained
resource sharing},
booktitle = {Proceedings of the {ACM/SIGDA} 16th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2008, Monterey, California, USA,
February 24-26, 2008},
pages = {99--106},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1344671.1344687},
doi = {10.1145/1344671.1344687},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/DinhCW08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/El-GhazawiL08,
author = {Tarek A. El{-}Ghazawi and
Guy G. Lemieux},
editor = {Mike Hutton and
Paul Chow},
title = {Extreme parallel architectures for the masses},
booktitle = {Proceedings of the {ACM/SIGDA} 16th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2008, Monterey, California, USA,
February 24-26, 2008},
pages = {127--128},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1344671.1344691},
doi = {10.1145/1344671.1344691},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/El-GhazawiL08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/FangR08,
author = {Wei Mark Fang and
Jonathan Rose},
editor = {Mike Hutton and
Paul Chow},
title = {Modeling routing demand for early-stage {FPGA} architecture development},
booktitle = {Proceedings of the {ACM/SIGDA} 16th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2008, Monterey, California, USA,
February 24-26, 2008},
pages = {139--148},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1344671.1344694},
doi = {10.1145/1344671.1344694},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/FangR08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/FrederickS08,
author = {Michael T. Frederick and
Arun K. Somani},
editor = {Mike Hutton and
Paul Chow},
title = {Beyond the arithmetic constraint: depth-optimal mapping of logic chains
in LUT-based FPGAs},
booktitle = {Proceedings of the {ACM/SIGDA} 16th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2008, Monterey, California, USA,
February 24-26, 2008},
pages = {37--46},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1344671.1344679},
doi = {10.1145/1344671.1344679},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/FrederickS08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/HaselmanMLH08,
author = {Michael Haselman and
Robert Miyaoka and
Thomas K. Lewellen and
Scott Hauck},
editor = {Mike Hutton and
Paul Chow},
title = {Fpga-based data acquisition system for a positron emission tomography
{(PET)} scanner},
booktitle = {Proceedings of the {ACM/SIGDA} 16th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2008, Monterey, California, USA,
February 24-26, 2008},
pages = {264},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1344671.1344727},
doi = {10.1145/1344671.1344727},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/HaselmanMLH08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/JangCCM08,
author = {Stephen Jang and
Billy Chan and
Kevin Chung and
Alan Mishchenko},
editor = {Mike Hutton and
Paul Chow},
title = {WireMap: {FPGA} technology mapping for improved routability},
booktitle = {Proceedings of the {ACM/SIGDA} 16th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2008, Monterey, California, USA,
February 24-26, 2008},
pages = {47--55},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1344671.1344680},
doi = {10.1145/1344671.1344680},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/JangCCM08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/JordanV08,
author = {Matthew Collin Jordan and
Ramachandran Vaidyanathan},
editor = {Mike Hutton and
Paul Chow},
title = {Configurable decoders with application in fast partial reconfiguration
of FPGAs},
booktitle = {Proceedings of the {ACM/SIGDA} 16th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2008, Monterey, California, USA,
February 24-26, 2008},
pages = {259},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1344671.1344715},
doi = {10.1145/1344671.1344715},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/JordanV08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/KelmL08,
author = {John H. Kelm and
Steven S. Lumetta},
editor = {Mike Hutton and
Paul Chow},
title = {HybridOS: runtime support for reconfigurable accelerators},
booktitle = {Proceedings of the {ACM/SIGDA} 16th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2008, Monterey, California, USA,
February 24-26, 2008},
pages = {212--221},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1344671.1344703},
doi = {10.1145/1344671.1344703},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/KelmL08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/KuonR08,
author = {Ian Kuon and
Jonathan Rose},
editor = {Mike Hutton and
Paul Chow},
title = {Area and delay trade-offs in the circuit and architecture design of
FPGAs},
booktitle = {Proceedings of the {ACM/SIGDA} 16th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2008, Monterey, California, USA,
February 24-26, 2008},
pages = {149--158},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1344671.1344695},
doi = {10.1145/1344671.1344695},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/KuonR08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/LemieuxE08,
author = {Guy G. Lemieux and
Tarek A. El{-}Ghazawi},
editor = {Mike Hutton and
Paul Chow},
title = {Designing with extreme parallelism},
booktitle = {Proceedings of the {ACM/SIGDA} 16th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2008, Monterey, California, USA,
February 24-26, 2008},
pages = {1--2},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1344671.1344673},
doi = {10.1145/1344671.1344673},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/LemieuxE08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/Lin08,
author = {Mingjie Lin},
editor = {Mike Hutton and
Paul Chow},
title = {The amorphous {FPGA} architecture},
booktitle = {Proceedings of the {ACM/SIGDA} 16th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2008, Monterey, California, USA,
February 24-26, 2008},
pages = {191--200},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1344671.1344700},
doi = {10.1145/1344671.1344700},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/Lin08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/LinG08,
author = {Mingjie Lin and
Abbas El Gamal},
editor = {Mike Hutton and
Paul Chow},
title = {{TORCH:} a design tool for routing channel segmentation in FPGAs},
booktitle = {Proceedings of the {ACM/SIGDA} 16th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2008, Monterey, California, USA,
February 24-26, 2008},
pages = {131--138},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1344671.1344693},
doi = {10.1145/1344671.1344693},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/LinG08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/LudwinBP08,
author = {Adrian Ludwin and
Vaughn Betz and
Ketan Padalia},
editor = {Mike Hutton and
Paul Chow},
title = {High-quality, deterministic parallel placement for FPGAs on commodity
hardware},
booktitle = {Proceedings of the {ACM/SIGDA} 16th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2008, Monterey, California, USA,
February 24-26, 2008},
pages = {14--23},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1344671.1344676},
doi = {10.1145/1344671.1344676},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/LudwinBP08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/MahajanSPWW08,
author = {Atul Mahajan and
Benfano Soewito and
Sai K. Parsi and
Ning Weng and
Haibo Wang},
editor = {Mike Hutton and
Paul Chow},
title = {Implementing high-speed string matching hardware for network intrusion
detection systems},
booktitle = {Proceedings of the {ACM/SIGDA} 16th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2008, Monterey, California, USA,
February 24-26, 2008},
pages = {264},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1344671.1344726},
doi = {10.1145/1344671.1344726},
timestamp = {Thu, 09 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/MahajanSPWW08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/MakSCL08,
author = {Terrence S. T. Mak and
N. Pete Sedcole and
Peter Y. K. Cheung and
Wayne Luk},
editor = {Mike Hutton and
Paul Chow},
title = {High-throughput interconnect wave-pipelining for global communication
in FPGAs},
booktitle = {Proceedings of the {ACM/SIGDA} 16th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2008, Monterey, California, USA,
February 24-26, 2008},
pages = {258},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1344671.1344714},
doi = {10.1145/1344671.1344714},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/MakSCL08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/MatsubayashiNASO08,
author = {Hidenori Matsubayashi and
Shinsuke Nino and
Toru Aramaki and
Yuichiro Shibata and
Kiyoshi Oguri},
editor = {Mike Hutton and
Paul Chow},
title = {Retrieving 3-d information with FPGA-based stream processing},
booktitle = {Proceedings of the {ACM/SIGDA} 16th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2008, Monterey, California, USA,
February 24-26, 2008},
pages = {261},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1344671.1344721},
doi = {10.1145/1344671.1344721},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/MatsubayashiNASO08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/McKechnieLV08,
author = {Paul Edward McKechnie and
Nathan A. Lindop and
Wim Vanderbauwhede},
editor = {Mike Hutton and
Paul Chow},
title = {A type system for static typing of a domain-specific language},
booktitle = {Proceedings of the {ACM/SIGDA} 16th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2008, Monterey, California, USA,
February 24-26, 2008},
pages = {258},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1344671.1344712},
doi = {10.1145/1344671.1344712},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/McKechnieLV08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/MinkovichC08,
author = {Kirill Minkovich and
Jason Cong},
editor = {Mike Hutton and
Paul Chow},
title = {Mapping for better than worst-case delays in LUT-based {FPGA} designs},
booktitle = {Proceedings of the {ACM/SIGDA} 16th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2008, Monterey, California, USA,
February 24-26, 2008},
pages = {56--64},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1344671.1344681},
doi = {10.1145/1344671.1344681},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/MinkovichC08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/MoazeniVGS08,
author = {Maryam Moazeni and
Alireza Vahdatpour and
Karthik Gururaj and
Majid Sarrafzadeh},
editor = {Mike Hutton and
Paul Chow},
title = {Communication bottleneck in hardware-software partitioning},
booktitle = {Proceedings of the {ACM/SIGDA} 16th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2008, Monterey, California, USA,
February 24-26, 2008},
pages = {262},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1344671.1344722},
doi = {10.1145/1344671.1344722},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/MoazeniVGS08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/NoteR08,
author = {Jean{-}Baptiste Note and
{\'{E}}ric Rannaud},
editor = {Mike Hutton and
Paul Chow},
title = {From the bitstream to the netlist},
booktitle = {Proceedings of the {ACM/SIGDA} 16th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2008, Monterey, California, USA,
February 24-26, 2008},
pages = {264},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1344671.1344729},
doi = {10.1145/1344671.1344729},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/NoteR08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/Parandeh-AfsharBI08,
author = {Hadi Parandeh{-}Afshar and
Philip Brisk and
Paolo Ienne},
editor = {Mike Hutton and
Paul Chow},
title = {A novel {FPGA} logic block for improved arithmetic performance},
booktitle = {Proceedings of the {ACM/SIGDA} 16th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2008, Monterey, California, USA,
February 24-26, 2008},
pages = {171--180},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1344671.1344698},
doi = {10.1145/1344671.1344698},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/Parandeh-AfsharBI08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/PellauerVAAE08,
author = {Michael Pellauer and
Muralidaran Vijayaraghavan and
Michael Adler and
Arvind and
Joel S. Emer},
editor = {Mike Hutton and
Paul Chow},
title = {A-Ports: an efficient abstraction for cycle-accurate performance models
on FPGAs},
booktitle = {Proceedings of the {ACM/SIGDA} 16th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2008, Monterey, California, USA,
February 24-26, 2008},
pages = {87--96},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1344671.1344685},
doi = {10.1145/1344671.1344685},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/PellauerVAAE08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/PutnamBDMS08,
author = {Andrew Putnam and
Dave Bennett and
Eric Dellinger and
Jeff Mason and
Prasanna Sundararajan},
editor = {Mike Hutton and
Paul Chow},
title = {CHiMPS: a high-level compilation flow for hybrid {CPU-FPGA} architectures},
booktitle = {Proceedings of the {ACM/SIGDA} 16th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2008, Monterey, California, USA,
February 24-26, 2008},
pages = {261},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1344671.1344720},
doi = {10.1145/1344671.1344720},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/PutnamBDMS08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/Rangel-MagdalenoRCG08,
author = {Jose de Jesus Rangel{-}Magdaleno and
Ren{\'{e}} de Jes{\'{u}}s Romero{-}Troncoso and
Luis Miguel Contreras{-}Medina and
Arturo Garcia{-}Perez},
editor = {Mike Hutton and
Paul Chow},
title = {{FPGA} implementation of a novel algorithm for on-line bar breakage
detection on induction motors},
booktitle = {Proceedings of the {ACM/SIGDA} 16th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2008, Monterey, California, USA,
February 24-26, 2008},
pages = {263},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1344671.1344725},
doi = {10.1145/1344671.1344725},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/Rangel-MagdalenoRCG08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/SedcoleWC08,
author = {N. Pete Sedcole and
Justin S. J. Wong and
Peter Y. K. Cheung},
editor = {Mike Hutton and
Paul Chow},
title = {Measuring and modeling {FPGA} clock variability},
booktitle = {Proceedings of the {ACM/SIGDA} 16th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2008, Monterey, California, USA,
February 24-26, 2008},
pages = {258},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1344671.1344713},
doi = {10.1145/1344671.1344713},
timestamp = {Wed, 03 Apr 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/SedcoleWC08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/SheldonV08,
author = {David Sheldon and
Frank Vahid},
editor = {Mike Hutton and
Paul Chow},
title = {A pipelined binary tree as a case study on designing efficient circuits
for an {FPGA} in a bram aware design},
booktitle = {Proceedings of the {ACM/SIGDA} 16th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2008, Monterey, California, USA,
February 24-26, 2008},
pages = {264},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1344671.1344728},
doi = {10.1145/1344671.1344728},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/SheldonV08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/SirowySV08,
author = {Scott Sirowy and
Greg Stitt and
Frank Vahid},
editor = {Mike Hutton and
Paul Chow},
title = {C is for circuits: capturing {FPGA} circuits as sequential code for
portability},
booktitle = {Proceedings of the {ACM/SIGDA} 16th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2008, Monterey, California, USA,
February 24-26, 2008},
pages = {117--126},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1344671.1344689},
doi = {10.1145/1344671.1344689},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/SirowySV08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/So08,
author = {Keith So},
editor = {Mike Hutton and
Paul Chow},
title = {Enforcing long-path timing closure for {FPGA} routing with path searches
on clamped lexicographic spirals},
booktitle = {Proceedings of the {ACM/SIGDA} 16th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2008, Monterey, California, USA,
February 24-26, 2008},
pages = {24--34},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1344671.1344677},
doi = {10.1145/1344671.1344677},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/So08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/SugiharaKKO08,
author = {Yuuri Sugihara and
Yohei Kume and
Kazutoshi Kobayashi and
Hidetoshi Onodera},
editor = {Mike Hutton and
Paul Chow},
title = {Speed and yield enhancement by track swapping on critical paths utilizing
random variations for FPGAs},
booktitle = {Proceedings of the {ACM/SIGDA} 16th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2008, Monterey, California, USA,
February 24-26, 2008},
pages = {257},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1344671.1344711},
doi = {10.1145/1344671.1344711},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/SugiharaKKO08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/ThomasL08,
author = {David B. Thomas and
Wayne Luk},
editor = {Mike Hutton and
Paul Chow},
title = {FPGA-optimised high-quality uniform random number generators},
booktitle = {Proceedings of the {ACM/SIGDA} 16th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2008, Monterey, California, USA,
February 24-26, 2008},
pages = {235--244},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1344671.1344706},
doi = {10.1145/1344671.1344706},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/ThomasL08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/WangL08,
author = {Xiaojun Wang and
Miriam Leeser},
editor = {Mike Hutton and
Paul Chow},
title = {Efficient {FPGA} implementation of qr decomposition using a systolic
array architecture},
booktitle = {Proceedings of the {ACM/SIGDA} 16th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2008, Monterey, California, USA,
February 24-26, 2008},
pages = {260},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1344671.1344718},
doi = {10.1145/1344671.1344718},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/WangL08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/YuCL08,
author = {Haile Yu and
Yuk Hei Chan and
Philip Heng Wai Leong},
editor = {Mike Hutton and
Paul Chow},
title = {{FPGA} interconnect design using logical effort},
booktitle = {Proceedings of the {ACM/SIGDA} 16th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2008, Monterey, California, USA,
February 24-26, 2008},
pages = {257},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1344671.1344710},
doi = {10.1145/1344671.1344710},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/YuCL08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/YuLE08,
author = {Jason Yu and
Guy G. Lemieux and
Christopher Eagleston},
editor = {Mike Hutton and
Paul Chow},
title = {Vector processing as a soft-core {CPU} accelerator},
booktitle = {Proceedings of the {ACM/SIGDA} 16th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2008, Monterey, California, USA,
February 24-26, 2008},
pages = {222--232},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1344671.1344704},
doi = {10.1145/1344671.1344704},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/YuLE08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/fpga/2008,
editor = {Mike Hutton and
Paul Chow},
title = {Proceedings of the {ACM/SIGDA} 16th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2008, Monterey, California, USA,
February 24-26, 2008},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1344671},
doi = {10.1145/1344671},
isbn = {978-1-59593-934-0},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/2008.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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