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@inproceedings{DBLP:conf/dft/BasemanDBMTFSS18,
  author       = {Elisabeth Baseman and
                  Nathan DeBardeleben and
                  Sean Blanchard and
                  Juston S. Moore and
                  Olena Tkachenko and
                  Kurt B. Ferreira and
                  Taniya Siddiqua and
                  Vilas Sridharan},
  title        = {Physics-Informed Machine Learning for {DRAM} Error Modeling},
  booktitle    = {2018 {IEEE} International Symposium on Defect and Fault Tolerance
                  in {VLSI} and Nanotechnology Systems, {DFT} 2018, Chicago, IL, USA,
                  October 8-10, 2018},
  pages        = {1--6},
  publisher    = {{IEEE} Computer Society},
  year         = {2018},
  url          = {https://doi.org/10.1109/DFT.2018.8602983},
  doi          = {10.1109/DFT.2018.8602983},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/dft/BasemanDBMTFSS18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/dft/BozzoliS18,
  author       = {Ludovica Bozzoli and
                  Luca Sterpone},
  title        = {MATS**: An On-Line Testing Approach for Reconfigurable Embedded Memories},
  booktitle    = {2018 {IEEE} International Symposium on Defect and Fault Tolerance
                  in {VLSI} and Nanotechnology Systems, {DFT} 2018, Chicago, IL, USA,
                  October 8-10, 2018},
  pages        = {1--6},
  publisher    = {{IEEE} Computer Society},
  year         = {2018},
  url          = {https://doi.org/10.1109/DFT.2018.8602934},
  doi          = {10.1109/DFT.2018.8602934},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/dft/BozzoliS18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/dft/BuCK18,
  author       = {Lake Bu and
                  Hai Cheng and
                  Michel A. Kinsy},
  title        = {Fast Dynamic Device Authentication Based on Lorenz Chaotic Systems},
  booktitle    = {2018 {IEEE} International Symposium on Defect and Fault Tolerance
                  in {VLSI} and Nanotechnology Systems, {DFT} 2018, Chicago, IL, USA,
                  October 8-10, 2018},
  pages        = {1--6},
  publisher    = {{IEEE} Computer Society},
  year         = {2018},
  url          = {https://doi.org/10.1109/DFT.2018.8602986},
  doi          = {10.1109/DFT.2018.8602986},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/dft/BuCK18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/dft/ChapmanTMKK18,
  author       = {Glenn H. Chapman and
                  Rohan Thomas and
                  Klinsmann J. Coelho Silva Meneses and
                  Israel Koren and
                  Zahava Koren},
  title        = {Analysis of Single Event Upsets Based on Digital Cameras with Very
                  Small Pixels},
  booktitle    = {2018 {IEEE} International Symposium on Defect and Fault Tolerance
                  in {VLSI} and Nanotechnology Systems, {DFT} 2018, Chicago, IL, USA,
                  October 8-10, 2018},
  pages        = {1--6},
  publisher    = {{IEEE} Computer Society},
  year         = {2018},
  url          = {https://doi.org/10.1109/DFT.2018.8602867},
  doi          = {10.1109/DFT.2018.8602867},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/dft/ChapmanTMKK18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/dft/CoelhoCZV18,
  author       = {Alexandre Coelho and
                  Amir Charif and
                  Nacer{-}Eddine Zergainoh and
                  Raoul Velazco},
  title        = {A Runtime Fault-Tolerant Routing Scheme for Partially Connected 3D
                  Networks-on-Chip},
  booktitle    = {2018 {IEEE} International Symposium on Defect and Fault Tolerance
                  in {VLSI} and Nanotechnology Systems, {DFT} 2018, Chicago, IL, USA,
                  October 8-10, 2018},
  pages        = {1--6},
  publisher    = {{IEEE} Computer Society},
  year         = {2018},
  url          = {https://doi.org/10.1109/DFT.2018.8602971},
  doi          = {10.1109/DFT.2018.8602971},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/dft/CoelhoCZV18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/dft/DasT18,
  author       = {Abhishek Das and
                  Nur A. Touba},
  title        = {Efficient Non-Binary Hamming Codes for Limited Magnitude Errors in
                  {MLC} PCMs},
  booktitle    = {2018 {IEEE} International Symposium on Defect and Fault Tolerance
                  in {VLSI} and Nanotechnology Systems, {DFT} 2018, Chicago, IL, USA,
                  October 8-10, 2018},
  pages        = {1--6},
  publisher    = {{IEEE} Computer Society},
  year         = {2018},
  url          = {https://doi.org/10.1109/DFT.2018.8602848},
  doi          = {10.1109/DFT.2018.8602848},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/dft/DasT18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/dft/FloridiaS18,
  author       = {Andrea Floridia and
                  Ernesto S{\'{a}}nchez},
  title        = {Hybrid On-Line Self-Test Strategy for Dual-Core Lockstep Processors},
  booktitle    = {2018 {IEEE} International Symposium on Defect and Fault Tolerance
                  in {VLSI} and Nanotechnology Systems, {DFT} 2018, Chicago, IL, USA,
                  October 8-10, 2018},
  pages        = {1--6},
  publisher    = {{IEEE} Computer Society},
  year         = {2018},
  url          = {https://doi.org/10.1109/DFT.2018.8602982},
  doi          = {10.1109/DFT.2018.8602982},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/dft/FloridiaS18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/dft/FuranoTSFBAMKWD18,
  author       = {Gianluca Furano and
                  Antonis Tavoularis and
                  Lucana Santos and
                  Veronique Ferlet{-}Cavrois and
                  Cesar Boatella and
                  Ruben Garcia Alia and
                  Pablo Fern{\'{a}}ndez{-}Mart{\'{\i}}nez and
                  Maria Kastriotou and
                  Vanessa Wyrwoll and
                  Salvatore Danzeca and
                  Maris Tali and
                  Dejan Gacnik and
                  Iztok Kramberger and
                  Lars Juul and
                  Konstantinos Maragos and
                  George Lentaris},
  title        = {{FPGA} {SEE} Test with Ultra-High Energy Heavy Ions},
  booktitle    = {2018 {IEEE} International Symposium on Defect and Fault Tolerance
                  in {VLSI} and Nanotechnology Systems, {DFT} 2018, Chicago, IL, USA,
                  October 8-10, 2018},
  pages        = {1--4},
  publisher    = {{IEEE} Computer Society},
  year         = {2018},
  url          = {https://doi.org/10.1109/DFT.2018.8602958},
  doi          = {10.1109/DFT.2018.8602958},
  timestamp    = {Wed, 31 Jan 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/dft/FuranoTSFBAMKWD18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/dft/GaoYZHR18,
  author       = {Zhen Gao and
                  Lina Yan and
                  Jinhua Zhu and
                  Ruishi Han and
                  Pedro Reviriego},
  title        = {Analysis of the Effects of Single Event Upsets (SEUs) on User Memory
                  in {FPGA} Implemented Viterbi Decoders},
  booktitle    = {2018 {IEEE} International Symposium on Defect and Fault Tolerance
                  in {VLSI} and Nanotechnology Systems, {DFT} 2018, Chicago, IL, USA,
                  October 8-10, 2018},
  pages        = {1--6},
  publisher    = {{IEEE} Computer Society},
  year         = {2018},
  url          = {https://doi.org/10.1109/DFT.2018.8602988},
  doi          = {10.1109/DFT.2018.8602988},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/dft/GaoYZHR18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/dft/GuptaKMO18,
  author       = {Vishal Gupta and
                  Saurabh Khandelwal and
                  Jimson Mathew and
                  Marco Ottavi},
  title        = {45nm Bit-Interleaving Differential 10T Low Leakage FinFET Based {SRAM}
                  with Column-Wise Write Access Control},
  booktitle    = {2018 {IEEE} International Symposium on Defect and Fault Tolerance
                  in {VLSI} and Nanotechnology Systems, {DFT} 2018, Chicago, IL, USA,
                  October 8-10, 2018},
  pages        = {1--6},
  publisher    = {{IEEE} Computer Society},
  year         = {2018},
  url          = {https://doi.org/10.1109/DFT.2018.8602981},
  doi          = {10.1109/DFT.2018.8602981},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/dft/GuptaKMO18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/dft/JavvajiT18,
  author       = {Pavan Kumar Javvaji and
                  Spyros Tragoudas},
  title        = {A Method to Model Statistical Path Delays for Accurate Defect Coverage},
  booktitle    = {2018 {IEEE} International Symposium on Defect and Fault Tolerance
                  in {VLSI} and Nanotechnology Systems, {DFT} 2018, Chicago, IL, USA,
                  October 8-10, 2018},
  pages        = {1--6},
  publisher    = {{IEEE} Computer Society},
  year         = {2018},
  url          = {https://doi.org/10.1109/DFT.2018.8602962},
  doi          = {10.1109/DFT.2018.8602962},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/dft/JavvajiT18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/dft/JunsangsriL18,
  author       = {Pilin Junsangsri and
                  Fabrizio Lombardi},
  title        = {Multiple Fault Detection in Nano Programmable Logic Arrays},
  booktitle    = {2018 {IEEE} International Symposium on Defect and Fault Tolerance
                  in {VLSI} and Nanotechnology Systems, {DFT} 2018, Chicago, IL, USA,
                  October 8-10, 2018},
  pages        = {1--6},
  publisher    = {{IEEE} Computer Society},
  year         = {2018},
  url          = {https://doi.org/10.1109/DFT.2018.8602985},
  doi          = {10.1109/DFT.2018.8602985},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/dft/JunsangsriL18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/dft/OlowogemoRL18,
  author       = {Semiu A. Olowogemo and
                  William H. Robinson and
                  Daniel B. Limbrick},
  title        = {Effects of Voltage and Temperature Variations on the Electrical Masking
                  Capability of Sub-65 nm Combinational Logic Circuits},
  booktitle    = {2018 {IEEE} International Symposium on Defect and Fault Tolerance
                  in {VLSI} and Nanotechnology Systems, {DFT} 2018, Chicago, IL, USA,
                  October 8-10, 2018},
  pages        = {1--6},
  publisher    = {{IEEE} Computer Society},
  year         = {2018},
  url          = {https://doi.org/10.1109/DFT.2018.8602975},
  doi          = {10.1109/DFT.2018.8602975},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/dft/OlowogemoRL18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/dft/PaliaroutisTEDS18,
  author       = {Georgios Ioannis Paliaroutis and
                  Pelopidas Tsoumanis and
                  Nestor E. Evmorfopoulos and
                  George Dimitriou and
                  Georgios I. Stamoulis},
  title        = {A Placement-Aware Soft Error Rate Estimation of Combinational Circuits
                  for Multiple Transient Faults in {CMOS} Technology},
  booktitle    = {2018 {IEEE} International Symposium on Defect and Fault Tolerance
                  in {VLSI} and Nanotechnology Systems, {DFT} 2018, Chicago, IL, USA,
                  October 8-10, 2018},
  pages        = {1--6},
  publisher    = {{IEEE} Computer Society},
  year         = {2018},
  url          = {https://doi.org/10.1109/DFT.2018.8602855},
  doi          = {10.1109/DFT.2018.8602855},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/dft/PaliaroutisTEDS18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/dft/PellegriniOMN18,
  author       = {Danilo Pellegrini and
                  Marco Ottavi and
                  Eugenio Martinelli and
                  Corrado Di Natale},
  title        = {Complementary Resistive Switch Sensing},
  booktitle    = {2018 {IEEE} International Symposium on Defect and Fault Tolerance
                  in {VLSI} and Nanotechnology Systems, {DFT} 2018, Chicago, IL, USA,
                  October 8-10, 2018},
  pages        = {1--5},
  publisher    = {{IEEE} Computer Society},
  year         = {2018},
  url          = {https://doi.org/10.1109/DFT.2018.8602976},
  doi          = {10.1109/DFT.2018.8602976},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/dft/PellegriniOMN18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/dft/Pomeranz18,
  author       = {Irith Pomeranz},
  title        = {Postprocessing Procedure for Reducing the Faulty Switching Activity
                  of a Low-Power Test Set},
  booktitle    = {2018 {IEEE} International Symposium on Defect and Fault Tolerance
                  in {VLSI} and Nanotechnology Systems, {DFT} 2018, Chicago, IL, USA,
                  October 8-10, 2018},
  pages        = {1--6},
  publisher    = {{IEEE} Computer Society},
  year         = {2018},
  url          = {https://doi.org/10.1109/DFT.2018.8602967},
  doi          = {10.1109/DFT.2018.8602967},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/dft/Pomeranz18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/dft/SavanurT18,
  author       = {Puneet Ramesh Savanur and
                  Spyros Tragoudas},
  title        = {Threshold Voltage Extraction Using Static {NBTI} Aging},
  booktitle    = {2018 {IEEE} International Symposium on Defect and Fault Tolerance
                  in {VLSI} and Nanotechnology Systems, {DFT} 2018, Chicago, IL, USA,
                  October 8-10, 2018},
  pages        = {1--6},
  publisher    = {{IEEE} Computer Society},
  year         = {2018},
  url          = {https://doi.org/10.1109/DFT.2018.8602814},
  doi          = {10.1109/DFT.2018.8602814},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/dft/SavanurT18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/dft/SchutzSHL18,
  author       = {Markus Sch{\"{u}}tz and
                  Andreas Steininger and
                  Florian Huemer and
                  Jakob Lechner},
  title        = {State Recovery for Coarse-Grain {TMR} Designs in FPGAs Using Partial
                  Reconfiguration},
  booktitle    = {2018 {IEEE} International Symposium on Defect and Fault Tolerance
                  in {VLSI} and Nanotechnology Systems, {DFT} 2018, Chicago, IL, USA,
                  October 8-10, 2018},
  pages        = {1--6},
  publisher    = {{IEEE} Computer Society},
  year         = {2018},
  url          = {https://doi.org/10.1109/DFT.2018.8602984},
  doi          = {10.1109/DFT.2018.8602984},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/dft/SchutzSHL18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/dft/TasoulasGA18,
  author       = {Zois{-}Gerasimos Tasoulas and
                  Ryan Guss and
                  Iraklis Anagnostopoulos},
  title        = {Performance-Based and Aging-Aware Resource Allocation for Concurrent
                  {GPU} Applications},
  booktitle    = {2018 {IEEE} International Symposium on Defect and Fault Tolerance
                  in {VLSI} and Nanotechnology Systems, {DFT} 2018, Chicago, IL, USA,
                  October 8-10, 2018},
  pages        = {1--6},
  publisher    = {{IEEE} Computer Society},
  year         = {2018},
  url          = {https://doi.org/10.1109/DFT.2018.8602850},
  doi          = {10.1109/DFT.2018.8602850},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/dft/TasoulasGA18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/dft/TraiolaV0BB18,
  author       = {Marcello Traiola and
                  Arnaud Virazel and
                  Patrick Girard and
                  Mario Barbareschi and
                  Alberto Bosio},
  title        = {Investigation of Mean-Error Metrics for Testing Approximate Integrated
                  Circuits},
  booktitle    = {2018 {IEEE} International Symposium on Defect and Fault Tolerance
                  in {VLSI} and Nanotechnology Systems, {DFT} 2018, Chicago, IL, USA,
                  October 8-10, 2018},
  pages        = {1--6},
  publisher    = {{IEEE} Computer Society},
  year         = {2018},
  url          = {https://doi.org/10.1109/DFT.2018.8602939},
  doi          = {10.1109/DFT.2018.8602939},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/dft/TraiolaV0BB18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/dft/WangPBEV18,
  author       = {Naixing Wang and
                  Irith Pomeranz and
                  Brady Benware and
                  M. Enamul Amyeen and
                  Srikanth Venkataraman},
  title        = {Improving the Resolution of Multiple Defect Diagnosis by Removing
                  and Selecting Tests},
  booktitle    = {2018 {IEEE} International Symposium on Defect and Fault Tolerance
                  in {VLSI} and Nanotechnology Systems, {DFT} 2018, Chicago, IL, USA,
                  October 8-10, 2018},
  pages        = {1--6},
  publisher    = {{IEEE} Computer Society},
  year         = {2018},
  url          = {https://doi.org/10.1109/DFT.2018.8602935},
  doi          = {10.1109/DFT.2018.8602935},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/dft/WangPBEV18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/dft/WilkeningPKGRS18,
  author       = {Mark Wilkening and
                  Fritz Previlon and
                  David R. Kaeli and
                  Sudhanva Gurumurthi and
                  Steven Raasch and
                  Vilas Sridharan},
  title        = {Evaluating the Resilience of Parallel Applications},
  booktitle    = {2018 {IEEE} International Symposium on Defect and Fault Tolerance
                  in {VLSI} and Nanotechnology Systems, {DFT} 2018, Chicago, IL, USA,
                  October 8-10, 2018},
  pages        = {1--6},
  publisher    = {{IEEE} Computer Society},
  year         = {2018},
  url          = {https://doi.org/10.1109/DFT.2018.8602987},
  doi          = {10.1109/DFT.2018.8602987},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/dft/WilkeningPKGRS18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/dft/YamamotoN18,
  author       = {Yuta Yamamoto and
                  Kazuteru Namba},
  title        = {Construction of Latch Design with Complete Double Node Upset Tolerant
                  Capability Using C-Element},
  booktitle    = {2018 {IEEE} International Symposium on Defect and Fault Tolerance
                  in {VLSI} and Nanotechnology Systems, {DFT} 2018, Chicago, IL, USA,
                  October 8-10, 2018},
  pages        = {1--6},
  publisher    = {{IEEE} Computer Society},
  year         = {2018},
  url          = {https://doi.org/10.1109/DFT.2018.8602841},
  doi          = {10.1109/DFT.2018.8602841},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/dft/YamamotoN18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@proceedings{DBLP:conf/dft/2018,
  title        = {2018 {IEEE} International Symposium on Defect and Fault Tolerance
                  in {VLSI} and Nanotechnology Systems, {DFT} 2018, Chicago, IL, USA,
                  October 8-10, 2018},
  publisher    = {{IEEE} Computer Society},
  year         = {2018},
  url          = {https://ieeexplore.ieee.org/xpl/conhome/8586781/proceeding},
  isbn         = {978-1-5386-8398-9},
  timestamp    = {Wed, 16 Oct 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/dft/2018.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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