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@article{DBLP:journals/trets/AnupreethamIHBKMNBCS24, author = {Anupreetham Anupreetham and Mohamed Ibrahim and Mathew Hall and Andrew Boutros and Ajay Kuzhively and Abinash Mohanty and Eriko Nurvitadhi and Vaughn Betz and Yu Cao and Jae{-}Sun Seo}, title = {High Throughput FPGA-Based Object Detection via Algorithm-Hardware Co-Design}, journal = {{ACM} Trans. Reconfigurable Technol. Syst.}, volume = {17}, number = {1}, pages = {1:1--1:20}, year = {2024}, url = {https://doi.org/10.1145/3634919}, doi = {10.1145/3634919}, timestamp = {Mon, 15 Apr 2024 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/trets/AnupreethamIHBKMNBCS24.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/trets/ChenJHHM24, author = {Jeffrey Chen and Sang{-}Woo Jun and Sehwan Hong and Warrick He and Jinyeong Moon}, title = {Eciton: Very Low-power Recurrent Neural Network Accelerator for Real-time Inference at the Edge}, journal = {{ACM} Trans. Reconfigurable Technol. Syst.}, volume = {17}, number = {1}, pages = {16:1--16:25}, year = {2024}, url = {https://doi.org/10.1145/3629979}, doi = {10.1145/3629979}, timestamp = {Mon, 15 Apr 2024 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/trets/ChenJHHM24.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/trets/FanHLXGHP24, author = {Zimeng Fan and Wei Hu and Fang Liu and Dian Xu and Hong Guo and Yanxiang He and Min Peng}, title = {A Hardware Design Framework for Computer Vision Models Based on Reconfigurable Devices}, journal = {{ACM} Trans. Reconfigurable Technol. Syst.}, volume = {17}, number = {1}, pages = {2:1--2:31}, year = {2024}, url = {https://doi.org/10.1145/3635157}, doi = {10.1145/3635157}, timestamp = {Mon, 15 Apr 2024 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/trets/FanHLXGHP24.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/trets/GohringerKK24, author = {Diana G{\"{o}}hringer and Georgios Keramidas and Akash Kumar}, title = {Introduction to the {FPL} 2021 Special Section}, journal = {{ACM} Trans. Reconfigurable Technol. Syst.}, volume = {17}, number = {1}, pages = {13:1--13:2}, year = {2024}, url = {https://doi.org/10.1145/3635115}, doi = {10.1145/3635115}, timestamp = {Mon, 15 Apr 2024 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/trets/GohringerKK24.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/trets/HaslerH24, author = {Jennifer Hasler and Cong Hao}, title = {Programmable Analog System Benchmarks Leading to Efficient Analog Computation Synthesis}, journal = {{ACM} Trans. Reconfigurable Technol. Syst.}, volume = {17}, number = {1}, pages = {12:1--12:25}, year = {2024}, url = {https://doi.org/10.1145/3625298}, doi = {10.1145/3625298}, timestamp = {Mon, 15 Apr 2024 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/trets/HaslerH24.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/trets/HonoratDMN24, author = {Alexandre Honorat and Micka{\"{e}}l Dardaillon and Hugo Miomandre and Jean{-}Fran{\c{c}}ois Nezan}, title = {Automated Buffer Sizing of Dataflow Applications in a High-level Synthesis Workflow}, journal = {{ACM} Trans. Reconfigurable Technol. Syst.}, volume = {17}, number = {1}, pages = {8:1--8:26}, year = {2024}, url = {https://doi.org/10.1145/3626103}, doi = {10.1145/3626103}, timestamp = {Sat, 04 May 2024 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/trets/HonoratDMN24.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/trets/KalomirosVV24, author = {John A. Kalomiros and John V. Vourvoulakis and Stavros Vologiannidis}, title = {A Hardware Accelerator for the Semi-Global Matching Stereo Algorithm: An Efficient Implementation for the Stratix {V} and Zynq UltraScale+ {FPGA} Technology}, journal = {{ACM} Trans. Reconfigurable Technol. Syst.}, volume = {17}, number = {1}, pages = {5:1--5:25}, year = {2024}, url = {https://doi.org/10.1145/3615869}, doi = {10.1145/3615869}, timestamp = {Mon, 15 Apr 2024 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/trets/KalomirosVV24.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/trets/LiLSFXH24, author = {Yonggen Li and Xin Li and Haibin Shen and Jicong Fan and Yanfeng Xu and Kejie Huang}, title = {An All-digital Compute-in-memory {FPGA} Architecture for Deep Learning Acceleration}, journal = {{ACM} Trans. Reconfigurable Technol. Syst.}, volume = {17}, number = {1}, pages = {18:1--18:27}, year = {2024}, url = {https://doi.org/10.1145/3640469}, doi = {10.1145/3640469}, timestamp = {Mon, 15 Apr 2024 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/trets/LiLSFXH24.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/trets/LiuLYC24, author = {Zhengyan Liu and Qiang Liu and Shun Yan and Ray C. C. Cheung}, title = {An Efficient FPGA-based Depthwise Separable Convolutional Neural Network Accelerator with Hardware Pruning}, journal = {{ACM} Trans. Reconfigurable Technol. Syst.}, volume = {17}, number = {1}, pages = {15:1--15:20}, year = {2024}, url = {https://doi.org/10.1145/3615661}, doi = {10.1145/3615661}, timestamp = {Mon, 15 Apr 2024 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/trets/LiuLYC24.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/trets/MaschiA24, author = {Fabio Maschi and Gustavo Alonso}, title = {Strega: An {HTTP} Server for FPGAs}, journal = {{ACM} Trans. Reconfigurable Technol. Syst.}, volume = {17}, number = {1}, pages = {3:1--3:27}, year = {2024}, url = {https://doi.org/10.1145/3611312}, doi = {10.1145/3611312}, timestamp = {Mon, 15 Apr 2024 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/trets/MaschiA24.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/trets/MouraC24, author = {Rafael F{\~{a}}o de Moura and Luigi Carro}, title = {Reprogrammable Non-Linear Circuits Using ReRAM for {NN} Accelerators}, journal = {{ACM} Trans. Reconfigurable Technol. Syst.}, volume = {17}, number = {1}, pages = {7:1--7:19}, year = {2024}, url = {https://doi.org/10.1145/3617894}, doi = {10.1145/3617894}, timestamp = {Mon, 15 Apr 2024 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/trets/MouraC24.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/trets/NikolicI24, author = {Stefan Nikolic and Paolo Ienne}, title = {Exploring {FPGA} Switch-Blocks without Explicitly Listing Connectivity Patterns}, journal = {{ACM} Trans. Reconfigurable Technol. Syst.}, volume = {17}, number = {1}, pages = {14:1--14:39}, year = {2024}, url = {https://doi.org/10.1145/3597417}, doi = {10.1145/3597417}, timestamp = {Mon, 15 Apr 2024 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/trets/NikolicI24.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/trets/NoyezMPV24, author = {Louis Noyez and Nadia El Mrabet and Olivier Potin and Pascal V{\'{e}}ron}, title = {Montgomery Multiplication Scalable Systolic Designs Optimized for {DSP48E2}}, journal = {{ACM} Trans. Reconfigurable Technol. Syst.}, volume = {17}, number = {1}, pages = {9:1--9:31}, year = {2024}, url = {https://doi.org/10.1145/3624571}, doi = {10.1145/3624571}, timestamp = {Mon, 15 Apr 2024 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/trets/NoyezMPV24.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/trets/QiuMGCLYW24, author = {Yunhui Qiu and Yiqing Mao and Xuchen Gao and Sichao Chen and Jiangnan Li and Wenbo Yin and Lingli Wang}, title = {{FDRA:} {A} Framework for a Dynamically Reconfigurable Accelerator Supporting Multi-Level Parallelism}, journal = {{ACM} Trans. Reconfigurable Technol. Syst.}, volume = {17}, number = {1}, pages = {4:1--4:26}, year = {2024}, url = {https://doi.org/10.1145/3614224}, doi = {10.1145/3614224}, timestamp = {Mon, 15 Apr 2024 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/trets/QiuMGCLYW24.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/trets/ReisVN24, author = {Miguel Reis and M{\'{a}}rio P. V{\'{e}}stias and Hor{\'{a}}cio C. Neto}, title = {Designing Deep Learning Models on {FPGA} with Multiple Heterogeneous Engines}, journal = {{ACM} Trans. Reconfigurable Technol. Syst.}, volume = {17}, number = {1}, pages = {6:1--6:30}, year = {2024}, url = {https://doi.org/10.1145/3615870}, doi = {10.1145/3615870}, timestamp = {Sat, 04 May 2024 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/trets/ReisVN24.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/trets/SaniY24, author = {Sajjad Rostami Sani and Andy Gean Ye}, title = {Evaluating the Impact of Using Multiple-Metal Layers on the Layout Area of Switch Blocks for Tile-Based FPGAs in FinFET 7nm}, journal = {{ACM} Trans. Reconfigurable Technol. Syst.}, volume = {17}, number = {1}, pages = {17:1--17:29}, year = {2024}, url = {https://doi.org/10.1145/3639055}, doi = {10.1145/3639055}, timestamp = {Mon, 15 Apr 2024 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/trets/SaniY24.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/trets/SoleimaniCL24, author = {Parastoo Soleimani and David W. Capson and Kin Fun Li}, title = {A Partitioned {CAM} Architecture with {FPGA} Acceleration for Binary Descriptor Matching}, journal = {{ACM} Trans. Reconfigurable Technol. Syst.}, volume = {17}, number = {1}, pages = {10:1--10:21}, year = {2024}, url = {https://doi.org/10.1145/3624749}, doi = {10.1145/3624749}, timestamp = {Mon, 15 Apr 2024 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/trets/SoleimaniCL24.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/trets/WengMLKASMKDDK24, author = {Olivia Weng and Gabriel Marcano and Vladimir Loncar and Alireza Khodamoradi and G. Abarajithan and Nojan Sheybani and Andres Meza and Farinaz Koushanfar and Kristof Denolf and Javier Mauricio Duarte and Ryan Kastner}, title = {Tailor: Altering Skip Connections for Resource-Efficient Inference}, journal = {{ACM} Trans. Reconfigurable Technol. Syst.}, volume = {17}, number = {1}, pages = {11:1--11:23}, year = {2024}, url = {https://doi.org/10.1145/3624990}, doi = {10.1145/3624990}, timestamp = {Mon, 15 Apr 2024 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/trets/WengMLKASMKDDK24.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
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