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@inproceedings{DBLP:conf/slip/Cheng0KW23,
author = {Chung{-}Kuan Cheng and
Bill Lin and
Byeonggon Kang and
Yucheng Wang},
title = {Invited Paper: The Scope and Challenges of Scaling in Advanced Technologies},
booktitle = {Proceedings of the {ACM} International Workshop on System-Level Interconnect
Pathfinding, {SLIP} 2023, San Francisco, CA, USA, 2 November 2023},
pages = {6:1--6:8},
publisher = {{ACM}},
year = {2023},
url = {https://doi.org/10.1145/3632409.3632841},
doi = {10.1145/3632409.3632841},
timestamp = {Mon, 01 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/Cheng0KW23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/ChengK0WY23,
author = {Chung{-}Kuan Cheng and
Andrew B. Kahng and
Bill Lin and
Yucheng Wang and
Dooseok Yoon},
title = {Gear-Ratio-Aware Standard Cell Layout Framework for {DTCO} Exploration},
booktitle = {Proceedings of the {ACM} International Workshop on System-Level Interconnect
Pathfinding, {SLIP} 2023, San Francisco, CA, USA, 2 November 2023},
pages = {2:1--2:10},
publisher = {{ACM}},
year = {2023},
url = {https://doi.org/10.1145/3632409.3640475},
doi = {10.1145/3632409.3640475},
timestamp = {Mon, 01 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/ChengK0WY23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/LouageIS23,
author = {Marieke Louage and
Muhammad Mazher Iqbal and
Dirk Stroobandt},
title = {On the Interconnection Complexity vs Size Trade-off in Circuit Graphs},
booktitle = {Proceedings of the {ACM} International Workshop on System-Level Interconnect
Pathfinding, {SLIP} 2023, San Francisco, CA, USA, 2 November 2023},
pages = {1:1--1:7},
publisher = {{ACM}},
year = {2023},
url = {https://doi.org/10.1145/3632409.3632838},
doi = {10.1145/3632409.3632838},
timestamp = {Mon, 01 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/LouageIS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/Mohammadhassani23,
author = {Arghavan Mohammadhassani and
Anup Das},
title = {Improving Performance of Network-on-Memory Architectures via (De-)/Compression-in-DRAM},
booktitle = {Proceedings of the {ACM} International Workshop on System-Level Interconnect
Pathfinding, {SLIP} 2023, San Francisco, CA, USA, 2 November 2023},
pages = {4:1--4:10},
publisher = {{ACM}},
year = {2023},
url = {https://doi.org/10.1145/3632409.3640477},
doi = {10.1145/3632409.3640477},
timestamp = {Mon, 01 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/Mohammadhassani23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/ParkKK23,
author = {Seonghyeon Park and
Daeyeon Kim and
Seokhyeong Kang},
title = {Invited: Acceleration on Physical Design: Machine Learning-based Routability
Optimization},
booktitle = {Proceedings of the {ACM} International Workshop on System-Level Interconnect
Pathfinding, {SLIP} 2023, San Francisco, CA, USA, 2 November 2023},
pages = {5:1--5:6},
publisher = {{ACM}},
year = {2023},
url = {https://doi.org/10.1145/3632409.3632840},
doi = {10.1145/3632409.3632840},
timestamp = {Mon, 01 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/ParkKK23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/RaikarS23,
author = {Raveena Raikar and
Dirk Stroobandt},
title = {Modularity Driven Parallel Placement Algorithm for 2.5D {FPGA} Architectures},
booktitle = {Proceedings of the {ACM} International Workshop on System-Level Interconnect
Pathfinding, {SLIP} 2023, San Francisco, CA, USA, 2 November 2023},
pages = {3:1--3:8},
publisher = {{ACM}},
year = {2023},
url = {https://doi.org/10.1145/3632409.3632839},
doi = {10.1145/3632409.3632839},
timestamp = {Mon, 01 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/RaikarS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/slip/2023,
title = {Proceedings of the {ACM} International Workshop on System-Level Interconnect
Pathfinding, {SLIP} 2023, San Francisco, CA, USA, 2 November 2023},
publisher = {{ACM}},
year = {2023},
url = {https://doi.org/10.1145/3632409},
doi = {10.1145/3632409},
timestamp = {Mon, 19 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/2023.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/AhnK22,
author = {Jaehoon Ahn and
Taewhan Kim},
editor = {Mustafa Badaroglu and
Shantanu Dutt},
title = {Neural Network Model for Detour Net Prediction},
booktitle = {Proceedings of the 24th {ACM/IEEE} Workshop on System Level Interconnect
Pathfinding, {SLIP} 2022, San Diego, California, 3 November 2022},
pages = {6:1--6:5},
publisher = {{ACM}},
year = {2022},
url = {https://doi.org/10.1145/3557988.3569710},
doi = {10.1145/3557988.3569710},
timestamp = {Mon, 19 Feb 2024 16:17:50 +0100},
biburl = {https://dblp.org/rec/conf/slip/AhnK22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/ChenSZMWPB22,
author = {Rongmei Chen and
Giuliano Sisto and
Odysseas Zografos and
Dragomir Milojevic and
Pieter Weckx and
Geert Van der Plas and
Eric Beyne},
editor = {Mustafa Badaroglu and
Shantanu Dutt},
title = {Opportunities of Chip Power Integrity and Performance Improvement
through Wafer Backside {(BS)} Connection: Invited Paper},
booktitle = {Proceedings of the 24th {ACM/IEEE} Workshop on System Level Interconnect
Pathfinding, {SLIP} 2022, San Diego, California, 3 November 2022},
pages = {3:1--3:5},
publisher = {{ACM}},
year = {2022},
url = {https://doi.org/10.1145/3557988.3569716},
doi = {10.1145/3557988.3569716},
timestamp = {Fri, 22 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/ChenSZMWPB22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/HuHZTB22,
author = {Hailiang Hu and
Jiang Hu and
Fan Zhang and
Bing Tian and
Ismail Bustany},
editor = {Mustafa Badaroglu and
Shantanu Dutt},
title = {Machine-Learning Based Delay Prediction for {FPGA} Technology Mapping},
booktitle = {Proceedings of the 24th {ACM/IEEE} Workshop on System Level Interconnect
Pathfinding, {SLIP} 2022, San Diego, California, 3 November 2022},
pages = {7:1--7:6},
publisher = {{ACM}},
year = {2022},
url = {https://doi.org/10.1145/3557988.3569713},
doi = {10.1145/3557988.3569713},
timestamp = {Mon, 19 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/HuHZTB22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/PhilippeCPGREGN22,
author = {A. Philippe and
Lorenzo Ciampolini and
A. Philippe and
M. Gerbaud and
M. Ramirez{-}Corrales and
Valentin Egloff and
Bastien Giraud and
Jean{-}Philippe No{\"{e}}l},
editor = {Mustafa Badaroglu and
Shantanu Dutt},
title = {An Automated Design Methodology for Computational {SRAM} Dedicated
to Highly Data-Centric Applications: Invited Paper},
booktitle = {Proceedings of the 24th {ACM/IEEE} Workshop on System Level Interconnect
Pathfinding, {SLIP} 2022, San Diego, California, 3 November 2022},
pages = {4:1--4:7},
publisher = {{ACM}},
year = {2022},
url = {https://doi.org/10.1145/3557988.3569715},
doi = {10.1145/3557988.3569715},
timestamp = {Mon, 19 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/PhilippeCPGREGN22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/RaikarS22,
author = {Raveena Raikar and
Dirk Stroobandt},
editor = {Mustafa Badaroglu and
Shantanu Dutt},
title = {Multi-Die Heterogeneous FPGAs: How Balanced Should Netlist Partitioning
be?},
booktitle = {Proceedings of the 24th {ACM/IEEE} Workshop on System Level Interconnect
Pathfinding, {SLIP} 2022, San Diego, California, 3 November 2022},
pages = {1:1--1:7},
publisher = {{ACM}},
year = {2022},
url = {https://doi.org/10.1145/3557988.3569711},
doi = {10.1145/3557988.3569711},
timestamp = {Mon, 19 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/RaikarS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/YuDBD22,
author = {Tianyi Yu and
Nima Karimpour Darav and
Ismail Bustany and
Mehrdad Eslami Dehkordi},
editor = {Mustafa Badaroglu and
Shantanu Dutt},
title = {A Machine Learning Approach for Accelerating SimPL-Based Global Placement
for FPGA's},
booktitle = {Proceedings of the 24th {ACM/IEEE} Workshop on System Level Interconnect
Pathfinding, {SLIP} 2022, San Diego, California, 3 November 2022},
pages = {5:1--5:7},
publisher = {{ACM}},
year = {2022},
url = {https://doi.org/10.1145/3557988.3569714},
doi = {10.1145/3557988.3569714},
timestamp = {Mon, 19 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/YuDBD22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/ZhangD22,
author = {Xiuyan Zhang and
Shantanu Dutt},
editor = {Mustafa Badaroglu and
Shantanu Dutt},
title = {Limiting Interconnect Heating in Power-Driven Physical Synthesis},
booktitle = {Proceedings of the 24th {ACM/IEEE} Workshop on System Level Interconnect
Pathfinding, {SLIP} 2022, San Diego, California, 3 November 2022},
pages = {2:1--2:7},
publisher = {{ACM}},
year = {2022},
url = {https://doi.org/10.1145/3557988.3569712},
doi = {10.1145/3557988.3569712},
timestamp = {Mon, 19 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/ZhangD22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/slip/2022,
editor = {Mustafa Badaroglu and
Shantanu Dutt},
title = {Proceedings of the 24th {ACM/IEEE} Workshop on System Level Interconnect
Pathfinding, {SLIP} 2022, San Diego, California, 3 November 2022},
publisher = {{ACM}},
year = {2022},
url = {https://doi.org/10.1145/3557988},
doi = {10.1145/3557988},
isbn = {978-1-4503-9536-6},
timestamp = {Mon, 19 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/2022.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/CaloBBBFTSP21,
author = {Giovanna Cal{\`{o}} and
Marina Barbiroli and
Gaetano Bellanca and
Davide Bertozzi and
Franco Fuschini and
Velio Tralli and
Giovanni Serafino and
Vincenzo Petruzzelli},
title = {Reconfigurable on-chip wireless interconnections through optical phased
arrays (Invited)},
booktitle = {{ACM/IEEE} International Workshop on System Level Interconnect Prediction,
{SLIP} 2021, Munich, Germany, November 4, 2021},
pages = {33--40},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/SLIP52707.2021.00014},
doi = {10.1109/SLIP52707.2021.00014},
timestamp = {Fri, 21 Jan 2022 09:18:37 +0100},
biburl = {https://dblp.org/rec/conf/slip/CaloBBBFTSP21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/Campenhout21,
author = {Joris Van Campenhout},
title = {Silicon Photonics Technology for Terabit-scale Optical {I/O} (Invited)},
booktitle = {{ACM/IEEE} International Workshop on System Level Interconnect Prediction,
{SLIP} 2021, Munich, Germany, November 4, 2021},
pages = {41},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/SLIP52707.2021.00015},
doi = {10.1109/SLIP52707.2021.00015},
timestamp = {Fri, 21 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/Campenhout21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/ChengHHL21,
author = {Chung{-}Kuan Cheng and
Chia{-}Tung Ho and
Chester Holtz and
Bill Lin},
title = {Design and System Technology Co-Optimization Sensitivity Prediction
for {VLSI} Technology Development using Machine Learning},
booktitle = {{ACM/IEEE} International Workshop on System Level Interconnect Prediction,
{SLIP} 2021, Munich, Germany, November 4, 2021},
pages = {8--15},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/SLIP52707.2021.00009},
doi = {10.1109/SLIP52707.2021.00009},
timestamp = {Mon, 01 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/ChengHHL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/ChoudharyJC21,
author = {Jitesh Choudhary and
Soumya J. and
Linga Reddy Cenkeramaddi},
title = {{RAMAN:} Reinforcement Learning Inspired Algorithm for Mapping Applications
onto Mesh Network-on-Chip},
booktitle = {{ACM/IEEE} International Workshop on System Level Interconnect Prediction,
{SLIP} 2021, Munich, Germany, November 4, 2021},
pages = {52--58},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/SLIP52707.2021.00019},
doi = {10.1109/SLIP52707.2021.00019},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/ChoudharyJC21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/JiangP21,
author = {Minmin Jiang and
Vasilis F. Pavlidis},
title = {Performance-Aware Interconnect Delay Insertion Against {EM} Side-Channel
Attacks},
booktitle = {{ACM/IEEE} International Workshop on System Level Interconnect Prediction,
{SLIP} 2021, Munich, Germany, November 4, 2021},
pages = {25--32},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/SLIP52707.2021.00013},
doi = {10.1109/SLIP52707.2021.00013},
timestamp = {Fri, 21 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/JiangP21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/Karnik21,
author = {Tanay Karnik},
title = {Recent Advances and Future Challenges in 2.5D/3D Heterogeneous Integration
(Invited)},
booktitle = {{ACM/IEEE} International Workshop on System Level Interconnect Prediction,
{SLIP} 2021, Munich, Germany, November 4, 2021},
pages = {x},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/SLIP52707.2021.00007},
doi = {10.1109/SLIP52707.2021.00007},
timestamp = {Fri, 21 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/Karnik21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/Muck21,
author = {Tiago M{\"{u}}ck},
title = {Network-on-Chips for Future 3D Stacked Dies (Invited)},
booktitle = {{ACM/IEEE} International Workshop on System Level Interconnect Prediction,
{SLIP} 2021, Munich, Germany, November 4, 2021},
pages = {59},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/SLIP52707.2021.00020},
doi = {10.1109/SLIP52707.2021.00020},
timestamp = {Fri, 21 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/Muck21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/Nagata21,
author = {Makoto Nagata},
title = {Chip Stacking and Packaging Technology Explorations for Hardware Security
(Invited)},
booktitle = {{ACM/IEEE} International Workshop on System Level Interconnect Prediction,
{SLIP} 2021, Munich, Germany, November 4, 2021},
pages = {24},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/SLIP52707.2021.00012},
doi = {10.1109/SLIP52707.2021.00012},
timestamp = {Fri, 21 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/Nagata21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/Ramalingam21,
author = {Suresh Ramalingam},
title = {Enabling Chiplet Integration Beyond 7nm (Invited)},
booktitle = {{ACM/IEEE} International Workshop on System Level Interconnect Prediction,
{SLIP} 2021, Munich, Germany, November 4, 2021},
pages = {16},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/SLIP52707.2021.00010},
doi = {10.1109/SLIP52707.2021.00010},
timestamp = {Fri, 21 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/Ramalingam21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/SharifpourSR21,
author = {Babak Sharifpour and
Mohammad Sharifpour and
Midia Reshadi},
title = {SID-Mesh: Diagonal Mesh Topology for Silicon Interposer in 2.5D NoC
with Introducing a New Routing Algorithm},
booktitle = {{ACM/IEEE} International Workshop on System Level Interconnect Prediction,
{SLIP} 2021, Munich, Germany, November 4, 2021},
pages = {44--51},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/SLIP52707.2021.00018},
doi = {10.1109/SLIP52707.2021.00018},
timestamp = {Fri, 21 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/SharifpourSR21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/SistoCCPBMM21,
author = {Giuliano Sisto and
Rongmei Chen and
Richard Chou and
Geert Van der Plas and
Eric Beyne and
Rod Metcalfe and
Dragomir Milojevic},
title = {Design And Sign-off Methodologies For Wafer-To-Wafer Bonded 3D-ICs
At Advanced Nodes (invited)},
booktitle = {{ACM/IEEE} International Workshop on System Level Interconnect Prediction,
{SLIP} 2021, Munich, Germany, November 4, 2021},
pages = {17--23},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/SLIP52707.2021.00011},
doi = {10.1109/SLIP52707.2021.00011},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/SistoCCPBMM21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/Thonnart21,
author = {Yvain Thonnart},
title = {Designing a Multi-Chiplet Manycore System using the {POPSTAR} Optical
NoC Architecture (Invited)},
booktitle = {{ACM/IEEE} International Workshop on System Level Interconnect Prediction,
{SLIP} 2021, Munich, Germany, November 4, 2021},
pages = {42},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/SLIP52707.2021.00016},
doi = {10.1109/SLIP52707.2021.00016},
timestamp = {Fri, 21 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/Thonnart21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/Vinnakota21,
author = {Bapi Vinnakota},
title = {The Open Domain-Specific Architecture: An Introduction (Invited)},
booktitle = {{ACM/IEEE} International Workshop on System Level Interconnect Prediction,
{SLIP} 2021, Munich, Germany, November 4, 2021},
pages = {43},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/SLIP52707.2021.00017},
doi = {10.1109/SLIP52707.2021.00017},
timestamp = {Fri, 21 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/Vinnakota21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/ZahedmaneshCZBC21,
author = {Houman Zahedmanesh and
Ivan Ciofi and
Odysseas Zografos and
Mustafa Badaroglu and
Kristof Croes},
title = {A Novel System-Level Physics-Based Electromigration Modelling Framework:
Application to the Power Delivery Network},
booktitle = {{ACM/IEEE} International Workshop on System Level Interconnect Prediction,
{SLIP} 2021, Munich, Germany, November 4, 2021},
pages = {1--7},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/SLIP52707.2021.00008},
doi = {10.1109/SLIP52707.2021.00008},
timestamp = {Fri, 21 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/ZahedmaneshCZBC21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/slip/2021,
title = {{ACM/IEEE} International Workshop on System Level Interconnect Prediction,
{SLIP} 2021, Munich, Germany, November 4, 2021},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/SLIP52707.2021},
doi = {10.1109/SLIP52707.2021},
isbn = {978-1-6654-0083-1},
timestamp = {Fri, 21 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/2021.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/AyoubKMO20,
author = {Raid Ayoub and
Michael Kishinevsky and
Sumit K. Mandal and
{\"{U}}mit Y. Ogras},
editor = {Andrew B. Kahng},
title = {Analytical modeling of NoCs for fast simulation and design exploration
(invited)},
booktitle = {{SLIP} '20: System-Level Interconnect - Problems and Pathfinding Workshop,
San Diego, California, November 5, 2020},
pages = {8},
publisher = {{ACM}},
year = {2020},
url = {https://doi.org/10.1145/3414622.3432993},
doi = {10.1145/3414622.3432993},
timestamp = {Mon, 08 Feb 2021 17:13:33 +0100},
biburl = {https://dblp.org/rec/conf/slip/AyoubKMO20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/Badaroglu20,
author = {Mustafa Badaroglu},
editor = {Andrew B. Kahng},
title = {Outlook of device and assembly technologies enabling high-performance
mobile computing: {IRDS} view (invited)},
booktitle = {{SLIP} '20: System-Level Interconnect - Problems and Pathfinding Workshop,
San Diego, California, November 5, 2020},
pages = {1},
publisher = {{ACM}},
year = {2020},
url = {https://doi.org/10.1145/3414622.3431912},
doi = {10.1145/3414622.3431912},
timestamp = {Mon, 08 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/Badaroglu20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/ChanKW20,
author = {Tuck{-}Boon Chan and
Andrew B. Kahng and
Mingyu Woo},
editor = {Andrew B. Kahng},
title = {Revisiting inherent noise floors for interconnect prediction},
booktitle = {{SLIP} '20: System-Level Interconnect - Problems and Pathfinding Workshop,
San Diego, California, November 5, 2020},
pages = {10},
publisher = {{ACM}},
year = {2020},
url = {https://doi.org/10.1145/3414622.3431907},
doi = {10.1145/3414622.3431907},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/ChanKW20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/DHooreBS20,
author = {Jonathan D'Hoore and
Poona Bahrebar and
Dirk Stroobandt},
editor = {Andrew B. Kahng},
title = {3D NoC emulation model on a single {FPGA}},
booktitle = {{SLIP} '20: System-Level Interconnect - Problems and Pathfinding Workshop,
San Diego, California, November 5, 2020},
pages = {11},
publisher = {{ACM}},
year = {2020},
url = {https://doi.org/10.1145/3414622.3431910},
doi = {10.1145/3414622.3431910},
timestamp = {Mon, 08 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/DHooreBS20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/FatemiKKG20,
author = {Hamed Fatemi and
Andrew B. Kahng and
Minsoo Kim and
Jos{\'{e}} Pineda de Gyvez},
editor = {Andrew B. Kahng},
title = {Optimal bounded-skew steiner trees to minimize maximum \emph{k}-active
dynamic power},
booktitle = {{SLIP} '20: System-Level Interconnect - Problems and Pathfinding Workshop,
San Diego, California, November 5, 2020},
pages = {12},
publisher = {{ACM}},
year = {2020},
url = {https://doi.org/10.1145/3414622.3431908},
doi = {10.1145/3414622.3431908},
timestamp = {Mon, 08 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/FatemiKKG20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/Groeneveld20,
author = {Patrick Groeneveld},
editor = {Andrew B. Kahng},
title = {Wafer scale interconnect and pathfinding for machine learning hardware
(invited)},
booktitle = {{SLIP} '20: System-Level Interconnect - Problems and Pathfinding Workshop,
San Diego, California, November 5, 2020},
pages = {7},
publisher = {{ACM}},
year = {2020},
url = {https://doi.org/10.1145/3414622.3432992},
doi = {10.1145/3414622.3432992},
timestamp = {Mon, 08 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/Groeneveld20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/JabbariF20,
author = {Tahereh Jabbari and
Eby G. Friedman},
editor = {Andrew B. Kahng},
title = {Global interconnects in {VLSI} complexity single flux quantum systems},
booktitle = {{SLIP} '20: System-Level Interconnect - Problems and Pathfinding Workshop,
San Diego, California, November 5, 2020},
pages = {4},
publisher = {{ACM}},
year = {2020},
url = {https://doi.org/10.1145/3414622.3431911},
doi = {10.1145/3414622.3431911},
timestamp = {Mon, 08 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/JabbariF20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/Jain20,
author = {Abhishek Kumar Jain},
editor = {Andrew B. Kahng},
title = {Role of on-chip networks in building domain-specific architectures
(DSAs) for sparse computations (invited)},
booktitle = {{SLIP} '20: System-Level Interconnect - Problems and Pathfinding Workshop,
San Diego, California, November 5, 2020},
pages = {9},
publisher = {{ACM}},
year = {2020},
url = {https://doi.org/10.1145/3414622.3432994},
doi = {10.1145/3414622.3432994},
timestamp = {Mon, 08 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/Jain20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/KauthSBSG20,
author = {Kevin Kauth and
Tim Stadtmann and
Ruben Brandhofer and
Vida Sobhani and
Tobias Gemmeke},
editor = {Andrew B. Kahng},
title = {Communication architecture enabling 100x accelerated simulation of
biological neural networks},
booktitle = {{SLIP} '20: System-Level Interconnect - Problems and Pathfinding Workshop,
San Diego, California, November 5, 2020},
pages = {2},
publisher = {{ACM}},
year = {2020},
url = {https://doi.org/10.1145/3414622.3431909},
doi = {10.1145/3414622.3431909},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/KauthSBSG20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/Orcutt20,
author = {Jason Orcutt},
editor = {Andrew B. Kahng},
title = {Extending quantum systems with optical interconnects (invited)},
booktitle = {{SLIP} '20: System-Level Interconnect - Problems and Pathfinding Workshop,
San Diego, California, November 5, 2020},
pages = {6},
publisher = {{ACM}},
year = {2020},
url = {https://doi.org/10.1145/3414622.3431914},
doi = {10.1145/3414622.3431914},
timestamp = {Mon, 08 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/Orcutt20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/PalG20,
author = {Saptadeep Pal and
Puneet Gupta},
editor = {Andrew B. Kahng},
title = {Pathfinding for 2.5D interconnect technologies},
booktitle = {{SLIP} '20: System-Level Interconnect - Problems and Pathfinding Workshop,
San Diego, California, November 5, 2020},
pages = {3},
publisher = {{ACM}},
year = {2020},
url = {https://doi.org/10.1145/3414622.3431906},
doi = {10.1145/3414622.3431906},
timestamp = {Thu, 28 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/PalG20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/Sanders20,
author = {Barry C. Sanders},
editor = {Andrew B. Kahng},
title = {Building a quantum computer (invited)},
booktitle = {{SLIP} '20: System-Level Interconnect - Problems and Pathfinding Workshop,
San Diego, California, November 5, 2020},
pages = {5},
publisher = {{ACM}},
year = {2020},
url = {https://doi.org/10.1145/3414622.3431913},
doi = {10.1145/3414622.3431913},
timestamp = {Mon, 08 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/Sanders20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/slip/2020,
editor = {Andrew B. Kahng},
title = {{SLIP} '20: System-Level Interconnect - Problems and Pathfinding Workshop,
San Diego, California, November 5, 2020},
publisher = {{ACM}},
year = {2020},
url = {https://doi.org/10.1145/3414622},
doi = {10.1145/3414622},
isbn = {978-1-4503-8106-2},
timestamp = {Mon, 08 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/2020.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/KenarangiP19,
author = {Farid Kenarangi and
Inna Partin{-}Vaisband},
title = {Security Network On-Chip for Mitigating Side-Channel Attacks},
booktitle = {21st {ACM/IEEE} International Workshop on System Level Interconnect
Prediction, {SLIP} 2019, Las Vegas, NV, USA, June 1-2, 2019},
pages = {1--6},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/SLIP.2019.8771328},
doi = {10.1109/SLIP.2019.8771328},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/slip/KenarangiP19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/PuiWMY19,
author = {Chak{-}Wa Pui and
Gang Wu and
Freddy Y. C. Mang and
Evangeline F. Y. Young},
title = {An Analytical Approach for Time-Division Multiplexing Optimization
in Multi-FPGA based Systems},
booktitle = {21st {ACM/IEEE} International Workshop on System Level Interconnect
Prediction, {SLIP} 2019, Las Vegas, NV, USA, June 1-2, 2019},
pages = {1--8},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/SLIP.2019.8771330},
doi = {10.1109/SLIP.2019.8771330},
timestamp = {Tue, 30 Jul 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/PuiWMY19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/StowA019,
author = {Dylan C. Stow and
Itir Akgun and
Yuan Xie},
title = {Investigation of Cost-Optimal Network-on-Chip for Passive and Active
Interposer Systems},
booktitle = {21st {ACM/IEEE} International Workshop on System Level Interconnect
Prediction, {SLIP} 2019, Las Vegas, NV, USA, June 1-2, 2019},
pages = {1--8},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/SLIP.2019.8771333},
doi = {10.1109/SLIP.2019.8771333},
timestamp = {Fri, 15 Nov 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/StowA019.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/VaisbandI19,
author = {Boris Vaisband and
Subramanian S. Iyer},
title = {Communication Considerations for Silicon Interconnect Fabric},
booktitle = {21st {ACM/IEEE} International Workshop on System Level Interconnect
Prediction, {SLIP} 2019, Las Vegas, NV, USA, June 1-2, 2019},
pages = {1--6},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/SLIP.2019.8771326},
doi = {10.1109/SLIP.2019.8771326},
timestamp = {Tue, 30 Jul 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/VaisbandI19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/VosoughiWK19,
author = {M. Ali Vosoughi and
Longfei Wang and
Sel{\c{c}}uk K{\"{o}}se},
title = {Bus-Invert Coding as a Low-Power Countermeasure Against Correlation
Power Analysis Attack},
booktitle = {21st {ACM/IEEE} International Workshop on System Level Interconnect
Prediction, {SLIP} 2019, Las Vegas, NV, USA, June 1-2, 2019},
pages = {1--5},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/SLIP.2019.8771332},
doi = {10.1109/SLIP.2019.8771332},
timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/VosoughiWK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/WangKTK19,
author = {Longfei Wang and
Ragh Kuttappa and
Baris Taskin and
Sel{\c{c}}uk K{\"{o}}se},
title = {Distributed Digital Low-Dropout Regulators with Phase Interleaving
for On-Chip Voltage Noise Mitigation},
booktitle = {21st {ACM/IEEE} International Workshop on System Level Interconnect
Prediction, {SLIP} 2019, Las Vegas, NV, USA, June 1-2, 2019},
pages = {1--5},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/SLIP.2019.8771327},
doi = {10.1109/SLIP.2019.8771327},
timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/WangKTK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/WenAY19,
author = {Yiming Wen and
Sayyed Farid Ahamed and
Weize Yu},
title = {A Novel {PUF} Architecture Against Non-Invasive Attacks},
booktitle = {21st {ACM/IEEE} International Workshop on System Level Interconnect
Prediction, {SLIP} 2019, Las Vegas, NV, USA, June 1-2, 2019},
pages = {1--5},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/SLIP.2019.8771329},
doi = {10.1109/SLIP.2019.8771329},
timestamp = {Tue, 30 Jul 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/WenAY19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/XuA19,
author = {Zheng Xu and
Jacob Abraham},
title = {FSNoC: Safe Network-on-Chip Design with Packet Level Lock Stepping},
booktitle = {21st {ACM/IEEE} International Workshop on System Level Interconnect
Prediction, {SLIP} 2019, Las Vegas, NV, USA, June 1-2, 2019},
pages = {1--6},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/SLIP.2019.8771331},
doi = {10.1109/SLIP.2019.8771331},
timestamp = {Tue, 30 Jul 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/XuA19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/slip/2019,
title = {21st {ACM/IEEE} International Workshop on System Level Interconnect
Prediction, {SLIP} 2019, Las Vegas, NV, USA, June 1-2, 2019},
publisher = {{IEEE}},
year = {2019},
url = {https://ieeexplore.ieee.org/xpl/conhome/8766240/proceeding},
isbn = {978-1-7281-2818-4},
timestamp = {Wed, 16 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/2019.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/DofeY18,
author = {Jaya Dofe and
Qiaoyan Yu},
editor = {Shiyan Hu},
title = {Exploiting {PDN} noise to thwart correlation power analysis attacks
in 3D ICs},
booktitle = {Proceedings of the 20th System Level Interconnect Prediction Workshop,
SLIP@DAC 2018, San Francisco, CA, USA, June 23, 2018},
pages = {6:1--6:6},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3225209.3225212},
doi = {10.1145/3225209.3225212},
timestamp = {Wed, 21 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/DofeY18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/GaoSZ18,
author = {Di Gao and
Tianhao Shen and
Cheng Zhuo},
editor = {Shiyan Hu},
title = {A design framework for processing-in-memory accelerator},
booktitle = {Proceedings of the 20th System Level Interconnect Prediction Workshop,
SLIP@DAC 2018, San Francisco, CA, USA, June 23, 2018},
pages = {3:1--3:6},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3225209.3225213},
doi = {10.1145/3225209.3225213},
timestamp = {Wed, 21 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/GaoSZ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/HanKMZ18,
author = {Kwangsoo Han and
Andrew B. Kahng and
Christopher Moyes and
Alex Zelikovsky},
editor = {Shiyan Hu},
title = {A study of optimal cost-skew tradeoff and remaining suboptimality
in interconnect tree constructions},
booktitle = {Proceedings of the 20th System Level Interconnect Prediction Workshop,
SLIP@DAC 2018, San Francisco, CA, USA, June 23, 2018},
pages = {2:1--2:8},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3225209.3225215},
doi = {10.1145/3225209.3225215},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/HanKMZ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/HsuYWC18,
author = {Po{-}Ya Hsu and
Chun{-}Han Yao and
Yuwei Wang and
Chung{-}Kuan Cheng},
editor = {Shiyan Hu},
title = {Adaptive sensitivity analysis with nonlinear power load modeling},
booktitle = {Proceedings of the 20th System Level Interconnect Prediction Workshop,
SLIP@DAC 2018, San Francisco, CA, USA, June 23, 2018},
pages = {5:1--5:6},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3225209.3225211},
doi = {10.1145/3225209.3225211},
timestamp = {Wed, 21 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/HsuYWC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/KangPHC18,
author = {Ilgweon Kang and
Dongwon Park and
Changho Han and
Chung{-}Kuan Cheng},
editor = {Shiyan Hu},
title = {Fast and precise routability analysis with conditional design rules},
booktitle = {Proceedings of the 20th System Level Interconnect Prediction Workshop,
SLIP@DAC 2018, San Francisco, CA, USA, June 23, 2018},
pages = {4:1--4:8},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3225209.3225210},
doi = {10.1145/3225209.3225210},
timestamp = {Thu, 01 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/KangPHC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/LiuKWC18,
author = {Xinheng Liu and
Dae Hee Kim and
Chang Wu and
Deming Chen},
editor = {Shiyan Hu},
title = {Resource and data optimization for hardware implementation of deep
neural networks targeting FPGA-based edge devices},
booktitle = {Proceedings of the 20th System Level Interconnect Prediction Workshop,
SLIP@DAC 2018, San Francisco, CA, USA, June 23, 2018},
pages = {1:1--1:8},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3225209.3225214},
doi = {10.1145/3225209.3225214},
timestamp = {Wed, 21 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/LiuKWC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/dac/2018slip,
editor = {Shiyan Hu},
title = {Proceedings of the 20th System Level Interconnect Prediction Workshop,
SLIP@DAC 2018, San Francisco, CA, USA, June 23, 2018},
publisher = {{ACM}},
year = {2018},
url = {http://dl.acm.org/citation.cfm?id=3225209},
timestamp = {Wed, 15 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/2018slip.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/ChittamuruTP17,
author = {Sai Vineel Reddy Chittamuru and
Ishan G. Thakkar and
Sudeep Pasricha},
title = {Analyzing voltage bias and temperature induced aging effects in photonic
interconnects for manycore computing},
booktitle = {{ACM/IEEE} 2017 International Workshop on System Level Interconnect
Prediction, {SLIP} 2017, Austin, TX, USA, June 17, 2017},
pages = {1--8},
publisher = {{IEEE} Computer Society},
year = {2017},
url = {https://doi.org/10.1109/SLIP.2017.7974906},
doi = {10.1109/SLIP.2017.7974906},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/ChittamuruTP17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/Chow0TY17,
author = {Wing{-}Kai Chow and
Jian Kuang and
Peishan Tu and
Evangeline F. Y. Young},
title = {Fence-aware detailed-routability driven placement},
booktitle = {{ACM/IEEE} 2017 International Workshop on System Level Interconnect
Prediction, {SLIP} 2017, Austin, TX, USA, June 17, 2017},
pages = {1--7},
publisher = {{IEEE} Computer Society},
year = {2017},
url = {https://doi.org/10.1109/SLIP.2017.7974905},
doi = {10.1109/SLIP.2017.7974905},
timestamp = {Tue, 18 Jul 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/Chow0TY17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/DaulagalaS17,
author = {Isuru Daulagala and
Ioannis Savidis},
title = {Clock tree synthesis for heterogeneous 3-D integrated circuits},
booktitle = {{ACM/IEEE} 2017 International Workshop on System Level Interconnect
Prediction, {SLIP} 2017, Austin, TX, USA, June 17, 2017},
pages = {1--6},
publisher = {{IEEE} Computer Society},
year = {2017},
url = {https://doi.org/10.1109/SLIP.2017.7974911},
doi = {10.1109/SLIP.2017.7974911},
timestamp = {Tue, 18 Jul 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/DaulagalaS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/FilippiniT17,
author = {Leo Filippini and
Baris Taskin},
title = {A charge recovery logic system bus},
booktitle = {{ACM/IEEE} 2017 International Workshop on System Level Interconnect
Prediction, {SLIP} 2017, Austin, TX, USA, June 17, 2017},
pages = {1--4},
publisher = {{IEEE} Computer Society},
year = {2017},
url = {https://doi.org/10.1109/SLIP.2017.7974909},
doi = {10.1109/SLIP.2017.7974909},
timestamp = {Fri, 30 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/FilippiniT17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/HuangXYC17,
author = {Jinglei Huang and
Xiaodong Xu and
Lan Yao and
Song Chen},
title = {Reconfigurable topology synthesis for application-specific noc on
partially dynamically reconfigurable FPGAs},
booktitle = {{ACM/IEEE} 2017 International Workshop on System Level Interconnect
Prediction, {SLIP} 2017, Austin, TX, USA, June 17, 2017},
pages = {1--8},
publisher = {{IEEE} Computer Society},
year = {2017},
url = {https://doi.org/10.1109/SLIP.2017.7974907},
doi = {10.1109/SLIP.2017.7974907},
timestamp = {Sat, 08 Sep 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/HuangXYC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/LernerLT17,
author = {Scott Lerner and
Eric Leggett and
Baris Taskin},
title = {Slew-down: analysis of slew relaxation for low-impact clock buffers},
booktitle = {{ACM/IEEE} 2017 International Workshop on System Level Interconnect
Prediction, {SLIP} 2017, Austin, TX, USA, June 17, 2017},
pages = {1--4},
publisher = {{IEEE} Computer Society},
year = {2017},
url = {https://doi.org/10.1109/SLIP.2017.7974910},
doi = {10.1109/SLIP.2017.7974910},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/LernerLT17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/Schlichtmann17,
author = {Ulf Schlichtmann},
title = {Frontiers of timing},
booktitle = {{ACM/IEEE} 2017 International Workshop on System Level Interconnect
Prediction, {SLIP} 2017, Austin, TX, USA, June 17, 2017},
pages = {1--4},
publisher = {{IEEE} Computer Society},
year = {2017},
url = {https://doi.org/10.1109/SLIP.2017.7974912},
doi = {10.1109/SLIP.2017.7974912},
timestamp = {Mon, 16 Sep 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/Schlichtmann17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/TuCY17,
author = {Peishan Tu and
Wing{-}Kai Chow and
Evangeline F. Y. Young},
title = {Timing driven routing tree construction},
booktitle = {{ACM/IEEE} 2017 International Workshop on System Level Interconnect
Prediction, {SLIP} 2017, Austin, TX, USA, June 17, 2017},
pages = {1--8},
publisher = {{IEEE} Computer Society},
year = {2017},
url = {https://doi.org/10.1109/SLIP.2017.7974908},
doi = {10.1109/SLIP.2017.7974908},
timestamp = {Tue, 18 Jul 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/TuCY17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/slip/2017,
title = {{ACM/IEEE} 2017 International Workshop on System Level Interconnect
Prediction, {SLIP} 2017, Austin, TX, USA, June 17, 2017},
publisher = {{IEEE} Computer Society},
year = {2017},
url = {https://ieeexplore.ieee.org/xpl/conhome/7974634/proceeding},
isbn = {978-1-5386-1536-2},
timestamp = {Wed, 16 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/2017.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/AhmedMC16,
author = {Mohammad A. Ahmed and
Sucheta Mohapatra and
Malgorzata Chrzanowska{-}Jeske},
editor = {Baris Taskin and
Tsung{-}Yi Ho},
title = {Buffered Interconnects in 3D {IC} Layout Design},
booktitle = {Proceedings of the 18th System Level Interconnect Prediction Workshop,
{SLIP} 2016, Austin, TX, USA, June 4, 2016},
pages = {4:1--4:8},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2947357.2947366},
doi = {10.1145/2947357.2947366},
timestamp = {Wed, 11 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/AhmedMC16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/BazylevychPB16,
author = {Roman P. Bazylevych and
Marek Palasinski and
Lubov Bazylevych},
editor = {Baris Taskin and
Tsung{-}Yi Ho},
title = {Topologically-Geometric Routing},
booktitle = {Proceedings of the 18th System Level Interconnect Prediction Workshop,
{SLIP} 2016, Austin, TX, USA, June 4, 2016},
pages = {5:1--5:6},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2947357.2947367},
doi = {10.1145/2947357.2947367},
timestamp = {Tue, 31 May 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/BazylevychPB16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/ChanKL16,
author = {Wei{-}Ting Jonas Chan and
Andrew B. Kahng and
Jiajia Li},
editor = {Baris Taskin and
Tsung{-}Yi Ho},
title = {Revisiting 3DIC Benefit with Multiple Tiers},
booktitle = {Proceedings of the 18th System Level Interconnect Prediction Workshop,
{SLIP} 2016, Austin, TX, USA, June 4, 2016},
pages = {6:1--6:8},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2947357.2947363},
doi = {10.1145/2947357.2947363},
timestamp = {Wed, 11 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/ChanKL16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/EkenBZYWLC16,
author = {Enes Eken and
Ismail Bayram and
Yaojun Zhang and
Bonan Yan and
Wenqing Wu and
Hai (Helen) Li and
Yiran Chen},
editor = {Baris Taskin and
Tsung{-}Yi Ho},
title = {Spin-Hall Assisted {STT-RAM} Design and Discussion},
booktitle = {Proceedings of the 18th System Level Interconnect Prediction Workshop,
{SLIP} 2016, Austin, TX, USA, June 4, 2016},
pages = {7:1--7:4},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2947357.2947360},
doi = {10.1145/2947357.2947360},
timestamp = {Mon, 04 Jul 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/EkenBZYWLC16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/HsuLH16,
author = {Chih{-}Cheng Hsu and
Mark Po{-}Hung Lin and
Masanori Hashimoto},
editor = {Baris Taskin and
Tsung{-}Yi Ho},
title = {Latch Clustering for Minimizing Detection-to-Boosting Latency Toward
Low-Power Resilient Circuits},
booktitle = {Proceedings of the 18th System Level Interconnect Prediction Workshop,
{SLIP} 2016, Austin, TX, USA, June 4, 2016},
pages = {2:1--2:6},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2947357.2947364},
doi = {10.1145/2947357.2947364},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/HsuLH16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/MansoorSG16,
author = {Naseef Mansoor and
Md Shahriar Shamim and
Amlan Ganguly},
editor = {Baris Taskin and
Tsung{-}Yi Ho},
title = {A Demand-Aware Predictive Dynamic Bandwidth Allocation Mechanism for
Wireless Network-on-Chip},
booktitle = {Proceedings of the 18th System Level Interconnect Prediction Workshop,
{SLIP} 2016, Austin, TX, USA, June 4, 2016},
pages = {8:1--8:8},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2947357.2947361},
doi = {10.1145/2947357.2947361},
timestamp = {Wed, 11 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/MansoorSG16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/SegalDMB16,
author = {Carrie Segal and
Aditya Dalakoti and
Merritt Miller and
Forrest Brewer},
editor = {Baris Taskin and
Tsung{-}Yi Ho},
title = {Connectivity Effects on Energy and Area for Neuromorphic System with
High Speed Asynchronous Pulse Mode Links},
booktitle = {Proceedings of the 18th System Level Interconnect Prediction Workshop,
{SLIP} 2016, Austin, TX, USA, June 4, 2016},
pages = {3:1--3:7},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2947357.2947365},
doi = {10.1145/2947357.2947365},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/SegalDMB16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/ThakkarCP16,
author = {Ishan G. Thakkar and
Sai Vineel Reddy Chittamuru and
Sudeep Pasricha},
editor = {Baris Taskin and
Tsung{-}Yi Ho},
title = {A Comparative Analysis of Front-End and Back-End Compatible Silicon
Photonic On-Chip Interconnects},
booktitle = {Proceedings of the 18th System Level Interconnect Prediction Workshop,
{SLIP} 2016, Austin, TX, USA, June 4, 2016},
pages = {1:1--1:8},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2947357.2947362},
doi = {10.1145/2947357.2947362},
timestamp = {Wed, 11 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/ThakkarCP16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/slip/2016,
editor = {Baris Taskin and
Tsung{-}Yi Ho},
title = {Proceedings of the 18th System Level Interconnect Prediction Workshop,
{SLIP} 2016, Austin, TX, USA, June 4, 2016},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2947357},
doi = {10.1145/2947357},
isbn = {978-1-4503-4430-2},
timestamp = {Wed, 16 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/2016.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/BangHKS15,
author = {Samyoung Bang and
Kwangsoo Han and
Andrew B. Kahng and
Vaishnav Srinivas},
title = {Clock clustering and {IO} optimization for 3D integration},
booktitle = {2015 {ACM/IEEE} International Workshop on System Level Interconnect
Prediction, {SLIP} 2015, San Francisco, CA, USA, June 6, 2015},
pages = {1--8},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/SLIP.2015.7171709},
doi = {10.1109/SLIP.2015.7171709},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/BangHKS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/DWHY15,
author = {Sai Manoj P. D. and
Kanwen Wang and
Hantao Huang and
Hao Yu},
title = {Smart I/Os: a data-pattern aware 2.5D interconnect with space-time
multiplexing},
booktitle = {2015 {ACM/IEEE} International Workshop on System Level Interconnect
Prediction, {SLIP} 2015, San Francisco, CA, USA, June 6, 2015},
pages = {1--6},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/SLIP.2015.7171707},
doi = {10.1109/SLIP.2015.7171707},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/DWHY15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/EscalanteKKOS15,
author = {Marco Escalante and
Andrew B. Kahng and
Michael Kishinevsky and
{\"{U}}mit Y. Ogras and
Kambiz Samadi},
title = {Multi-product floorplan and uncore design framework for chip multiprocessors},
booktitle = {2015 {ACM/IEEE} International Workshop on System Level Interconnect
Prediction, {SLIP} 2015, San Francisco, CA, USA, June 6, 2015},
pages = {1--7},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/SLIP.2015.7171713},
doi = {10.1109/SLIP.2015.7171713},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/EscalanteKKOS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/HuangW15,
author = {Tsung{-}Wei Huang and
Martin D. F. Wong},
title = {On fast timing closure: speeding up incremental path-based timing
analysis with mapreduce},
booktitle = {2015 {ACM/IEEE} International Workshop on System Level Interconnect
Prediction, {SLIP} 2015, San Francisco, CA, USA, June 6, 2015},
pages = {1--6},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/SLIP.2015.7171710},
doi = {10.1109/SLIP.2015.7171710},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/HuangW15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/KahngLN15,
author = {Andrew B. Kahng and
Mulong Luo and
Siddhartha Nath},
title = {{SI} for free: machine learning of interconnect coupling delay and
transition effects},
booktitle = {2015 {ACM/IEEE} International Workshop on System Level Interconnect
Prediction, {SLIP} 2015, San Francisco, CA, USA, June 6, 2015},
pages = {1--8},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/SLIP.2015.7171706},
doi = {10.1109/SLIP.2015.7171706},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/KahngLN15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/WuCFFBC15,
author = {Rui Wu and
Chin{-}Hui Chen and
Jean{-}Marc Fedeli and
Maryse Fournier and
Raymond G. Beausoleil and
Kwang{-}Ting Cheng},
title = {Compact modeling and system implications of microring modulators in
nanophotonic interconnects},
booktitle = {2015 {ACM/IEEE} International Workshop on System Level Interconnect
Prediction, {SLIP} 2015, San Francisco, CA, USA, June 6, 2015},
pages = {1--6},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/SLIP.2015.7171708},
doi = {10.1109/SLIP.2015.7171708},
timestamp = {Mon, 04 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/WuCFFBC15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/XuBCSLJ15,
author = {Haifeng Xu and
Melissa M. Bilec and
William O. Collinge and
Laura A. Schaefer and
Amy E. Landis and
Alex K. Jones},
title = {Lynx: a self-organizing wireless sensor network with commodity palmtop
computers},
booktitle = {2015 {ACM/IEEE} International Workshop on System Level Interconnect
Prediction, {SLIP} 2015, San Francisco, CA, USA, June 6, 2015},
pages = {1--7},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/SLIP.2015.7171712},
doi = {10.1109/SLIP.2015.7171712},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/XuBCSLJ15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/ZhangLCC15,
author = {Xiang Zhang and
Yang Liu and
Ryan Coutts and
Chung{-}Kuan Cheng},
title = {Power line communication for hybrid power/signal pin {SOC} design},
booktitle = {2015 {ACM/IEEE} International Workshop on System Level Interconnect
Prediction, {SLIP} 2015, San Francisco, CA, USA, June 6, 2015},
pages = {1--8},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/SLIP.2015.7171711},
doi = {10.1109/SLIP.2015.7171711},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/ZhangLCC15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/slip/2015,
title = {2015 {ACM/IEEE} International Workshop on System Level Interconnect
Prediction, {SLIP} 2015, San Francisco, CA, USA, June 6, 2015},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://ieeexplore.ieee.org/xpl/conhome/7160953/proceeding},
isbn = {978-1-4673-8189-5},
timestamp = {Wed, 16 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/2015.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/ChanKN14,
author = {Wei{-}Ting Jonas Chan and
Andrew B. Kahng and
Siddhartha Nath},
title = {Methodology for electromigration signoff in the presence of adaptive
voltage scaling},
booktitle = {{ACM/IEEE} International Workshop on System Level Interconnect Prediction,
{SLIP} 2014, San Francisco, CA, USA, June 1, 2014},
pages = {6:1--6:7},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1145/2633948.2633950},
doi = {10.1145/2633948.2633950},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/slip/ChanKN14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/HuangWW14,
author = {Tsung{-}Wei Huang and
Pei{-}Ci Wu and
Martin D. F. Wong},
title = {UI-route: An ultra-fast incremental maze routing algorithm},
booktitle = {{ACM/IEEE} International Workshop on System Level Interconnect Prediction,
{SLIP} 2014, San Francisco, CA, USA, June 1, 2014},
pages = {4:1--4:8},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1145/2633948.2633952},
doi = {10.1145/2633948.2633952},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/HuangWW14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/KemmererT14,
author = {Julian Kemmerer and
Baris Taskin},
title = {Range-based dynamic routing of hierarchical on chip network traffic},
booktitle = {{ACM/IEEE} International Workshop on System Level Interconnect Prediction,
{SLIP} 2014, San Francisco, CA, USA, June 1, 2014},
pages = {5:1--5:9},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://ieeexplore.ieee.org/document/6886040/},
timestamp = {Wed, 11 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/KemmererT14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/VaisbandF14,
author = {Inna Vaisband and
Eby G. Friedman},
title = {Power network-on-chip for scalable power delivery},
booktitle = {{ACM/IEEE} International Workshop on System Level Interconnect Prediction,
{SLIP} 2014, San Francisco, CA, USA, June 1, 2014},
pages = {1:1--1:5},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1145/2633948.2633949},
doi = {10.1145/2633948.2633949},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/VaisbandF14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/ZhangLLC14,
author = {Xiang Zhang and
Jingwei Lu and
Yang Liu and
Chung{-}Kuan Cheng},
title = {Worst-case noise area prediciton of on-chip power distribution network},
booktitle = {{ACM/IEEE} International Workshop on System Level Interconnect Prediction,
{SLIP} 2014, San Francisco, CA, USA, June 1, 2014},
pages = {2:1--2:8},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1145/2633948.2633951},
doi = {10.1145/2633948.2633951},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/ZhangLLC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/ZhouRPKQLAS14,
author = {Nancy Y. Zhou and
Phillip J. Restle and
Joseph N. Palumbo and
Joseph N. Kozhaya and
Haifeng Qian and
Zhuo Li and
Charles J. Alpert and
Cliff C. N. Sze},
title = {Pacman: driving nonuniform clock grid loads for low-skew robust clock
network},
booktitle = {{ACM/IEEE} International Workshop on System Level Interconnect Prediction,
{SLIP} 2014, San Francisco, CA, USA, June 1, 2014},
pages = {3:1--3:5},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1145/2633948.2633953},
doi = {10.1145/2633948.2633953},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/ZhouRPKQLAS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/Zou014,
author = {Qiaosha Zou and
Yuan Xie},
title = {Compact models and model standard for 2.5D and 3D integration},
booktitle = {{ACM/IEEE} International Workshop on System Level Interconnect Prediction,
{SLIP} 2014, San Francisco, CA, USA, June 1, 2014},
pages = {7:1--7:7},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1145/2633948.2633955},
doi = {10.1145/2633948.2633955},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/Zou014.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/slip/2014,
title = {{ACM/IEEE} International Workshop on System Level Interconnect Prediction,
{SLIP} 2014, San Francisco, CA, USA, June 1, 2014},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://ieeexplore.ieee.org/xpl/conhome/6872646/proceeding},
isbn = {978-1-4503-3053-4},
timestamp = {Wed, 16 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/2014.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/BrowningLGP13,
author = {Mark Browning and
Cheng Li and
Paul V. Gratz and
Samuel Palermo},
title = {LumiNOC: {A} low-latency, high-bandwidth per Watt, photonic Network-on-Chip},
booktitle = {{ACM/IEEE} International Workshop on System Level Interconnect Prediction,
{SLIP} 2013, Austin, TX, USA, June 2, 2013},
pages = {1--4},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://doi.org/10.1109/SLIP.2013.6681679},
doi = {10.1109/SLIP.2013.6681679},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/BrowningLGP13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/ChanKL13,
author = {Tuck{-}Boon Chan and
Andrew B. Kahng and
Jiajia Li},
title = {Toward quantifying the {IC} design value of interconnect technology
improvements},
booktitle = {{ACM/IEEE} International Workshop on System Level Interconnect Prediction,
{SLIP} 2013, Austin, TX, USA, June 2, 2013},
pages = {1--6},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://doi.org/10.1109/SLIP.2013.6681680},
doi = {10.1109/SLIP.2013.6681680},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/ChanKL13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/Chen13,
author = {Deming Chen},
title = {Optimizations in {GPU:} Smart compilers and core-level reconfiguration},
booktitle = {{ACM/IEEE} International Workshop on System Level Interconnect Prediction,
{SLIP} 2013, Austin, TX, USA, June 2, 2013},
pages = {1},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://doi.org/10.1109/SLIP.2013.6681686},
doi = {10.1109/SLIP.2013.6681686},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/Chen13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/CondratKB13,
author = {Christopher Condrat and
Priyank Kalla and
Steve Blair},
title = {Channel routing for integrated optics},
booktitle = {{ACM/IEEE} International Workshop on System Level Interconnect Prediction,
{SLIP} 2013, Austin, TX, USA, June 2, 2013},
pages = {1--8},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://doi.org/10.1109/SLIP.2013.6681678},
doi = {10.1109/SLIP.2013.6681678},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/CondratKB13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/Gill13,
author = {Doug Gill},
title = {{IBM} {CMOS} compatible photonics and traveling wave electro-optic
modulator design},
booktitle = {{ACM/IEEE} International Workshop on System Level Interconnect Prediction,
{SLIP} 2013, Austin, TX, USA, June 2, 2013},
pages = {1},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://doi.org/10.1109/SLIP.2013.6681677},
doi = {10.1109/SLIP.2013.6681677},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/Gill13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/KahngKLNW13,
author = {Andrew B. Kahng and
Seokhyeong Kang and
Hyein Lee and
Siddhartha Nath and
Jyoti Wadhwani},
title = {Learning-based approximation of interconnect delay and slew in signoff
timing tools},
booktitle = {{ACM/IEEE} International Workshop on System Level Interconnect Prediction,
{SLIP} 2013, Austin, TX, USA, June 2, 2013},
pages = {1--8},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://doi.org/10.1109/SLIP.2013.6681682},
doi = {10.1109/SLIP.2013.6681682},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/KahngKLNW13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/KahngLN13,
author = {Andrew B. Kahng and
Bill Lin and
Siddhartha Nath},
title = {High-dimensional metamodeling for prediction of clock tree synthesis
outcomes},
booktitle = {{ACM/IEEE} International Workshop on System Level Interconnect Prediction,
{SLIP} 2013, Austin, TX, USA, June 2, 2013},
pages = {1--7},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://doi.org/10.1109/SLIP.2013.6681685},
doi = {10.1109/SLIP.2013.6681685},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/KahngLN13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/MorrisKL13,
author = {Randy Morris and
Avinash Karanth Kodi and
Ahmed Louri},
title = {Evaluating the scalability and performance of 3D stacked reconfigurable
nanophotonic interconnects},
booktitle = {{ACM/IEEE} International Workshop on System Level Interconnect Prediction,
{SLIP} 2013, Austin, TX, USA, June 2, 2013},
pages = {1},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://doi.org/10.1109/SLIP.2013.6681676},
doi = {10.1109/SLIP.2013.6681676},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/MorrisKL13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/RakhejaKN13,
author = {Shaloo Rakheja and
Vachan Kumar and
Azad Naeemi},
title = {Performance modeling for interconnects for conventional and emerging
switches},
booktitle = {{ACM/IEEE} International Workshop on System Level Interconnect Prediction,
{SLIP} 2013, Austin, TX, USA, June 2, 2013},
pages = {1--9},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://doi.org/10.1109/SLIP.2013.6681683},
doi = {10.1109/SLIP.2013.6681683},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/RakhejaKN13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/Taskin13,
author = {Baris Taskin},
title = {Wireless on Networks-on-Chip},
booktitle = {{ACM/IEEE} International Workshop on System Level Interconnect Prediction,
{SLIP} 2013, Austin, TX, USA, June 2, 2013},
pages = {1--2},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://doi.org/10.1109/SLIP.2013.6681675},
doi = {10.1109/SLIP.2013.6681675},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/Taskin13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/Topaloglu13,
author = {Rasit Onur Topaloglu},
title = {Chip-scale physical interconnect models (Tutorial)},
booktitle = {{ACM/IEEE} International Workshop on System Level Interconnect Prediction,
{SLIP} 2013, Austin, TX, USA, June 2, 2013},
pages = {1--3},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://doi.org/10.1109/SLIP.2013.6681684},
doi = {10.1109/SLIP.2013.6681684},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/Topaloglu13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/ZhangLC13,
author = {Xiang Zhang and
Yang Liu and
Chung{-}Kuan Cheng},
title = {Worst-case noise prediction using power network impedance profile},
booktitle = {{ACM/IEEE} International Workshop on System Level Interconnect Prediction,
{SLIP} 2013, Austin, TX, USA, June 2, 2013},
pages = {1--8},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://doi.org/10.1109/SLIP.2013.6681681},
doi = {10.1109/SLIP.2013.6681681},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/ZhangLC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/slip/2013,
title = {{ACM/IEEE} International Workshop on System Level Interconnect Prediction,
{SLIP} 2013, Austin, TX, USA, June 2, 2013},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://ieeexplore.ieee.org/xpl/conhome/6675895/proceeding},
isbn = {978-1-4673-6173-6},
timestamp = {Wed, 16 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/2013.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/Ben-ItzhakCK12,
author = {Yaniv Ben{-}Itzhak and
Israel Cidon and
Avinoam Kolodny},
title = {Optimizing heterogeneous NoC design},
booktitle = {International Workshop on System Level Interconnect Prediction, {SLIP}
'12, San Francisco, CA, USA, June 3, 2012},
pages = {32--39},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2347655.2347670},
doi = {10.1145/2347655.2347670},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/Ben-ItzhakCK12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/ChenLW12,
author = {Xiangyu Chen and
Jiale Liang and
H.{-}S. Philip Wong},
title = {Interconnect scaling into the sub-10nm regime},
booktitle = {International Workshop on System Level Interconnect Prediction, {SLIP}
'12, San Francisco, CA, USA, June 3, 2012},
pages = {2},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2347655.2347658},
doi = {10.1145/2347655.2347658},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/ChenLW12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/HuangQC12,
author = {Wenxun Huang and
Yujuan Quan and
Deming Chen},
title = {Improving broadcast efficiency in wireless sensor network time synchronization
protocols},
booktitle = {International Workshop on System Level Interconnect Prediction, {SLIP}
'12, San Francisco, CA, USA, June 3, 2012},
pages = {48--55},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2347655.2347672},
doi = {10.1145/2347655.2347672},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/HuangQC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/ManevichCK12,
author = {Ran Manevich and
Israel Cidon and
Avinoam Kolodny},
title = {Handling global traffic in future {CMP} NoCs},
booktitle = {International Workshop on System Level Interconnect Prediction, {SLIP}
'12, San Francisco, CA, USA, June 3, 2012},
pages = {40--47},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2347655.2347671},
doi = {10.1145/2347655.2347671},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/ManevichCK12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/MoreT12,
author = {Ankit More and
Baris Taskin},
title = {A locality-aware bi-level mesh-mesh 2d-noc architecture for future
thousand core CMPs},
booktitle = {International Workshop on System Level Interconnect Prediction, {SLIP}
'12, San Francisco, CA, USA, June 3, 2012},
pages = {22},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2347655.2347666},
doi = {10.1145/2347655.2347666},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/MoreT12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/OgrasEXKK12,
author = {{\"{U}}mit Y. Ogras and
Yunus Emre and
Jianping Xu and
Timothy Kam and
Michael Kishinevsky},
title = {Energy-guided exploration of on-chip network design for exa-scale
computing},
booktitle = {International Workshop on System Level Interconnect Prediction, {SLIP}
'12, San Francisco, CA, USA, June 3, 2012},
pages = {24--31},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2347655.2347669},
doi = {10.1145/2347655.2347669},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/OgrasEXKK12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/OgrasK12,
author = {{\"{U}}mit Y. Ogras and
Michael Kishinevsky},
title = {Design and optimization of communication fabrics: an industrial perspective},
booktitle = {International Workshop on System Level Interconnect Prediction, {SLIP}
'12, San Francisco, CA, USA, June 3, 2012},
pages = {19},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2347655.2347662},
doi = {10.1145/2347655.2347662},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/OgrasK12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/Paolone12,
author = {Mario Paolone},
title = {Towards the power networks of the future: needs, challenges and tools},
booktitle = {International Workshop on System Level Interconnect Prediction, {SLIP}
'12, San Francisco, CA, USA, June 3, 2012},
pages = {20},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2347655.2347664},
doi = {10.1145/2347655.2347664},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/Paolone12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/SamantaSRDB12,
author = {Tuhina Samanta and
Raka Sardar and
Hafizur Rahaman and
Parthasarathi Dasgupta and
Bhargab B. Bhattacharya},
title = {A heuristic method for obstacle avoiding group Steiner tree construction},
booktitle = {International Workshop on System Level Interconnect Prediction, {SLIP}
'12, San Francisco, CA, USA, June 3, 2012},
pages = {21},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2347655.2347665},
doi = {10.1145/2347655.2347665},
timestamp = {Tue, 22 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/SamantaSRDB12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/Srinivasa12,
author = {Ganapati Srinivasa},
title = {Heterogeneity and interconnect},
booktitle = {International Workshop on System Level Interconnect Prediction, {SLIP}
'12, San Francisco, CA, USA, June 3, 2012},
pages = {1},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2347655.2347656},
doi = {10.1145/2347655.2347656},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/Srinivasa12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/SunWCLZ12,
author = {Guang Sun and
Shih{-}Hung Weng and
Chung{-}Kuan Cheng and
Bill Lin and
Lieguang Zeng},
title = {An on-chip global broadcast network design with equalized transmission
lines in the 1024-core era},
booktitle = {International Workshop on System Level Interconnect Prediction, {SLIP}
'12, San Francisco, CA, USA, June 3, 2012},
pages = {11--18},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2347655.2347660},
doi = {10.1145/2347655.2347660},
timestamp = {Mon, 01 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/SunWCLZ12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/SwartzLFB12,
author = {William Swartz and
Yang{-}Yang Li and
Amin Farshidi and
Laleh Behjat},
title = {Analysis of post-placement length estimation},
booktitle = {International Workshop on System Level Interconnect Prediction, {SLIP}
'12, San Francisco, CA, USA, June 3, 2012},
pages = {23},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2347655.2347667},
doi = {10.1145/2347655.2347667},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/SwartzLFB12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/ZhangDKW12,
author = {Hongbo Zhang and
Yunfei Deng and
Jongwook Kye and
Martin D. F. Wong},
title = {Impact of lithography retargeting process on low level interconnect
in 20nm technology},
booktitle = {International Workshop on System Level Interconnect Prediction, {SLIP}
'12, San Francisco, CA, USA, June 3, 2012},
pages = {3--10},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2347655.2347659},
doi = {10.1145/2347655.2347659},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/ZhangDKW12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/slip/2012,
title = {International Workshop on System Level Interconnect Prediction, {SLIP}
'12, San Francisco, CA, USA, June 3, 2012},
publisher = {{ACM}},
year = {2012},
url = {http://dl.acm.org/citation.cfm?id=2347655},
isbn = {978-1-4503-1437-4},
timestamp = {Mon, 24 Mar 2014 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/2012.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/BezerraFZ11,
author = {George B. P. Bezerra and
Stephanie Forrest and
Payman Zarkesh{-}Ha},
editor = {Janet Meiling Wang and
Deming Chen},
title = {Reducing energy and increasing performance with traffic optimization
in many-core systems},
booktitle = {2011 International Workshop on System Level Interconnect Prediction,
{SLIP} 2011, San Diego, CA, USA, June 5, 2011},
pages = {1--7},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/SLIP.2011.6135429},
doi = {10.1109/SLIP.2011.6135429},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/BezerraFZ11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/ChouMOCKL11,
author = {Chen{-}Ling Chou and
Radu Marculescu and
{\"{U}}mit Y. Ogras and
Satrajit Chatterjee and
Michael Kishinevsky and
Dmitrii Loukianov},
editor = {Janet Meiling Wang and
Deming Chen},
title = {System interconnect design exploration for embedded MPSoCs},
booktitle = {2011 International Workshop on System Level Interconnect Prediction,
{SLIP} 2011, San Diego, CA, USA, June 5, 2011},
pages = {1--8},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/SLIP.2011.6135433},
doi = {10.1109/SLIP.2011.6135433},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/ChouMOCKL11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/DongCMC11,
author = {Chen Dong and
Chen Chen and
Subhasish Mitra and
Deming Chen},
editor = {Janet Meiling Wang and
Deming Chen},
title = {Architecture and performance evaluation of 3D {CMOS-NEM} {FPGA}},
booktitle = {2011 International Workshop on System Level Interconnect Prediction,
{SLIP} 2011, San Diego, CA, USA, June 5, 2011},
pages = {1--8},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/SLIP.2011.6135428},
doi = {10.1109/SLIP.2011.6135428},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/DongCMC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/HanJKL11,
author = {Sung Kyu Han and
Kwangok Jeong and
Andrew B. Kahng and
Jingwei Lu},
editor = {Janet Meiling Wang and
Deming Chen},
title = {Stability and scalability in global routing},
booktitle = {2011 International Workshop on System Level Interconnect Prediction,
{SLIP} 2011, San Diego, CA, USA, June 5, 2011},
pages = {1--6},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/SLIP.2011.6135431},
doi = {10.1109/SLIP.2011.6135431},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/HanJKL11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/JeongK11,
author = {Kwangok Jeong and
Andrew B. Kahng},
editor = {Janet Meiling Wang and
Deming Chen},
title = {Toward {PDN} resource estimation: {A} law of general power density},
booktitle = {2011 International Workshop on System Level Interconnect Prediction,
{SLIP} 2011, San Diego, CA, USA, June 5, 2011},
pages = {1--6},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/SLIP.2011.6135432},
doi = {10.1109/SLIP.2011.6135432},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/JeongK11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/KahngS11,
author = {Andrew B. Kahng and
Vaishnav Srinivas},
editor = {Janet Meiling Wang and
Deming Chen},
title = {Mobile system considerations for {SDRAM} interface trends},
booktitle = {2011 International Workshop on System Level Interconnect Prediction,
{SLIP} 2011, San Diego, CA, USA, June 5, 2011},
pages = {1--8},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/SLIP.2011.6135437},
doi = {10.1109/SLIP.2011.6135437},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/KahngS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/KimKL11,
author = {Daehyun Kim and
Suyoun Kim and
Sung Kyu Lim},
editor = {Janet Meiling Wang and
Deming Chen},
title = {Impact of nano-scale through-silicon vias on the quality of today
and future 3D {IC} designs},
booktitle = {2011 International Workshop on System Level Interconnect Prediction,
{SLIP} 2011, San Diego, CA, USA, June 5, 2011},
pages = {1--8},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/SLIP.2011.6135435},
doi = {10.1109/SLIP.2011.6135435},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/KimKL11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/KoseF11,
author = {Sel{\c{c}}uk K{\"{o}}se and
Eby G. Friedman},
editor = {Janet Meiling Wang and
Deming Chen},
title = {Distributed power network co-design with on-chip power supplies and
decoupling capacitors},
booktitle = {2011 International Workshop on System Level Interconnect Prediction,
{SLIP} 2011, San Diego, CA, USA, June 5, 2011},
pages = {1--5},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/SLIP.2011.6135434},
doi = {10.1109/SLIP.2011.6135434},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/KoseF11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/LiRBS11,
author = {Yang{-}Yang Li and
Logan M. Rakai and
Laleh Behjat and
Bill Swartz},
editor = {Janet Meiling Wang and
Deming Chen},
title = {Wirelength and congestion estimation for routability-driven placement},
booktitle = {2011 International Workshop on System Level Interconnect Prediction,
{SLIP} 2011, San Diego, CA, USA, June 5, 2011},
pages = {1},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/SLIP.2011.6135441},
doi = {10.1109/SLIP.2011.6135441},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/LiRBS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/MeisterLT11,
author = {Tilo Meister and
Jens Lienig and
Gisbert Thomke},
editor = {Janet Meiling Wang and
Deming Chen},
title = {Interface optimization for improved routability in chip-package-board
co-design},
booktitle = {2011 International Workshop on System Level Interconnect Prediction,
{SLIP} 2011, San Diego, CA, USA, June 5, 2011},
pages = {1--8},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/SLIP.2011.6135430},
doi = {10.1109/SLIP.2011.6135430},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/MeisterLT11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/MoreT11,
author = {Ankit More and
Baris Taskin},
editor = {Janet Meiling Wang and
Deming Chen},
title = {Simulation based study of on-chip antennas for a reconfigurable hybrid
2D wireless network-on-chip},
booktitle = {2011 International Workshop on System Level Interconnect Prediction,
{SLIP} 2011, San Diego, CA, USA, June 5, 2011},
pages = {1},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/SLIP.2011.6135440},
doi = {10.1109/SLIP.2011.6135440},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/MoreT11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/NguyenRK11,
author = {Hung Viet Nguyen and
Myunghwan Ryu and
Youngmin Kim},
editor = {Janet Meiling Wang and
Deming Chen},
title = {Performance and power analysis of through silicon via based 3D {IC}
integration},
booktitle = {2011 International Workshop on System Level Interconnect Prediction,
{SLIP} 2011, San Diego, CA, USA, June 5, 2011},
pages = {1},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/SLIP.2011.6135439},
doi = {10.1109/SLIP.2011.6135439},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/NguyenRK11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/YuhLHHYC11,
author = {Ping{-}Hung Yuh and
Cliff Chiung{-}Yu Lin and
Tsung{-}Wei Huang and
Tsung{-}Yi Ho and
Chia{-}Lin Yang and
Yao{-}Wen Chang},
editor = {Janet Meiling Wang and
Deming Chen},
title = {A SAT-based routing algorithm for cross-referencing biochips},
booktitle = {2011 International Workshop on System Level Interconnect Prediction,
{SLIP} 2011, San Diego, CA, USA, June 5, 2011},
pages = {1--7},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/SLIP.2011.6135436},
doi = {10.1109/SLIP.2011.6135436},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/YuhLHHYC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/slip/2011,
editor = {Janet Meiling Wang and
Deming Chen},
title = {2011 International Workshop on System Level Interconnect Prediction,
{SLIP} 2011, San Diego, CA, USA, June 5, 2011},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://ieeexplore.ieee.org/xpl/conhome/6125889/proceeding},
isbn = {978-1-4577-1240-1},
timestamp = {Wed, 16 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/2011.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/BezerraFFDZ10,
author = {George B. P. Bezerra and
Stephanie Forrest and
Melanie Forrest and
Al Davis and
Payman Zarkesh{-}Ha},
editor = {Sherief Reda and
Janet Meiling Wang},
title = {Modeling NoC traffic locality and energy consumption with rent's communication
probability distribution},
booktitle = {International Workshop on System Level Interconnect Prediction Workshop,
{SLIP} 2010, Anaheim, CA, USA, June 13, 2010},
pages = {3--8},
publisher = {{ACM}},
year = {2010},
url = {https://doi.org/10.1145/1811100.1811103},
doi = {10.1145/1811100.1811103},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/BezerraFFDZ10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/Borkar10,
author = {Shekhar Y. Borkar},
editor = {Sherief Reda and
Janet Meiling Wang},
title = {Future of interconnect fabric: a contrarian view},
booktitle = {International Workshop on System Level Interconnect Prediction Workshop,
{SLIP} 2010, Anaheim, CA, USA, June 13, 2010},
pages = {1--2},
publisher = {{ACM}},
year = {2010},
url = {https://doi.org/10.1145/1811100.1811101},
doi = {10.1145/1811100.1811101},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/Borkar10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/ChengAKS10,
author = {Chung{-}Kuan Cheng and
Andrew B. Kahng and
Kambiz Samadi and
Amirali Shayan Arani},
editor = {Sherief Reda and
Janet Meiling Wang},
title = {Worst-case performance prediction under supply voltage and temperature
variation},
booktitle = {International Workshop on System Level Interconnect Prediction Workshop,
{SLIP} 2010, Anaheim, CA, USA, June 13, 2010},
pages = {91--96},
publisher = {{ACM}},
year = {2010},
url = {https://doi.org/10.1145/1811100.1811121},
doi = {10.1145/1811100.1811121},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/ChengAKS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/CondleyHG10,
author = {Walter James Condley and
Xuchu Hu and
Matthew R. Guthaus},
editor = {Sherief Reda and
Janet Meiling Wang},
title = {Analysis of high-performance clock networks with {RLC} and transmission
line effects},
booktitle = {International Workshop on System Level Interconnect Prediction Workshop,
{SLIP} 2010, Anaheim, CA, USA, June 13, 2010},
pages = {51--58},
publisher = {{ACM}},
year = {2010},
url = {https://doi.org/10.1145/1811100.1811113},
doi = {10.1145/1811100.1811113},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/CondleyHG10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/GroeneveldSS10,
author = {Patrick Groeneveld and
Louis Scheffer and
Dirk Stroobandt},
editor = {Sherief Reda and
Janet Meiling Wang},
title = {{SLIP:} 10 years ago and 10 years from now},
booktitle = {International Workshop on System Level Interconnect Prediction Workshop,
{SLIP} 2010, Anaheim, CA, USA, June 13, 2010},
pages = {67--68},
publisher = {{ACM}},
year = {2010},
url = {https://doi.org/10.1145/1811100.1811116},
doi = {10.1145/1811100.1811116},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/GroeneveldSS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/KimL10,
author = {Daehyun Kim and
Sung Kyu Lim},
editor = {Sherief Reda and
Janet Meiling Wang},
title = {Through-silicon-via-aware delay and power prediction model for buffered
interconnects in 3D ICs},
booktitle = {International Workshop on System Level Interconnect Prediction Workshop,
{SLIP} 2010, Anaheim, CA, USA, June 13, 2010},
pages = {25--32},
publisher = {{ACM}},
year = {2010},
url = {https://doi.org/10.1145/1811100.1811108},
doi = {10.1145/1811100.1811108},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/KimL10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/LiML10,
author = {Di{-}An Li and
Malgorzata Marek{-}Sadowska and
Bill Lee},
editor = {Sherief Reda and
Janet Meiling Wang},
title = {On-chip em-sensitive interconnect structures},
booktitle = {International Workshop on System Level Interconnect Prediction Workshop,
{SLIP} 2010, Anaheim, CA, USA, June 13, 2010},
pages = {43--50},
publisher = {{ACM}},
year = {2010},
url = {https://doi.org/10.1145/1811100.1811112},
doi = {10.1145/1811100.1811112},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/LiML10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/MoreT10,
author = {Ankit More and
Baris Taskin},
editor = {Sherief Reda and
Janet Meiling Wang},
title = {Simulation based study of wireless {RF} interconnects for practical
CMOs implementation},
booktitle = {International Workshop on System Level Interconnect Prediction Workshop,
{SLIP} 2010, Anaheim, CA, USA, June 13, 2010},
pages = {35--42},
publisher = {{ACM}},
year = {2010},
url = {https://doi.org/10.1145/1811100.1811111},
doi = {10.1145/1811100.1811111},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/MoreT10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/QiuRH10,
author = {Jinhai Qiu and
Sherief Reda and
Soha Hassoun},
editor = {Sherief Reda and
Janet Meiling Wang},
title = {Fast, accurate a priori routing delay estimation},
booktitle = {International Workshop on System Level Interconnect Prediction Workshop,
{SLIP} 2010, Anaheim, CA, USA, June 13, 2010},
pages = {77--82},
publisher = {{ACM}},
year = {2010},
url = {https://doi.org/10.1145/1811100.1811119},
doi = {10.1145/1811100.1811119},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/QiuRH10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/Suaris10,
author = {Peter Ramyalal Suaris},
editor = {Sherief Reda and
Janet Meiling Wang},
title = {Application of 3-D ICs to FPGAs},
booktitle = {International Workshop on System Level Interconnect Prediction Workshop,
{SLIP} 2010, Anaheim, CA, USA, June 13, 2010},
pages = {15--16},
publisher = {{ACM}},
year = {2010},
url = {https://doi.org/10.1145/1811100.1811106},
doi = {10.1145/1811100.1811106},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/Suaris10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/Topaloglu10,
author = {Rasit Onur Topaloglu},
editor = {Sherief Reda and
Janet Meiling Wang},
title = {3-2-1 contact: an experimental approach to the analysisof contacts
in 45 nm and below},
booktitle = {International Workshop on System Level Interconnect Prediction Workshop,
{SLIP} 2010, Anaheim, CA, USA, June 13, 2010},
pages = {59--66},
publisher = {{ACM}},
year = {2010},
url = {https://doi.org/10.1145/1811100.1811114},
doi = {10.1145/1811100.1811114},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/Topaloglu10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/Wong10,
author = {Martin D. F. Wong},
editor = {Sherief Reda and
Janet Meiling Wang},
title = {Advances in {PCB} routing},
booktitle = {International Workshop on System Level Interconnect Prediction Workshop,
{SLIP} 2010, Anaheim, CA, USA, June 13, 2010},
pages = {33--34},
publisher = {{ACM}},
year = {2010},
url = {https://doi.org/10.1145/1811100.1811110},
doi = {10.1145/1811100.1811110},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/Wong10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/XuPM10,
author = {Hu Xu and
Vasilis F. Pavlidis and
Giovanni De Micheli},
editor = {Sherief Reda and
Janet Meiling Wang},
title = {Process-induced skew variation for scaled 2-D and 3-D ICs},
booktitle = {International Workshop on System Level Interconnect Prediction Workshop,
{SLIP} 2010, Anaheim, CA, USA, June 13, 2010},
pages = {17--24},
publisher = {{ACM}},
year = {2010},
url = {https://doi.org/10.1145/1811100.1811107},
doi = {10.1145/1811100.1811107},
timestamp = {Thu, 11 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/XuPM10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/YamanagaMS10,
author = {Koh Yamanaga and
Kazuya Masu and
Takashi Sato},
editor = {Sherief Reda and
Janet Meiling Wang},
title = {Application of generalized scattering matrix for prediction of power
supply noise},
booktitle = {International Workshop on System Level Interconnect Prediction Workshop,
{SLIP} 2010, Anaheim, CA, USA, June 13, 2010},
pages = {83--90},
publisher = {{ACM}},
year = {2010},
url = {https://doi.org/10.1145/1811100.1811120},
doi = {10.1145/1811100.1811120},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/YamanagaMS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/Zarkesh-HaBFM10,
author = {Payman Zarkesh{-}Ha and
George B. P. Bezerra and
Stephanie Forrest and
Melanie E. Moses},
editor = {Sherief Reda and
Janet Meiling Wang},
title = {Hybrid network on chip (HNoC): local buses with a global mesh architecture},
booktitle = {International Workshop on System Level Interconnect Prediction Workshop,
{SLIP} 2010, Anaheim, CA, USA, June 13, 2010},
pages = {9--14},
publisher = {{ACM}},
year = {2010},
url = {https://doi.org/10.1145/1811100.1811104},
doi = {10.1145/1811100.1811104},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/Zarkesh-HaBFM10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/ZhangBC10,
author = {Yulei Zhang and
James F. Buckwalter and
Chung{-}Kuan Cheng},
editor = {Sherief Reda and
Janet Meiling Wang},
title = {Performance prediction of throughput-centric pipelined global interconnects
with voltage scaling},
booktitle = {International Workshop on System Level Interconnect Prediction Workshop,
{SLIP} 2010, Anaheim, CA, USA, June 13, 2010},
pages = {69--76},
publisher = {{ACM}},
year = {2010},
url = {https://doi.org/10.1145/1811100.1811118},
doi = {10.1145/1811100.1811118},
timestamp = {Thu, 10 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/ZhangBC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/slip/2010,
editor = {Sherief Reda and
Janet Meiling Wang},
title = {International Workshop on System Level Interconnect Prediction Workshop,
{SLIP} 2010, Anaheim, CA, USA, June 13, 2010},
publisher = {{ACM}},
year = {2010},
url = {http://dl.acm.org/citation.cfm?id=1811100},
isbn = {978-1-4503-0037-7},
timestamp = {Wed, 25 Jan 2012 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/2010.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/Banerjee09,
author = {Kaustav Banerjee},
editor = {Chung{-}Kuan Cheng and
Sherief Reda},
title = {Graphene based nanomaterials for {VLSI} interconnect and energy-storage
applications},
booktitle = {The 11th International Workshop on System-Level Interconnect Prediction
{(SLIP} 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings},
pages = {105--106},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1572471.1572490},
doi = {10.1145/1572471.1572490},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/Banerjee09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/Bottoms09,
author = {Bill R. Bottoms},
editor = {Chung{-}Kuan Cheng and
Sherief Reda},
title = {Interconnect solutions for TeraScale computing},
booktitle = {The 11th International Workshop on System-Level Interconnect Prediction
{(SLIP} 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings},
pages = {1--2},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1572471.1572472},
doi = {10.1145/1572471.1572472},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/Bottoms09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/CessnaB09,
author = {Joseph B. Cessna and
Thomas R. Bewley},
editor = {Chung{-}Kuan Cheng and
Sherief Reda},
title = {Honeycomb-structured computational interconnects and their scalable
extension to spherical domains},
booktitle = {The 11th International Workshop on System-Level Interconnect Prediction
{(SLIP} 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings},
pages = {27--36},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1572471.1572477},
doi = {10.1145/1572471.1572477},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/CessnaB09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/CongCRT09,
author = {Jason Cong and
Mau{-}Chung Frank Chang and
Glenn Reinman and
Sai{-}Wang Tam},
editor = {Chung{-}Kuan Cheng and
Sherief Reda},
title = {Multiband RF-interconnect for reconfigurable network-on-chip communications},
booktitle = {The 11th International Workshop on System-Level Interconnect Prediction
{(SLIP} 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings},
pages = {107--108},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1572471.1572491},
doi = {10.1145/1572471.1572491},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/CongCRT09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/DingP09,
author = {Duo Ding and
David Z. Pan},
editor = {Chung{-}Kuan Cheng and
Sherief Reda},
title = {{OIL:} a nano-photonics optical interconnect library for a new photonic
networks-on-chip architecture},
booktitle = {The 11th International Workshop on System-Level Interconnect Prediction
{(SLIP} 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings},
pages = {11--18},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1572471.1572475},
doi = {10.1145/1572471.1572475},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/DingP09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/FathiBR09,
author = {Bahareh Fathi and
Laleh Behjat and
Logan M. Rakai},
editor = {Chung{-}Kuan Cheng and
Sherief Reda},
title = {A pre-placement net length estimation technique for mixed-size circuits},
booktitle = {The 11th International Workshop on System-Level Interconnect Prediction
{(SLIP} 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings},
pages = {45--52},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1572471.1572480},
doi = {10.1145/1572471.1572480},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/FathiBR09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/FischbachLM09,
author = {Robert Fischbach and
Jens Lienig and
Tilo Meister},
editor = {Chung{-}Kuan Cheng and
Sherief Reda},
title = {From 3D circuit technologies and data structures to interconnect prediction},
booktitle = {The 11th International Workshop on System-Level Interconnect Prediction
{(SLIP} 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings},
pages = {77--84},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1572471.1572485},
doi = {10.1145/1572471.1572485},
timestamp = {Wed, 14 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/FischbachLM09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/HeDHG09,
author = {Xu He and
Sheqin Dong and
Xianlong Hong and
Satoshi Goto},
editor = {Chung{-}Kuan Cheng and
Sherief Reda},
title = {Integrated interlayer via planning and pin assignment for 3D ICs},
booktitle = {The 11th International Workshop on System-Level Interconnect Prediction
{(SLIP} 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings},
pages = {99--104},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1572471.1572488},
doi = {10.1145/1572471.1572488},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/HeDHG09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/HuZDZAPEC09,
author = {Xiang Hu and
Wenbo Zhao and
Peng Du and
Yulei Zhang and
Amirali Shayan Arani and
Christopher Pan and
A. Ege Engin and
Chung{-}Kuan Cheng},
editor = {Chung{-}Kuan Cheng and
Sherief Reda},
title = {On the bound of time-domain power supply noise based on frequency-domain
target impedance},
booktitle = {The 11th International Workshop on System-Level Interconnect Prediction
{(SLIP} 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings},
pages = {69--76},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1572471.1572483},
doi = {10.1145/1572471.1572483},
timestamp = {Thu, 07 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/HuZDZAPEC09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/JeongKT09,
author = {Kwangok Jeong and
Andrew B. Kahng and
Rasit Onur Topaloglu},
editor = {Chung{-}Kuan Cheng and
Sherief Reda},
title = {Is overlay error more important than interconnect variations in double
patterning?},
booktitle = {The 11th International Workshop on System-Level Interconnect Prediction
{(SLIP} 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings},
pages = {3--10},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1572471.1572474},
doi = {10.1145/1572471.1572474},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/JeongKT09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/JevticCP09,
author = {Ruzica Jevtic and
Carlos Carreras and
Vukasin Pejovic},
editor = {Chung{-}Kuan Cheng and
Sherief Reda},
title = {Floorplan-based {FPGA} interconnect power estimation in {DSP} circuits},
booktitle = {The 11th International Workshop on System-Level Interconnect Prediction
{(SLIP} 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings},
pages = {53--60},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1572471.1572481},
doi = {10.1145/1572471.1572481},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/JevticCP09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/KimML09,
author = {Dae Hyun Kim and
Saibal Mukhopadhyay and
Sung Kyu Lim},
editor = {Chung{-}Kuan Cheng and
Sherief Reda},
title = {Through-silicon-via aware interconnect prediction and optimization
for 3D stacked ICs},
booktitle = {The 11th International Workshop on System-Level Interconnect Prediction
{(SLIP} 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings},
pages = {85--92},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1572471.1572486},
doi = {10.1145/1572471.1572486},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/KimML09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/Nayak09,
author = {Saroj K. Nayak},
editor = {Chung{-}Kuan Cheng and
Sherief Reda},
title = {Carbon nanotube, graphene and atomic wires as next generation interconnects:
current status and future promise},
booktitle = {The 11th International Workshop on System-Level Interconnect Prediction
{(SLIP} 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings},
pages = {109--110},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1572471.1572492},
doi = {10.1145/1572471.1572492},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/Nayak09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/Reda09,
author = {Sherief Reda},
editor = {Chung{-}Kuan Cheng and
Sherief Reda},
title = {Using circuit structural analysis techniques for networks in systems
biology},
booktitle = {The 11th International Workshop on System-Level Interconnect Prediction
{(SLIP} 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings},
pages = {37--44},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1572471.1572478},
doi = {10.1145/1572471.1572478},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/Reda09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/Saraswat09,
author = {Krishna Saraswat},
editor = {Chung{-}Kuan Cheng and
Sherief Reda},
title = {Performance comparison of cu/low-k, carbon nanotube, and optics for
on-chip and off-chip interconnects},
booktitle = {The 11th International Workshop on System-Level Interconnect Prediction
{(SLIP} 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings},
pages = {111--112},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1572471.1572493},
doi = {10.1145/1572471.1572493},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/Saraswat09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/SunL09,
author = {Peng Sun and
Rong Luo},
editor = {Chung{-}Kuan Cheng and
Sherief Reda},
title = {Closed-form solution for timing analysis of process variations on
{SWCNT} interconnect},
booktitle = {The 11th International Workshop on System-Level Interconnect Prediction
{(SLIP} 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings},
pages = {19--26},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1572471.1572476},
doi = {10.1145/1572471.1572476},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/SunL09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/ZhangHDEBC09,
author = {Yulei Zhang and
Xiang Hu and
Alina Deutsch and
A. Ege Engin and
James F. Buckwalter and
Chung{-}Kuan Cheng},
editor = {Chung{-}Kuan Cheng and
Sherief Reda},
title = {Prediction of high-performance on-chip global interconnection},
booktitle = {The 11th International Workshop on System-Level Interconnect Prediction
{(SLIP} 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings},
pages = {61--68},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1572471.1572482},
doi = {10.1145/1572471.1572482},
timestamp = {Thu, 10 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/ZhangHDEBC09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/ZhangYHAEC09,
author = {Wanping Zhang and
Wenjian Yu and
Xiang Hu and
Amirali Shayan Arani and
A. Ege Engin and
Chung{-}Kuan Cheng},
editor = {Chung{-}Kuan Cheng and
Sherief Reda},
title = {Predicting the worst-case voltage violation in a 3D power network},
booktitle = {The 11th International Workshop on System-Level Interconnect Prediction
{(SLIP} 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings},
pages = {93--98},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1572471.1572487},
doi = {10.1145/1572471.1572487},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/ZhangYHAEC09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/slip/2009,
editor = {Chung{-}Kuan Cheng and
Sherief Reda},
title = {The 11th International Workshop on System-Level Interconnect Prediction
{(SLIP} 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings},
publisher = {{ACM}},
year = {2009},
isbn = {978-1-60558-576-5},
timestamp = {Mon, 23 Nov 2009 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/2009.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/ChaudhuriGHD08,
author = {Sumanta Chaudhuri and
Sylvain Guilley and
Philippe Hoogvorst and
Jean{-}Luc Danger},
editor = {Ion I. Mandoiu and
Andrew A. Kennings},
title = {Efficient tiling patterns for reconfigurable gate arrays},
booktitle = {The Tenth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2008), Newcastle, UK, April 5-8, 2008, Proceedings},
pages = {11--18},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1353610.1353613},
doi = {10.1145/1353610.1353613},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/ChaudhuriGHD08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/DobkinMKG08,
author = {Rostislav (Reuven) Dobkin and
Arkadiy Morgenshtein and
Avinoam Kolodny and
Ran Ginosar},
editor = {Ion I. Mandoiu and
Andrew A. Kennings},
title = {Parallel vs. serial on-chip communication},
booktitle = {The Tenth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2008), Newcastle, UK, April 5-8, 2008, Proceedings},
pages = {43--50},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1353610.1353620},
doi = {10.1145/1353610.1353620},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/DobkinMKG08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/HalakSRYR08,
author = {Basel Halak and
Santosh Shedabale and
Hiran Ramakrishnan and
Alexandre Yakovlev and
Gordon Russell},
editor = {Ion I. Mandoiu and
Andrew A. Kennings},
title = {The impact of variability on the reliability of long on-chip interconnect
in the presence of crosstalk},
booktitle = {The Tenth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2008), Newcastle, UK, April 5-8, 2008, Proceedings},
pages = {65--72},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1353610.1353624},
doi = {10.1145/1353610.1353624},
timestamp = {Tue, 01 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/HalakSRYR08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/HeirmanDSC08,
author = {Wim Heirman and
Joni Dambre and
Dirk Stroobandt and
Jan M. Van Campenhout},
editor = {Ion I. Mandoiu and
Andrew A. Kennings},
title = {Rent's rule and parallel programs: characterizing network traffic
behavior},
booktitle = {The Tenth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2008), Newcastle, UK, April 5-8, 2008, Proceedings},
pages = {87--94},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1353610.1353628},
doi = {10.1145/1353610.1353628},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/HeirmanDSC08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/HuRM08,
author = {Jin Hu and
Jarrod A. Roy and
Igor L. Markov},
editor = {Ion I. Mandoiu and
Andrew A. Kennings},
title = {Sidewinder: a scalable ILP-based router},
booktitle = {The Tenth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2008), Newcastle, UK, April 5-8, 2008, Proceedings},
pages = {73--80},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1353610.1353625},
doi = {10.1145/1353610.1353625},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/HuRM08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/MadinaT08,
author = {Duraid Madina and
Makoto Taiji},
editor = {Ion I. Mandoiu and
Andrew A. Kennings},
title = {Circuit and physical design of the {MDGRAPE-4} on-chip network links},
booktitle = {The Tenth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2008), Newcastle, UK, April 5-8, 2008, Proceedings},
pages = {59--64},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1353610.1353622},
doi = {10.1145/1353610.1353622},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/MadinaT08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/MakDSCYL08,
author = {Terrence S. T. Mak and
Crescenzo D'Alessandro and
N. Pete Sedcole and
Peter Y. K. Cheung and
Alexandre Yakovlev and
Wayne Luk},
editor = {Ion I. Mandoiu and
Andrew A. Kennings},
title = {Global interconnections in FPGAs: modeling and performance analysis},
booktitle = {The Tenth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2008), Newcastle, UK, April 5-8, 2008, Proceedings},
pages = {51--58},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1353610.1353621},
doi = {10.1145/1353610.1353621},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/MakDSCYL08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/MakSCL08,
author = {Terrence S. T. Mak and
N. Pete Sedcole and
Peter Y. K. Cheung and
Wayne Luk},
editor = {Ion I. Mandoiu and
Andrew A. Kennings},
title = {Interconnection lengths and delays estimation for communication links
in FPGAs},
booktitle = {The Tenth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2008), Newcastle, UK, April 5-8, 2008, Proceedings},
pages = {1--10},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1353610.1353612},
doi = {10.1145/1353610.1353612},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/MakSCL08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/MooreG08,
author = {Simon W. Moore and
Daniel Greenfield},
editor = {Ion I. Mandoiu and
Andrew A. Kennings},
title = {The next resource war: computation vs. communication},
booktitle = {The Tenth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2008), Newcastle, UK, April 5-8, 2008, Proceedings},
pages = {81--86},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1353610.1353627},
doi = {10.1145/1353610.1353627},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/MooreG08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/MorgenshteinFGK08,
author = {Arkadiy Morgenshtein and
Eby G. Friedman and
Ran Ginosar and
Avinoam Kolodny},
editor = {Ion I. Mandoiu and
Andrew A. Kennings},
title = {Timing optimization in logic with interconnect},
booktitle = {The Tenth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2008), Newcastle, UK, April 5-8, 2008, Proceedings},
pages = {19--26},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1353610.1353615},
doi = {10.1145/1353610.1353615},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/MorgenshteinFGK08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/SamantaGRD08,
author = {Tuhina Samanta and
Prasun Ghosal and
Hafizur Rahaman and
Parthasarathi Dasgupta},
editor = {Ion I. Mandoiu and
Andrew A. Kennings},
title = {Revisiting fidelity: a case of elmore-based Y-routing trees},
booktitle = {The Tenth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2008), Newcastle, UK, April 5-8, 2008, Proceedings},
pages = {27--34},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1353610.1353616},
doi = {10.1145/1353610.1353616},
timestamp = {Tue, 22 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/SamantaGRD08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/SmitKWB08,
author = {Gerard J. M. Smit and
Andr{\'{e}} B. J. Kokkeler and
Pascal T. Wolkotte and
Marcel D. van de Burgwal},
editor = {Ion I. Mandoiu and
Andrew A. Kennings},
title = {Multi-core architectures and streaming applications},
booktitle = {The Tenth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2008), Newcastle, UK, April 5-8, 2008, Proceedings},
pages = {35--42},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1353610.1353618},
doi = {10.1145/1353610.1353618},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/SmitKWB08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/slip/2008,
editor = {Ion I. Mandoiu and
Andrew A. Kennings},
title = {The Tenth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2008), Newcastle, UK, April 5-8, 2008, Proceedings},
publisher = {{ACM}},
year = {2008},
isbn = {978-1-59593-918-0},
timestamp = {Tue, 08 Apr 2008 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/2008.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/AlpertKLNQRSVY07,
author = {Charles J. Alpert and
Shrirang K. Karandikar and
Zhuo Li and
Gi{-}Joon Nam and
Stephen T. Quay and
Haoxing Ren and
Cliff C. N. Sze and
Paul G. Villarrubia and
Mehmet Can Yildiz},
editor = {Andrew A. Kennings and
Ion I. Mandoiu},
title = {The nuts and bolts of physical synthesis},
booktitle = {The Ninth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2007), Austin, Texas, USA, March 17-18, 2007, Proceedings},
pages = {89--94},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1231956.1231975},
doi = {10.1145/1231956.1231975},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/AlpertKLNQRSVY07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/AmakawaUSOM07,
author = {Shuhei Amakawa and
Takumi Uezono and
Takashi Sato and
Kenichi Okada and
Kazuya Masu},
editor = {Andrew A. Kennings and
Ion I. Mandoiu},
title = {Adaptable wire-length distribution with tunable occupation probability},
booktitle = {The Ninth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2007), Austin, Texas, USA, March 17-18, 2007, Proceedings},
pages = {1--8},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1231956.1231958},
doi = {10.1145/1231956.1231958},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/AmakawaUSOM07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/ChoKKS07,
author = {Hoyeol Cho and
Kyung{-}Hoae Koo and
Pawan Kapur and
Krishna Saraswat},
editor = {Andrew A. Kennings and
Ion I. Mandoiu},
title = {Modeling of the performance of carbon nanotube bundle, cu/low-k and
optical on-chip global interconnects},
booktitle = {The Ninth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2007), Austin, Texas, USA, March 17-18, 2007, Proceedings},
pages = {81--88},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1231956.1231973},
doi = {10.1145/1231956.1231973},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/ChoKKS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/HatirnazBPLMAM07,
author = {Ilhan Hatirnaz and
St{\'{e}}phane Badel and
Nuria Pazos and
Yusuf Leblebici and
Srinivasan Murali and
David Atienza and
Giovanni De Micheli},
editor = {Andrew A. Kennings and
Ion I. Mandoiu},
title = {Early wire characterization for predictable network-on-chip global
interconnects},
booktitle = {The Ninth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2007), Austin, Texas, USA, March 17-18, 2007, Proceedings},
pages = {57--64},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1231956.1231969},
doi = {10.1145/1231956.1231969},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/HatirnazBPLMAM07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/HeirmanDC07,
author = {Wim Heirman and
Joni Dambre and
Jan Van Campenhout},
editor = {Andrew A. Kennings and
Ion I. Mandoiu},
title = {Synthetic traffic generation as a tool for dynamic interconnect evaluation},
booktitle = {The Ninth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2007), Austin, Texas, USA, March 17-18, 2007, Proceedings},
pages = {65--72},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1231956.1231970},
doi = {10.1145/1231956.1231970},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/HeirmanDC07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/HuTJH07,
author = {Yu Hu and
King Ho Tam and
Tong Jing and
Lei He},
editor = {Andrew A. Kennings and
Ion I. Mandoiu},
title = {Fast dual-vdd buffering based on interconnect prediction and sampling},
booktitle = {The Ninth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2007), Austin, Texas, USA, March 17-18, 2007, Proceedings},
pages = {95--102},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1231956.1231976},
doi = {10.1145/1231956.1231976},
timestamp = {Wed, 30 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/HuTJH07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/Kolodny07,
author = {Avinoam Kolodny},
editor = {Andrew A. Kennings and
Ion I. Mandoiu},
title = {Networks on chips: keeping up with Rent's rule and Moore's law},
booktitle = {The Ninth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2007), Austin, Texas, USA, March 17-18, 2007, Proceedings},
pages = {55--56},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1231956.1231968},
doi = {10.1145/1231956.1231968},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/Kolodny07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/LanzerottiFR07,
author = {Mary Yvonne Lanzerotti and
Giovanni Fiorenza and
Rick A. Rand},
editor = {Andrew A. Kennings and
Ion I. Mandoiu},
title = {Impact of interconnect length changes on effective materials properties
(dielectric constant)},
booktitle = {The Ninth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2007), Austin, Texas, USA, March 17-18, 2007, Proceedings},
pages = {73--80},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1231956.1231972},
doi = {10.1145/1231956.1231972},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/LanzerottiFR07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/LinLC07,
author = {I{-}Jye Lin and
Tsui{-}Yee Ling and
Yao{-}Wen Chang},
editor = {Andrew A. Kennings and
Ion I. Mandoiu},
title = {Statistical circuit optimization considering device andinterconnect
process variations},
booktitle = {The Ninth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2007), Austin, Texas, USA, March 17-18, 2007, Proceedings},
pages = {47--54},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1231956.1231966},
doi = {10.1145/1231956.1231966},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/LinLC07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/MitevMMW07,
author = {Alexander V. Mitev and
Michael M. Marefat and
Dongsheng Ma and
Janet Meiling Wang},
editor = {Andrew A. Kennings and
Ion I. Mandoiu},
title = {Principle hessian direction based parameter reduction for interconnect
networks with process variation},
booktitle = {The Ninth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2007), Austin, Texas, USA, March 17-18, 2007, Proceedings},
pages = {41--46},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1231956.1231965},
doi = {10.1145/1231956.1231965},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/MitevMMW07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/SatyanarayanaMB07,
author = {Nallamothu Satyanarayana and
Madhu Mutyam and
A. Vinaya Babu},
editor = {Andrew A. Kennings and
Ion I. Mandoiu},
title = {Exploiting on-chip data behavior for delay minimization},
booktitle = {The Ninth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2007), Austin, Texas, USA, March 17-18, 2007, Proceedings},
pages = {103--110},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1231956.1231977},
doi = {10.1145/1231956.1231977},
timestamp = {Wed, 25 Sep 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/SatyanarayanaMB07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/TaghaviDNS07,
author = {Taraneh Taghavi and
Foad Dabiri and
Ani Nahapetian and
Majid Sarrafzadeh},
editor = {Andrew A. Kennings and
Ion I. Mandoiu},
title = {Tutorial on congestion prediction},
booktitle = {The Ninth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2007), Austin, Texas, USA, March 17-18, 2007, Proceedings},
pages = {15--24},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1231956.1231961},
doi = {10.1145/1231956.1231961},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/TaghaviDNS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/WeiDHM07,
author = {Yaoguang Wei and
Sheqin Dong and
Xianlong Hong and
Yuchun Ma},
editor = {Andrew A. Kennings and
Ion I. Mandoiu},
title = {An accurate and efficient probabilistic congestion estimation model
in x architecture},
booktitle = {The Ninth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2007), Austin, Texas, USA, March 17-18, 2007, Proceedings},
pages = {25--32},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1231956.1231962},
doi = {10.1145/1231956.1231962},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/WeiDHM07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/YeagerCL07,
author = {David Yeager and
Darius Chiu and
Guy G. Lemieux},
editor = {Andrew A. Kennings and
Ion I. Mandoiu},
title = {Congestion estimation and localization in {FPGAS:} a visual tool for
interconnect prediction},
booktitle = {The Ninth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2007), Austin, Texas, USA, March 17-18, 2007, Proceedings},
pages = {33--40},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1231956.1231963},
doi = {10.1145/1231956.1231963},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/YeagerCL07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/Zarkesh-HaD07,
author = {Payman Zarkesh{-}Ha and
Ken Doniger},
editor = {Andrew A. Kennings and
Ion I. Mandoiu},
title = {Stochastic interconnect layout sensitivity model},
booktitle = {The Ninth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2007), Austin, Texas, USA, March 17-18, 2007, Proceedings},
pages = {9--14},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1231956.1231959},
doi = {10.1145/1231956.1231959},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/Zarkesh-HaD07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/slip/2007,
editor = {Andrew A. Kennings and
Ion I. Mandoiu},
title = {The Ninth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2007), Austin, Texas, USA, March 17-18, 2007, Proceedings},
publisher = {{ACM}},
year = {2007},
isbn = {978-1-59593-622-6},
timestamp = {Mon, 27 Aug 2007 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/2007.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/AnbalaganD06,
author = {Pranav Anbalagan and
Jeffrey A. Davis},
editor = {Mike Hutton and
Joni Dambre},
title = {A priori prediction of tightly clustered connections based on heuristic
classification trees},
booktitle = {The Eigth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2006), Munich, Germany, March 4-5, 2006, Proceedings},
pages = {9--15},
publisher = {{ACM}},
year = {2006},
url = {https://doi.org/10.1145/1117278.1117281},
doi = {10.1145/1117278.1117281},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/AnbalaganD06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/BalachandranBCKRNB06,
author = {J. Balachandran and
Steven Brebels and
Geert Carchon and
Maarten Kuijk and
Walter De Raedt and
Bart Nauwelaers and
Eric Beyne},
editor = {Mike Hutton and
Joni Dambre},
title = {Constant impedance scaling paradigm for interconnect synthesis},
booktitle = {The Eigth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2006), Munich, Germany, March 4-5, 2006, Proceedings},
pages = {99--105},
publisher = {{ACM}},
year = {2006},
url = {https://doi.org/10.1145/1117278.1117298},
doi = {10.1145/1117278.1117298},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/BalachandranBCKRNB06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/BamalTZSM06,
author = {Mandeep Bamal and
Youssef Travaly and
Wenqi Zhang and
Michele Stucchi and
Karen Maex},
editor = {Mike Hutton and
Joni Dambre},
title = {Impact of interconnect resistance increase on system performance of
low power and high performance designs},
booktitle = {The Eigth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2006), Munich, Germany, March 4-5, 2006, Proceedings},
pages = {85--90},
publisher = {{ACM}},
year = {2006},
url = {https://doi.org/10.1145/1117278.1117296},
doi = {10.1145/1117278.1117296},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/BamalTZSM06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/ChoCC06,
author = {Young{-}Sin Cho and
Eun{-}Ju Choi and
Kyoung{-}Rok Cho},
editor = {Mike Hutton and
Joni Dambre},
title = {Modeling and analysis of the system bus latency on the SoC platform},
booktitle = {The Eigth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2006), Munich, Germany, March 4-5, 2006, Proceedings},
pages = {67--74},
publisher = {{ACM}},
year = {2006},
url = {https://doi.org/10.1145/1117278.1117293},
doi = {10.1145/1117278.1117293},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/ChoCC06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/FengG06,
author = {Wenyi Feng and
Jonathan W. Greene},
editor = {Mike Hutton and
Joni Dambre},
title = {Post-placement interconnect entropy: how many configuration bits does
a programmable logic device need?},
booktitle = {The Eigth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2006), Munich, Germany, March 4-5, 2006, Proceedings},
pages = {41--48},
publisher = {{ACM}},
year = {2006},
url = {https://doi.org/10.1145/1117278.1117289},
doi = {10.1145/1117278.1117289},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/FengG06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/GuoPMC06,
author = {Jin Guo and
Antonis Papanikolaou and
Pol Marchal and
Francky Catthoor},
editor = {Mike Hutton and
Joni Dambre},
title = {Energy/area/delay trade-offs in the physical design of on-chip segmented
bus architecture},
booktitle = {The Eigth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2006), Munich, Germany, March 4-5, 2006, Proceedings},
pages = {75--81},
publisher = {{ACM}},
year = {2006},
url = {https://doi.org/10.1145/1117278.1117294},
doi = {10.1145/1117278.1117294},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/GuoPMC06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/HeirmanDC06,
author = {Wim Heirman and
Joni Dambre and
Jan M. Van Campenhout},
editor = {Mike Hutton and
Joni Dambre},
title = {Congestion modeling for reconfigurable inter-processor networks},
booktitle = {The Eigth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2006), Munich, Germany, March 4-5, 2006, Proceedings},
pages = {59--66},
publisher = {{ACM}},
year = {2006},
url = {https://doi.org/10.1145/1117278.1117292},
doi = {10.1145/1117278.1117292},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/HeirmanDC06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/KahngLX06,
author = {Andrew B. Kahng and
Bao Liu and
Xu Xu},
editor = {Mike Hutton and
Joni Dambre},
title = {Statistical crosstalk aggressor alignment aware interconnect delay
calculation},
booktitle = {The Eigth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2006), Munich, Germany, March 4-5, 2006, Proceedings},
pages = {91--97},
publisher = {{ACM}},
year = {2006},
url = {https://doi.org/10.1145/1117278.1117297},
doi = {10.1145/1117278.1117297},
timestamp = {Thu, 21 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/KahngLX06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/KahngR06,
author = {Andrew B. Kahng and
Sherief Reda},
editor = {Mike Hutton and
Joni Dambre},
title = {A tale of two nets: studies of wirelength progression in physical
design},
booktitle = {The Eigth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2006), Munich, Germany, March 4-5, 2006, Proceedings},
pages = {17--24},
publisher = {{ACM}},
year = {2006},
url = {https://doi.org/10.1145/1117278.1117282},
doi = {10.1145/1117278.1117282},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/KahngR06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/KahngT06,
author = {Andrew B. Kahng and
Rasit Onur Topaloglu},
editor = {Mike Hutton and
Joni Dambre},
title = {Generation of design guarantees for interconnect matching},
booktitle = {The Eigth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2006), Munich, Germany, March 4-5, 2006, Proceedings},
pages = {29--34},
publisher = {{ACM}},
year = {2006},
url = {https://doi.org/10.1145/1117278.1117285},
doi = {10.1145/1117278.1117285},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/KahngT06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/ManohararajahCSB06,
author = {Valavan Manohararajah and
Gordon R. Chiu and
Deshanand P. Singh and
Stephen Dean Brown},
editor = {Mike Hutton and
Joni Dambre},
title = {Difficulty of predicting interconnect delay in a timing driven {FPGA}
{CAD} flow},
booktitle = {The Eigth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2006), Munich, Germany, March 4-5, 2006, Proceedings},
pages = {3--8},
publisher = {{ACM}},
year = {2006},
url = {https://doi.org/10.1145/1117278.1117280},
doi = {10.1145/1117278.1117280},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/ManohararajahCSB06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/SaldanaSC06,
author = {Manuel Salda{\~{n}}a and
Lesley Shannon and
Paul Chow},
editor = {Mike Hutton and
Joni Dambre},
title = {The routability of multiprocessor network topologies in FPGAs},
booktitle = {The Eigth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2006), Munich, Germany, March 4-5, 2006, Proceedings},
pages = {49--56},
publisher = {{ACM}},
year = {2006},
url = {https://doi.org/10.1145/1117278.1117290},
doi = {10.1145/1117278.1117290},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/SaldanaSC06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/Saxena06,
author = {Prashant Saxena},
editor = {Mike Hutton and
Joni Dambre},
title = {The scaling of interconnect buffer needs},
booktitle = {The Eigth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2006), Munich, Germany, March 4-5, 2006, Proceedings},
pages = {109--112},
publisher = {{ACM}},
year = {2006},
url = {https://doi.org/10.1145/1117278.1117300},
doi = {10.1145/1117278.1117300},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/Saxena06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/Scheffer06,
author = {Louis Scheffer},
editor = {Mike Hutton and
Joni Dambre},
title = {An overview of on-chip interconnect variation},
booktitle = {The Eigth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2006), Munich, Germany, March 4-5, 2006, Proceedings},
pages = {27--28},
publisher = {{ACM}},
year = {2006},
url = {https://doi.org/10.1145/1117278.1117284},
doi = {10.1145/1117278.1117284},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/Scheffer06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/Visweswariah06,
author = {Chandu Visweswariah},
editor = {Mike Hutton and
Joni Dambre},
title = {Statistical analysis and optimization in the presence of gate and
interconnect delay variations},
booktitle = {The Eigth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2006), Munich, Germany, March 4-5, 2006, Proceedings},
pages = {37},
publisher = {{ACM}},
year = {2006},
url = {https://doi.org/10.1145/1117278.1117287},
doi = {10.1145/1117278.1117287},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/Visweswariah06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/WeerasekeraPZT06,
author = {Roshan Weerasekera and
Dinesh Pamunuwa and
Li{-}Rong Zheng and
Hannu Tenhunen},
editor = {Mike Hutton and
Joni Dambre},
title = {Minimal-power, delay-balanced smart repeaters for interconnects in
the nanometer regime},
booktitle = {The Eigth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2006), Munich, Germany, March 4-5, 2006, Proceedings},
pages = {113--120},
publisher = {{ACM}},
year = {2006},
url = {https://doi.org/10.1145/1117278.1117301},
doi = {10.1145/1117278.1117301},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/WeerasekeraPZT06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/slip/2006,
editor = {Mike Hutton and
Joni Dambre},
title = {The Eigth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2006), Munich, Germany, March 4-5, 2006, Proceedings},
publisher = {{ACM}},
year = {2006},
isbn = {1-59593-255-0},
timestamp = {Wed, 05 Apr 2006 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/2006.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/BalachandranBCWRNB05,
author = {J. Balachandran and
Steven Brebels and
Geert Carchon and
Tomas Webers and
Walter De Raedt and
Bart Nauwelaers and
Eric Beyne},
editor = {Igor L. Markov and
Mike Hutton},
title = {Package level interconnect options},
booktitle = {The Seventh International Workshop on System-Level Interconnect Prediction
{(SLIP} 2005), San Francisco, CA, USA, April 2-3, 2005, Proceedings},
pages = {21--27},
publisher = {{ACM}},
year = {2005},
url = {https://doi.org/10.1145/1053355.1053361},
doi = {10.1145/1053355.1053361},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/BalachandranBCWRNB05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/ChenCHNFFA05,
author = {Guoqing Chen and
Hui Chen and
Mikhail Haurylau and
Nicholas Nelson and
Philippe M. Fauchet and
Eby G. Friedman and
David H. Albonesi},
editor = {Igor L. Markov and
Mike Hutton},
title = {Predictions of {CMOS} compatible on-chip optical interconnect},
booktitle = {The Seventh International Workshop on System-Level Interconnect Prediction
{(SLIP} 2005), San Francisco, CA, USA, April 2-3, 2005, Proceedings},
pages = {13--20},
publisher = {{ACM}},
year = {2005},
url = {https://doi.org/10.1145/1053355.1053360},
doi = {10.1145/1053355.1053360},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/ChenCHNFFA05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/Hathaway05,
author = {David J. Hathaway},
editor = {Igor L. Markov and
Mike Hutton},
title = {Dealing with the spatio-temporal interactions among transient power,
supply noise and timing},
booktitle = {The Seventh International Workshop on System-Level Interconnect Prediction
{(SLIP} 2005), San Francisco, CA, USA, April 2-3, 2005, Proceedings},
pages = {61},
publisher = {{ACM}},
year = {2005},
url = {https://doi.org/10.1145/1053355.1053369},
doi = {10.1145/1053355.1053369},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/Hathaway05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/HeirmanDDTSC05,
author = {Wim Heirman and
Joni Dambre and
Christof Debaes and
Hugo Thienpont and
Dirk Stroobandt and
Jan Van Campenhout},
editor = {Igor L. Markov and
Mike Hutton},
title = {Prediction model for evaluation of reconfigurable interconnects in
distributed shared-memory systems},
booktitle = {The Seventh International Workshop on System-Level Interconnect Prediction
{(SLIP} 2005), San Francisco, CA, USA, April 2-3, 2005, Proceedings},
pages = {51--58},
publisher = {{ACM}},
year = {2005},
url = {https://doi.org/10.1145/1053355.1053367},
doi = {10.1145/1053355.1053367},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/HeirmanDDTSC05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/Ho05,
author = {Ron Ho},
editor = {Igor L. Markov and
Mike Hutton},
title = {High-performance {ULSI:} the real limiter to interconnect scaling},
booktitle = {The Seventh International Workshop on System-Level Interconnect Prediction
{(SLIP} 2005), San Francisco, CA, USA, April 2-3, 2005, Proceedings},
pages = {3},
publisher = {{ACM}},
year = {2005},
url = {https://doi.org/10.1145/1053355.1053357},
doi = {10.1145/1053355.1053357},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/Ho05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/KwonLCHT05,
author = {Young{-}Su Kwon and
Payam Lajevardi and
Anantha P. Chandrakasan and
Frank Honor{\'{e}} and
Donald E. Troxel},
editor = {Igor L. Markov and
Mike Hutton},
title = {A 3-D {FPGA} wire resource prediction model validated using a 3-D
placement and routing tool},
booktitle = {The Seventh International Workshop on System-Level Interconnect Prediction
{(SLIP} 2005), San Francisco, CA, USA, April 2-3, 2005, Proceedings},
pages = {65--72},
publisher = {{ACM}},
year = {2005},
url = {https://doi.org/10.1145/1053355.1053371},
doi = {10.1145/1053355.1053371},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/KwonLCHT05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/LanzerottiFR05,
author = {Mary Yvonne Lanzerotti and
Giovanni Fiorenza and
Rick A. Rand},
editor = {Igor L. Markov and
Mike Hutton},
title = {Predicting interconnect requirements in ultra-large-scale integrated
control logic circuitry},
booktitle = {The Seventh International Workshop on System-Level Interconnect Prediction
{(SLIP} 2005), San Francisco, CA, USA, April 2-3, 2005, Proceedings},
pages = {43--50},
publisher = {{ACM}},
year = {2005},
url = {https://doi.org/10.1145/1053355.1053366},
doi = {10.1145/1053355.1053366},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/LanzerottiFR05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/LiLCSC05,
author = {Katherine Shu{-}Min Li and
Chung{-}Len Lee and
Yao{-}Wen Chang and
Chauchin Su and
Jwu E. Chen},
editor = {Igor L. Markov and
Mike Hutton},
title = {Multilevel full-chip routing with testability and yield enhancement},
booktitle = {The Seventh International Workshop on System-Level Interconnect Prediction
{(SLIP} 2005), San Francisco, CA, USA, April 2-3, 2005, Proceedings},
pages = {29--36},
publisher = {{ACM}},
year = {2005},
url = {https://doi.org/10.1145/1053355.1053362},
doi = {10.1145/1053355.1053362},
timestamp = {Tue, 07 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/LiLCSC05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/Lienig05,
author = {Jens Lienig},
editor = {Igor L. Markov and
Mike Hutton},
title = {Interconnect and current density stress: an introduction to electromigration-aware
design},
booktitle = {The Seventh International Workshop on System-Level Interconnect Prediction
{(SLIP} 2005), San Francisco, CA, USA, April 2-3, 2005, Proceedings},
pages = {81--88},
publisher = {{ACM}},
year = {2005},
url = {https://doi.org/10.1145/1053355.1053374},
doi = {10.1145/1053355.1053374},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/Lienig05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/Nagaraj05,
author = {N. S. Nagaraj},
editor = {Igor L. Markov and
Mike Hutton},
title = {Dealing with interconnect process variations},
booktitle = {The Seventh International Workshop on System-Level Interconnect Prediction
{(SLIP} 2005), San Francisco, CA, USA, April 2-3, 2005, Proceedings},
pages = {39},
publisher = {{ACM}},
year = {2005},
url = {https://doi.org/10.1145/1053355.1053364},
doi = {10.1145/1053355.1053364},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/Nagaraj05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/NguyenC05,
author = {Viet H. Nguyen and
Phillip Christie},
editor = {Igor L. Markov and
Mike Hutton},
title = {The impact of interstratal interconnect density on the performance
of three-dimensional integrated circuits},
booktitle = {The Seventh International Workshop on System-Level Interconnect Prediction
{(SLIP} 2005), San Francisco, CA, USA, April 2-3, 2005, Proceedings},
pages = {73--78},
publisher = {{ACM}},
year = {2005},
url = {https://doi.org/10.1145/1053355.1053372},
doi = {10.1145/1053355.1053372},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/NguyenC05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/ShamY05,
author = {Chiu{-}Wing Sham and
Evangeline F. Y. Young},
editor = {Igor L. Markov and
Mike Hutton},
title = {Congestion prediction in early stages},
booktitle = {The Seventh International Workshop on System-Level Interconnect Prediction
{(SLIP} 2005), San Francisco, CA, USA, April 2-3, 2005, Proceedings},
pages = {91--98},
publisher = {{ACM}},
year = {2005},
url = {https://doi.org/10.1145/1053355.1053376},
doi = {10.1145/1053355.1053376},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/ShamY05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/UezonoIKOM05,
author = {Takumi Uezono and
Junpei Inoue and
Takanori Kyogoku and
Kenichi Okada and
Kazuya Masu},
editor = {Igor L. Markov and
Mike Hutton},
title = {Prediction of delay time for future {LSI} using on-chip transmission
line interconnects},
booktitle = {The Seventh International Workshop on System-Level Interconnect Prediction
{(SLIP} 2005), San Francisco, CA, USA, April 2-3, 2005, Proceedings},
pages = {7--12},
publisher = {{ACM}},
year = {2005},
url = {https://doi.org/10.1145/1053355.1053359},
doi = {10.1145/1053355.1053359},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/UezonoIKOM05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/WestraG05,
author = {Jurjen Westra and
Patrick Groeneveld},
editor = {Igor L. Markov and
Mike Hutton},
title = {Is probabilistic congestion estimation worthwhile?},
booktitle = {The Seventh International Workshop on System-Level Interconnect Prediction
{(SLIP} 2005), San Francisco, CA, USA, April 2-3, 2005, Proceedings},
pages = {99--106},
publisher = {{ACM}},
year = {2005},
url = {https://doi.org/10.1145/1053355.1053377},
doi = {10.1145/1053355.1053377},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/WestraG05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/slip/2005,
editor = {Igor L. Markov and
Mike Hutton},
title = {The Seventh International Workshop on System-Level Interconnect Prediction
{(SLIP} 2005), San Francisco, CA, USA, April 2-3, 2005, Proceedings},
publisher = {{ACM}},
year = {2005},
isbn = {1-59593-033-7},
timestamp = {Wed, 08 Jun 2005 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/2005.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/AhonenSBN04,
author = {Tapani Ahonen and
David A. Sig{\"{u}}enza{-}Tortosa and
Hong Bin and
Jari Nurmi},
editor = {Louis Scheffer and
Igor L. Markov},
title = {Topology optimization for application-specific networks-on-chip},
booktitle = {The Sixth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2004), Paris, France, February 14-15, 2004, Proceedings},
pages = {53--60},
publisher = {{ACM}},
year = {2004},
url = {https://doi.org/10.1145/966747.966758},
doi = {10.1145/966747.966758},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/AhonenSBN04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/BamalGSM04,
author = {Mandeep Bamal and
Evelyn Grossar and
Michele Stucchi and
Karen Maex},
editor = {Louis Scheffer and
Igor L. Markov},
title = {Interconnect width selection for deep submicron designs using the
table lookup method},
booktitle = {The Sixth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2004), Paris, France, February 14-15, 2004, Proceedings},
pages = {41--44},
publisher = {{ACM}},
year = {2004},
url = {https://doi.org/10.1145/966747.966756},
doi = {10.1145/966747.966756},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/BamalGSM04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/Bergamaschi04,
author = {Reinaldo A. Bergamaschi},
editor = {Louis Scheffer and
Igor L. Markov},
title = {Early and accurate analysis of SoCs: oxymoron or real?},
booktitle = {The Sixth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2004), Paris, France, February 14-15, 2004, Proceedings},
pages = {3--6},
publisher = {{ACM}},
year = {2004},
url = {https://doi.org/10.1145/966747.966749},
doi = {10.1145/966747.966749},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/Bergamaschi04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/ChandraXS04,
author = {Vikas Chandra and
Anthony Xu and
Herman Schmit},
editor = {Louis Scheffer and
Igor L. Markov},
title = {A low power approach to system level pipelined interconnect design},
booktitle = {The Sixth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2004), Paris, France, February 14-15, 2004, Proceedings},
pages = {45--52},
publisher = {{ACM}},
year = {2004},
url = {https://doi.org/10.1145/966747.966757},
doi = {10.1145/966747.966757},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/ChandraXS04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/Chklovskii04,
author = {Dmitri B. Chklovskii},
editor = {Louis Scheffer and
Igor L. Markov},
title = {Evolution as the blind engineer: wiring minimization in the brain},
booktitle = {The Sixth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2004), Paris, France, February 14-15, 2004, Proceedings},
pages = {63},
publisher = {{ACM}},
year = {2004},
url = {https://doi.org/10.1145/966747.966760},
doi = {10.1145/966747.966760},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/Chklovskii04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/GuptaKKS04,
author = {Puneet Gupta and
Andrew B. Kahng and
Youngmin Kim and
Dennis Sylvester},
editor = {Louis Scheffer and
Igor L. Markov},
title = {Investigation of performance metrics for interconnect stack architectures},
booktitle = {The Sixth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2004), Paris, France, February 14-15, 2004, Proceedings},
pages = {23--29},
publisher = {{ACM}},
year = {2004},
url = {https://doi.org/10.1145/966747.966753},
doi = {10.1145/966747.966753},
timestamp = {Thu, 28 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/GuptaKKS04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/JoshiD04,
author = {Ajay Joshi and
Jeffrey A. Davis},
editor = {Louis Scheffer and
Igor L. Markov},
title = {A 2-slot time-division multiplexing {(TDM)} interconnect network for
gigascale integration {(GSI)}},
booktitle = {The Sixth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2004), Paris, France, February 14-15, 2004, Proceedings},
pages = {64--68},
publisher = {{ACM}},
year = {2004},
url = {https://doi.org/10.1145/966747.966761},
doi = {10.1145/966747.966761},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/JoshiD04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/KumarT04,
author = {Arvind Kumar and
Sandip Tiwari},
editor = {Louis Scheffer and
Igor L. Markov},
title = {Defect tolerance for nanocomputer architecture},
booktitle = {The Sixth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2004), Paris, France, February 14-15, 2004, Proceedings},
pages = {89--96},
publisher = {{ACM}},
year = {2004},
url = {https://doi.org/10.1145/966747.966765},
doi = {10.1145/966747.966765},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/KumarT04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/MagenKWS04,
author = {Nir Magen and
Avinoam Kolodny and
Uri C. Weiser and
Nachum Shamir},
editor = {Louis Scheffer and
Igor L. Markov},
title = {Interconnect-power dissipation in a microprocessor},
booktitle = {The Sixth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2004), Paris, France, February 14-15, 2004, Proceedings},
pages = {7--13},
publisher = {{ACM}},
year = {2004},
url = {https://doi.org/10.1145/966747.966750},
doi = {10.1145/966747.966750},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/MagenKWS04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/MartinaM04,
author = {Maurizio Martina and
Guido Masera},
editor = {Louis Scheffer and
Igor L. Markov},
title = {A statistical model for estimating the effect of process variations
on crosstalk noise},
booktitle = {The Sixth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2004), Paris, France, February 14-15, 2004, Proceedings},
pages = {115--120},
publisher = {{ACM}},
year = {2004},
url = {https://doi.org/10.1145/966747.966769},
doi = {10.1145/966747.966769},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/MartinaM04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/OConnor04,
author = {Ian O'Connor},
editor = {Louis Scheffer and
Igor L. Markov},
title = {Optical solutions for system-level interconnect},
booktitle = {The Sixth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2004), Paris, France, February 14-15, 2004, Proceedings},
pages = {79--88},
publisher = {{ACM}},
year = {2004},
url = {https://doi.org/10.1145/966747.966764},
doi = {10.1145/966747.966764},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/OConnor04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/OngSYMDL04,
author = {Beng Hwee Ong and
Choon Beng Sia and
Kiat Seng Yeo and
Jianguo Ma and
Manh Anh Do and
Erping Li},
editor = {Louis Scheffer and
Igor L. Markov},
title = {Investigating the frequency dependence elements of {CMOS} {RFIC} interconnects
for physical modeling},
booktitle = {The Sixth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2004), Paris, France, February 14-15, 2004, Proceedings},
pages = {31--38},
publisher = {{ACM}},
year = {2004},
url = {https://doi.org/10.1145/966747.966754},
doi = {10.1145/966747.966754},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/OngSYMDL04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/RajendranKSFP04,
author = {Bipin Rajendran and
Pawan Kapur and
Krishna Saraswat and
R. Fabian W. Pease},
editor = {Louis Scheffer and
Igor L. Markov},
title = {Self-consistent power/performance/reliability analysis for copper
interconnects},
booktitle = {The Sixth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2004), Paris, France, February 14-15, 2004, Proceedings},
pages = {17--22},
publisher = {{ACM}},
year = {2004},
url = {https://doi.org/10.1145/966747.966752},
doi = {10.1145/966747.966752},
timestamp = {Mon, 29 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/RajendranKSFP04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/VenkatramanLJKZB04,
author = {Vishak Venkatraman and
Andrew Laffely and
Jinwook Jang and
Hempraveen Kukkamalla and
Zhi Zhu and
Wayne P. Burleson},
editor = {Louis Scheffer and
Igor L. Markov},
title = {NoCIC: a spice-based interconnect planning tool emphasizing aggressive
on-chip interconnect circuit methods},
booktitle = {The Sixth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2004), Paris, France, February 14-15, 2004, Proceedings},
pages = {69--75},
publisher = {{ACM}},
year = {2004},
url = {https://doi.org/10.1145/966747.966762},
doi = {10.1145/966747.966762},
timestamp = {Mon, 06 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/VenkatramanLJKZB04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/WanC04,
author = {Tao Wan and
Malgorzata Chrzanowska{-}Jeske},
editor = {Louis Scheffer and
Igor L. Markov},
title = {Prediction of interconnect net-degree distribution based on Rent's
rule},
booktitle = {The Sixth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2004), Paris, France, February 14-15, 2004, Proceedings},
pages = {107--114},
publisher = {{ACM}},
year = {2004},
url = {https://doi.org/10.1145/966747.966768},
doi = {10.1145/966747.966768},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/WanC04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/Zarkesh-HaDLB04,
author = {Payman Zarkesh{-}Ha and
Ken Doniger and
William Loh and
Peter Bendix},
editor = {Louis Scheffer and
Igor L. Markov},
title = {Prediction of interconnect adjacency distribution: derivation, validation,
and applications},
booktitle = {The Sixth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2004), Paris, France, February 14-15, 2004, Proceedings},
pages = {99--106},
publisher = {{ACM}},
year = {2004},
url = {https://doi.org/10.1145/966747.966767},
doi = {10.1145/966747.966767},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/Zarkesh-HaDLB04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/slip/2004,
editor = {Louis Scheffer and
Igor L. Markov},
title = {The Sixth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2004), Paris, France, February 14-15, 2004, Proceedings},
publisher = {{ACM}},
year = {2004},
isbn = {1-58113-818-0},
timestamp = {Fri, 03 Sep 2004 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/2004.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/AnbalaganD03,
author = {Pranav Anbalagan and
Jeffrey A. Davis},
editor = {Dennis Sylvester and
Dirk Stroobandt and
Louis Scheffer and
Payman Zarkesh{-}Ha},
title = {Maximum multiplicity distributions {(MMD)}},
booktitle = {The 5th International Workshop on System-Level Interconnect Prediction
{(SLIP} 2003), Monterey, CA, USA, April 5-6, 2003, Proceedings},
pages = {107--113},
publisher = {{ACM}},
year = {2003},
url = {https://doi.org/10.1145/639929.639951},
doi = {10.1145/639929.639951},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/AnbalaganD03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/AndersonN03,
author = {Jason Helge Anderson and
Farid N. Najm},
editor = {Dennis Sylvester and
Dirk Stroobandt and
Louis Scheffer and
Payman Zarkesh{-}Ha},
title = {Switching activity analysis and pre-layout activity prediction for
FPGAs},
booktitle = {The 5th International Workshop on System-Level Interconnect Prediction
{(SLIP} 2003), Monterey, CA, USA, April 5-6, 2003, Proceedings},
pages = {15--21},
publisher = {{ACM}},
year = {2003},
url = {https://doi.org/10.1145/639929.639934},
doi = {10.1145/639929.639934},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/AndersonN03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/BalachandranB03,
author = {Shankar Balachandran and
Dinesh Bhatia},
editor = {Dennis Sylvester and
Dirk Stroobandt and
Louis Scheffer and
Payman Zarkesh{-}Ha},
title = {A-priori wirelength and interconnect estimation based on circuit characteristics},
booktitle = {The 5th International Workshop on System-Level Interconnect Prediction
{(SLIP} 2003), Monterey, CA, USA, April 5-6, 2003, Proceedings},
pages = {77--84},
publisher = {{ACM}},
year = {2003},
url = {https://doi.org/10.1145/639929.639945},
doi = {10.1145/639929.639945},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/BalachandranB03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/Bennebroek03,
author = {Martijn T. Bennebroek},
editor = {Dennis Sylvester and
Dirk Stroobandt and
Louis Scheffer and
Payman Zarkesh{-}Ha},
title = {Validation of wire length distribution models on commercial designs},
booktitle = {The 5th International Workshop on System-Level Interconnect Prediction
{(SLIP} 2003), Monterey, CA, USA, April 5-6, 2003, Proceedings},
pages = {41},
publisher = {{ACM}},
year = {2003},
url = {https://doi.org/10.1145/639929.639938},
doi = {10.1145/639929.639938},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/Bennebroek03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/ChenCKMW03,
author = {Hongyu Chen and
Chung{-}Kuan Cheng and
Andrew B. Kahng and
Ion I. Mandoiu and
Qinke Wang},
editor = {Dennis Sylvester and
Dirk Stroobandt and
Louis Scheffer and
Payman Zarkesh{-}Ha},
title = {Estimation of wirelength reduction for lambda-geometry vs. manhattan
placement and routing},
booktitle = {The 5th International Workshop on System-Level Interconnect Prediction
{(SLIP} 2003), Monterey, CA, USA, April 5-6, 2003, Proceedings},
pages = {71--76},
publisher = {{ACM}},
year = {2003},
url = {https://doi.org/10.1145/639929.639944},
doi = {10.1145/639929.639944},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/ChenCKMW03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/Chiprout03,
author = {Eli Chiprout},
editor = {Dennis Sylvester and
Dirk Stroobandt and
Louis Scheffer and
Payman Zarkesh{-}Ha},
title = {Early electrical wire projections and implications},
booktitle = {The 5th International Workshop on System-Level Interconnect Prediction
{(SLIP} 2003), Monterey, CA, USA, April 5-6, 2003, Proceedings},
pages = {95},
publisher = {{ACM}},
year = {2003},
url = {https://doi.org/10.1145/639929.639948},
doi = {10.1145/639929.639948},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/Chiprout03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/DambreSC03,
author = {Joni Dambre and
Dirk Stroobandt and
Jan Van Campenhout},
editor = {Dennis Sylvester and
Dirk Stroobandt and
Louis Scheffer and
Payman Zarkesh{-}Ha},
title = {Fast estimation of the partitioning rent characteristic using a recursive
partitioning model},
booktitle = {The 5th International Workshop on System-Level Interconnect Prediction
{(SLIP} 2003), Monterey, CA, USA, April 5-6, 2003, Proceedings},
pages = {45--52},
publisher = {{ACM}},
year = {2003},
url = {https://doi.org/10.1145/639929.639940},
doi = {10.1145/639929.639940},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/DambreSC03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/KahngX03,
author = {Andrew B. Kahng and
Xu Xu},
editor = {Dennis Sylvester and
Dirk Stroobandt and
Louis Scheffer and
Payman Zarkesh{-}Ha},
title = {Accurate pseudo-constructive wirelength and congestion estimation},
booktitle = {The 5th International Workshop on System-Level Interconnect Prediction
{(SLIP} 2003), Monterey, CA, USA, April 5-6, 2003, Proceedings},
pages = {61--68},
publisher = {{ACM}},
year = {2003},
url = {https://doi.org/10.1145/639929.639942},
doi = {10.1145/639929.639942},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/KahngX03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/KravetsK03,
author = {Victor N. Kravets and
Prabhakar Kudva},
editor = {Dennis Sylvester and
Dirk Stroobandt and
Louis Scheffer and
Payman Zarkesh{-}Ha},
title = {Understanding metrics in logic synthesis for routability enhancement},
booktitle = {The 5th International Workshop on System-Level Interconnect Prediction
{(SLIP} 2003), Monterey, CA, USA, April 5-6, 2003, Proceedings},
pages = {3--5},
publisher = {{ACM}},
year = {2003},
url = {https://doi.org/10.1145/639929.639931},
doi = {10.1145/639929.639931},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/KravetsK03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/LiuHM03,
author = {Qinghua Liu and
Bo Hu and
Malgorzata Marek{-}Sadowska},
editor = {Dennis Sylvester and
Dirk Stroobandt and
Louis Scheffer and
Payman Zarkesh{-}Ha},
title = {Wire length prediction in constraint driven placement},
booktitle = {The 5th International Workshop on System-Level Interconnect Prediction
{(SLIP} 2003), Monterey, CA, USA, April 5-6, 2003, Proceedings},
pages = {99--105},
publisher = {{ACM}},
year = {2003},
url = {https://doi.org/10.1145/639929.639950},
doi = {10.1145/639929.639950},
timestamp = {Wed, 11 Sep 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/LiuHM03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/LiuSZT03,
author = {Jian Liu and
Meigen Shen and
Li{-}Rong Zheng and
Hannu Tenhunen},
editor = {Dennis Sylvester and
Dirk Stroobandt and
Louis Scheffer and
Payman Zarkesh{-}Ha},
title = {System level interconnect design for network-on-chip using interconnect
IPs},
booktitle = {The 5th International Workshop on System-Level Interconnect Prediction
{(SLIP} 2003), Monterey, CA, USA, April 5-6, 2003, Proceedings},
pages = {117--124},
publisher = {{ACM}},
year = {2003},
url = {https://doi.org/10.1145/639929.639953},
doi = {10.1145/639929.639953},
timestamp = {Thu, 04 Apr 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/LiuSZT03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/PapanikolaouMCCMRSM03,
author = {Antonis Papanikolaou and
Miguel Miranda and
Francky Catthoor and
Henk Corporaal and
Hugo De Man and
David De Roest and
Michele Stucchi and
Karen Maex},
editor = {Dennis Sylvester and
Dirk Stroobandt and
Louis Scheffer and
Payman Zarkesh{-}Ha},
title = {Global interconnect trade-off for technology over memory modules to
application level: case study},
booktitle = {The 5th International Workshop on System-Level Interconnect Prediction
{(SLIP} 2003), Monterey, CA, USA, April 5-6, 2003, Proceedings},
pages = {125--132},
publisher = {{ACM}},
year = {2003},
url = {https://doi.org/10.1145/639929.639954},
doi = {10.1145/639929.639954},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/PapanikolaouMCCMRSM03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/PatelM03,
author = {Ketan N. Patel and
Igor L. Markov},
editor = {Dennis Sylvester and
Dirk Stroobandt and
Louis Scheffer and
Payman Zarkesh{-}Ha},
title = {Error-correction and crosstalk avoidance in {DSM} busses},
booktitle = {The 5th International Workshop on System-Level Interconnect Prediction
{(SLIP} 2003), Monterey, CA, USA, April 5-6, 2003, Proceedings},
pages = {9--14},
publisher = {{ACM}},
year = {2003},
url = {https://doi.org/10.1145/639929.639933},
doi = {10.1145/639929.639933},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/PatelM03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/PistoriusH03,
author = {Joachim Pistorius and
Mike Hutton},
editor = {Dennis Sylvester and
Dirk Stroobandt and
Louis Scheffer and
Payman Zarkesh{-}Ha},
title = {Placement rent exponent calculation methods, temporal behaviour and
{FPGA} architecture evaluation},
booktitle = {The 5th International Workshop on System-Level Interconnect Prediction
{(SLIP} 2003), Monterey, CA, USA, April 5-6, 2003, Proceedings},
pages = {31--38},
publisher = {{ACM}},
year = {2003},
url = {https://doi.org/10.1145/639929.639936},
doi = {10.1145/639929.639936},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/PistoriusH03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/SelvakkumaranPK03,
author = {Navaratnasothie Selvakkumaran and
Phiroze N. Parakh and
George Karypis},
editor = {Dennis Sylvester and
Dirk Stroobandt and
Louis Scheffer and
Payman Zarkesh{-}Ha},
title = {Perimeter-degree: a priori metric for directly measuring and homogenizing
interconnection complexity in multilevel placement},
booktitle = {The 5th International Workshop on System-Level Interconnect Prediction
{(SLIP} 2003), Monterey, CA, USA, April 5-6, 2003, Proceedings},
pages = {53--59},
publisher = {{ACM}},
year = {2003},
url = {https://doi.org/10.1145/639929.639941},
doi = {10.1145/639929.639941},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/SelvakkumaranPK03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/YehM03,
author = {Chao{-}Yang Yeh and
Malgorzata Marek{-}Sadowska},
editor = {Dennis Sylvester and
Dirk Stroobandt and
Louis Scheffer and
Payman Zarkesh{-}Ha},
title = {Sequential delay budgeting with interconnect prediction},
booktitle = {The 5th International Workshop on System-Level Interconnect Prediction
{(SLIP} 2003), Monterey, CA, USA, April 5-6, 2003, Proceedings},
pages = {23--30},
publisher = {{ACM}},
year = {2003},
url = {https://doi.org/10.1145/639929.639935},
doi = {10.1145/639929.639935},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/YehM03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/Zarkesh-HaDLW03,
author = {Payman Zarkesh{-}Ha and
Ken Doniger and
William Loh and
Peter Wright},
editor = {Dennis Sylvester and
Dirk Stroobandt and
Louis Scheffer and
Payman Zarkesh{-}Ha},
title = {Prediction of interconnect pattern density distribution: derivation,
validation, and applications},
booktitle = {The 5th International Workshop on System-Level Interconnect Prediction
{(SLIP} 2003), Monterey, CA, USA, April 5-6, 2003, Proceedings},
pages = {85--91},
publisher = {{ACM}},
year = {2003},
url = {https://doi.org/10.1145/639929.639946},
doi = {10.1145/639929.639946},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/Zarkesh-HaDLW03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/ZhouCYCG03,
author = {Feng Zhou and
Esther Y. Cheng and
Bo Yao and
Chung{-}Kuan Cheng and
Ronald L. Graham},
editor = {Dennis Sylvester and
Dirk Stroobandt and
Louis Scheffer and
Payman Zarkesh{-}Ha},
title = {A hierarchical three-way interconnect architecture for hexagonal processors},
booktitle = {The 5th International Workshop on System-Level Interconnect Prediction
{(SLIP} 2003), Monterey, CA, USA, April 5-6, 2003, Proceedings},
pages = {133--139},
publisher = {{ACM}},
year = {2003},
url = {https://doi.org/10.1145/639929.639955},
doi = {10.1145/639929.639955},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/ZhouCYCG03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/slip/2003,
editor = {Dennis Sylvester and
Dirk Stroobandt and
Louis Scheffer and
Payman Zarkesh{-}Ha},
title = {The 5th International Workshop on System-Level Interconnect Prediction
{(SLIP} 2003), Monterey, CA, USA, April 5-6, 2003, Proceedings},
publisher = {{ACM}},
year = {2003},
isbn = {1-58113-627-7},
timestamp = {Wed, 09 Feb 2005 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/2003.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/BecerBHP02,
author = {Murat R. Becer and
David T. Blaauw and
Ibrahim N. Hajj and
Rajendran Panda},
title = {Early probabilistic noise estimation for capacitively coupled interconnects},
booktitle = {The Fourth {IEEE/ACM} International Workshop on System-Level Interconnect
Prediction {(SLIP} 2002), April 6-7, 2002, San Diego, California,
USA, Proceedings},
pages = {77--83},
publisher = {{ACM}},
year = {2002},
url = {https://doi.org/10.1145/505348.505365},
doi = {10.1145/505348.505365},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/BecerBHP02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/ChenQZC02,
author = {Hongyu Chen and
Changge Qiao and
Feng Zhou and
Chung{-}Kuan Cheng},
title = {Refined single trunk tree: a rectilinear steiner tree generator for
interconnect prediction},
booktitle = {The Fourth {IEEE/ACM} International Workshop on System-Level Interconnect
Prediction {(SLIP} 2002), April 6-7, 2002, San Diego, California,
USA, Proceedings},
pages = {85--89},
publisher = {{ACM}},
year = {2002},
url = {https://doi.org/10.1145/505348.505366},
doi = {10.1145/505348.505366},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/ChenQZC02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/DambreVSC02,
author = {Joni Dambre and
Peter Verplaetse and
Dirk Stroobandt and
Jan Van Campenhout},
title = {Getting more out of Donath's hierarchical model for interconnect prediction},
booktitle = {The Fourth {IEEE/ACM} International Workshop on System-Level Interconnect
Prediction {(SLIP} 2002), April 6-7, 2002, San Diego, California,
USA, Proceedings},
pages = {9--16},
publisher = {{ACM}},
year = {2002},
url = {https://doi.org/10.1145/505348.505351},
doi = {10.1145/505348.505351},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/DambreVSC02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/IqbalSHC02,
author = {Muzammil Iqbal and
Ahmed Sharkawy and
Usman Hameed and
Phillip Christie},
title = {Stochastic wire length sampling for cycle time estimation},
booktitle = {The Fourth {IEEE/ACM} International Workshop on System-Level Interconnect
Prediction {(SLIP} 2002), April 6-7, 2002, San Diego, California,
USA, Proceedings},
pages = {91--96},
publisher = {{ACM}},
year = {2002},
url = {https://doi.org/10.1145/505348.505367},
doi = {10.1145/505348.505367},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/IqbalSHC02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/KrufkaC02,
author = {Stephen E. Krufka and
Phillip Christie},
title = {Terminal optimization analysis for functional block re-use},
booktitle = {The Fourth {IEEE/ACM} International Workshop on System-Level Interconnect
Prediction {(SLIP} 2002), April 6-7, 2002, San Diego, California,
USA, Proceedings},
pages = {3--8},
publisher = {{ACM}},
year = {2002},
url = {https://doi.org/10.1145/505348.505350},
doi = {10.1145/505348.505350},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/KrufkaC02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/MezhibaF02,
author = {Andrey V. Mezhiba and
Eby G. Friedman},
title = {Scaling trends of on-chip Power distribution noise},
booktitle = {The Fourth {IEEE/ACM} International Workshop on System-Level Interconnect
Prediction {(SLIP} 2002), April 6-7, 2002, San Diego, California,
USA, Proceedings},
pages = {47--53},
publisher = {{ACM}},
year = {2002},
url = {https://doi.org/10.1145/505348.505359},
doi = {10.1145/505348.505359},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/MezhibaF02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/Muddu02,
author = {Sudhakar Muddu},
title = {Estimation needs for future networking systems interconnect},
booktitle = {The Fourth {IEEE/ACM} International Workshop on System-Level Interconnect
Prediction {(SLIP} 2002), April 6-7, 2002, San Diego, California,
USA, Proceedings},
pages = {41--44},
publisher = {{ACM}},
year = {2002},
url = {https://doi.org/10.1145/505348.505357},
doi = {10.1145/505348.505357},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/Muddu02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/NassifF02,
author = {Sani R. Nassif and
Onsi Fakhouri},
title = {Technology trends in power-grid-induced noise},
booktitle = {The Fourth {IEEE/ACM} International Workshop on System-Level Interconnect
Prediction {(SLIP} 2002), April 6-7, 2002, San Diego, California,
USA, Proceedings},
pages = {55--59},
publisher = {{ACM}},
year = {2002},
url = {https://doi.org/10.1145/505348.505360},
doi = {10.1145/505348.505360},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/NassifF02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/PapanikolaouMCCMRSM02,
author = {Antonis Papanikolaou and
Miguel Miranda and
Francky Catthoor and
Henk Corporaal and
Hugo De Man and
David De Roest and
Michele Stucchi and
Karen Maex},
title = {Interconnect exploration for future wire dominated technologies},
booktitle = {The Fourth {IEEE/ACM} International Workshop on System-Level Interconnect
Prediction {(SLIP} 2002), April 6-7, 2002, San Diego, California,
USA, Proceedings},
pages = {105--106},
publisher = {{ACM}},
year = {2002},
url = {https://doi.org/10.1145/505348.505370},
doi = {10.1145/505348.505370},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/PapanikolaouMCCMRSM02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/ShinEES02,
author = {Seongkyun Shin and
Yungseon Eo and
William R. Eisenstadt and
Jongin Shim},
title = {Analytical signal integrity verification models for inductance-dominant
multi-coupled {VLSI} interconnects},
booktitle = {The Fourth {IEEE/ACM} International Workshop on System-Level Interconnect
Prediction {(SLIP} 2002), April 6-7, 2002, San Diego, California,
USA, Proceedings},
pages = {61--68},
publisher = {{ACM}},
year = {2002},
url = {https://doi.org/10.1145/505348.505361},
doi = {10.1145/505348.505361},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/ShinEES02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/SinghM02,
author = {Amit Singh and
Malgorzata Marek{-}Sadowska},
title = {{FPGA} interconnect planning},
booktitle = {The Fourth {IEEE/ACM} International Workshop on System-Level Interconnect
Prediction {(SLIP} 2002), April 6-7, 2002, San Diego, California,
USA, Proceedings},
pages = {23--30},
publisher = {{ACM}},
year = {2002},
url = {https://doi.org/10.1145/505348.505353},
doi = {10.1145/505348.505353},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/SinghM02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/Teig02,
author = {Steven L. Teig},
title = {The {X} architecture: not your father's diagonal wiring},
booktitle = {The Fourth {IEEE/ACM} International Workshop on System-Level Interconnect
Prediction {(SLIP} 2002), April 6-7, 2002, San Diego, California,
USA, Proceedings},
pages = {33--37},
publisher = {{ACM}},
year = {2002},
url = {https://doi.org/10.1145/505348.505355},
doi = {10.1145/505348.505355},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/Teig02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/VerbauwhedeC02,
author = {Ingrid Verbauwhede and
M.{-}C. Frank Chang},
title = {Reconfigurable interconnect for next generation systems},
booktitle = {The Fourth {IEEE/ACM} International Workshop on System-Level Interconnect
Prediction {(SLIP} 2002), April 6-7, 2002, San Diego, California,
USA, Proceedings},
pages = {71--74},
publisher = {{ACM}},
year = {2002},
url = {https://doi.org/10.1145/505348.505363},
doi = {10.1145/505348.505363},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/VerbauwhedeC02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/WildmanKWC02,
author = {Raymond A. Wildman and
Joshua I. Kramer and
Daniel S. Weile and
Phillip Christie},
title = {Wire layer geometry optimization using stochastic wire sampling},
booktitle = {The Fourth {IEEE/ACM} International Workshop on System-Level Interconnect
Prediction {(SLIP} 2002), April 6-7, 2002, San Diego, California,
USA, Proceedings},
pages = {97--102},
publisher = {{ACM}},
year = {2002},
url = {https://doi.org/10.1145/505348.505368},
doi = {10.1145/505348.505368},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/WildmanKWC02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/ZhangS02,
author = {Tianpei Zhang and
Sachin S. Sapatnekar},
title = {Optimized pin assignment for lower routing congestion after floorplanning
phase},
booktitle = {The Fourth {IEEE/ACM} International Workshop on System-Level Interconnect
Prediction {(SLIP} 2002), April 6-7, 2002, San Diego, California,
USA, Proceedings},
pages = {17--21},
publisher = {{ACM}},
year = {2002},
url = {https://doi.org/10.1145/505348.505352},
doi = {10.1145/505348.505352},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/ZhangS02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/slip/2002,
title = {The Fourth {IEEE/ACM} International Workshop on System-Level Interconnect
Prediction {(SLIP} 2002), April 6-7, 2002, San Diego, California,
USA, Proceedings},
publisher = {{ACM}},
year = {2002},
timestamp = {Thu, 21 Jun 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/2002.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/BoeseKM01,
author = {Kenneth D. Boese and
Andrew B. Kahng and
Stefanus Mantik},
title = {On the relevance of wire load models},
booktitle = {The Third {IEEE/ACM} International Workshop on System-Level Interconnect
Prediction {(SLIP} 2001), March 31 - April 1, 2001, DoubleTree Hotel,
Rohnert Park, CA, USA, Proceedings},
pages = {91--98},
publisher = {{ACM}},
year = {2001},
url = {https://doi.org/10.1145/368640.368719},
doi = {10.1145/368640.368719},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/BoeseKM01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/ChengKL01,
author = {Chung{-}Kuan Cheng and
Andrew B. Kahng and
Bao Liu},
title = {Interconnect implications of growth-based structural models for {VLSI}
circuits},
booktitle = {The Third {IEEE/ACM} International Workshop on System-Level Interconnect
Prediction {(SLIP} 2001), March 31 - April 1, 2001, DoubleTree Hotel,
Rohnert Park, CA, USA, Proceedings},
pages = {99--106},
publisher = {{ACM}},
year = {2001},
url = {https://doi.org/10.1145/368640.368730},
doi = {10.1145/368640.368730},
timestamp = {Thu, 21 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/ChengKL01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/ChristieG01,
author = {Phillip Christie and
Jos{\'{e}} Pineda de Gyvez},
title = {Pre-layout prediction of interconnect manufacturability},
booktitle = {The Third {IEEE/ACM} International Workshop on System-Level Interconnect
Prediction {(SLIP} 2001), March 31 - April 1, 2001, DoubleTree Hotel,
Rohnert Park, CA, USA, Proceedings},
pages = {167--173},
publisher = {{ACM}},
year = {2001},
url = {https://doi.org/10.1145/368640.368826},
doi = {10.1145/368640.368826},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/ChristieG01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/DambreVSC01,
author = {Joni Dambre and
Peter Verplaetse and
Dirk Stroobandt and
Jan Van Campenhout},
title = {On rent's rule for rectangular regions},
booktitle = {The Third {IEEE/ACM} International Workshop on System-Level Interconnect
Prediction {(SLIP} 2001), March 31 - April 1, 2001, DoubleTree Hotel,
Rohnert Park, CA, USA, Proceedings},
pages = {49--56},
publisher = {{ACM}},
year = {2001},
url = {https://doi.org/10.1145/368640.368700},
doi = {10.1145/368640.368700},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/DambreVSC01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/DeHon01,
author = {Andr{\'{e}} DeHon},
title = {Rent's rule based switching requirements},
booktitle = {The Third {IEEE/ACM} International Workshop on System-Level Interconnect
Prediction {(SLIP} 2001), March 31 - April 1, 2001, DoubleTree Hotel,
Rohnert Park, CA, USA, Proceedings},
pages = {197--204},
publisher = {{ACM}},
year = {2001},
url = {https://doi.org/10.1145/368640.368870},
doi = {10.1145/368640.368870},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/DeHon01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/GrazianoMPZ01,
author = {Mariagrazia Graziano and
Guido Masera and
Gianluca Piccinini and
Maurizio Zamboni},
title = {Hierarchical power supply noise evaluation for early power grid design
prediction},
booktitle = {The Third {IEEE/ACM} International Workshop on System-Level Interconnect
Prediction {(SLIP} 2001), March 31 - April 1, 2001, DoubleTree Hotel,
Rohnert Park, CA, USA, Proceedings},
pages = {183--188},
publisher = {{ACM}},
year = {2001},
url = {https://doi.org/10.1145/368640.368845},
doi = {10.1145/368640.368845},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/GrazianoMPZ01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/Gyvez01,
author = {Jos{\'{e}} Pineda de Gyvez},
title = {Yield modeling and {BEOL} fundamentals},
booktitle = {The Third {IEEE/ACM} International Workshop on System-Level Interconnect
Prediction {(SLIP} 2001), March 31 - April 1, 2001, DoubleTree Hotel,
Rohnert Park, CA, USA, Proceedings},
pages = {135--163},
publisher = {{ACM}},
year = {2001},
url = {https://doi.org/10.1145/368640.368821},
doi = {10.1145/368640.368821},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/Gyvez01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/Huang01,
author = {Shih{-}Hsu Huang},
title = {An effective low power design methodology based on interconnect prediction},
booktitle = {The Third {IEEE/ACM} International Workshop on System-Level Interconnect
Prediction {(SLIP} 2001), March 31 - April 1, 2001, DoubleTree Hotel,
Rohnert Park, CA, USA, Proceedings},
pages = {189--194},
publisher = {{ACM}},
year = {2001},
url = {https://doi.org/10.1145/368640.368849},
doi = {10.1145/368640.368849},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/Huang01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/Hutton01,
author = {Michael D. Hutton},
title = {Interconnect prediction for programmable logic devices},
booktitle = {The Third {IEEE/ACM} International Workshop on System-Level Interconnect
Prediction {(SLIP} 2001), March 31 - April 1, 2001, DoubleTree Hotel,
Rohnert Park, CA, USA, Proceedings},
pages = {125--131},
publisher = {{ACM}},
year = {2001},
url = {https://doi.org/10.1145/368640.368816},
doi = {10.1145/368640.368816},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/Hutton01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/MaH01,
author = {James D. Z. Ma and
Lei He},
title = {Simultaneous signal and power routing under {K} model},
booktitle = {The Third {IEEE/ACM} International Workshop on System-Level Interconnect
Prediction {(SLIP} 2001), March 31 - April 1, 2001, DoubleTree Hotel,
Rohnert Park, CA, USA, Proceedings},
pages = {175--182},
publisher = {{ACM}},
year = {2001},
url = {https://doi.org/10.1145/368640.368841},
doi = {10.1145/368640.368841},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/MaH01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/OttenG01,
author = {Ralph H. J. M. Otten and
Giuseppe S. Garcea},
title = {Are wires plannable?},
booktitle = {The Third {IEEE/ACM} International Workshop on System-Level Interconnect
Prediction {(SLIP} 2001), March 31 - April 1, 2001, DoubleTree Hotel,
Rohnert Park, CA, USA, Proceedings},
pages = {59--66},
publisher = {{ACM}},
year = {2001},
url = {https://doi.org/10.1145/368640.368707},
doi = {10.1145/368640.368707},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/OttenG01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/ParthasarathyMMS01,
author = {Ganapathy Parthasarathy and
Malgorzata Marek{-}Sadowska and
Arindam Mukherjee and
Amit Singh},
title = {Interconnect complexity-aware {FPGA} placement using Rent's rule},
booktitle = {The Third {IEEE/ACM} International Workshop on System-Level Interconnect
Prediction {(SLIP} 2001), March 31 - April 1, 2001, DoubleTree Hotel,
Rohnert Park, CA, USA, Proceedings},
pages = {115--121},
publisher = {{ACM}},
year = {2001},
url = {https://doi.org/10.1145/368640.368806},
doi = {10.1145/368640.368806},
timestamp = {Mon, 05 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/ParthasarathyMMS01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/RahmanDCR01,
author = {Arifur Rahman and
Shamik Das and
Anantha P. Chandrakasan and
Rafael Reif},
title = {Wiring requirement and three-dimensional integration of field-programmable
gate arrays},
booktitle = {The Third {IEEE/ACM} International Workshop on System-Level Interconnect
Prediction {(SLIP} 2001), March 31 - April 1, 2001, DoubleTree Hotel,
Rohnert Park, CA, USA, Proceedings},
pages = {107--113},
publisher = {{ACM}},
year = {2001},
url = {https://doi.org/10.1145/368640.368739},
doi = {10.1145/368640.368739},
timestamp = {Mon, 27 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/RahmanDCR01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/Rose01,
author = {Kenneth Rose},
title = {A comprehensive look at system level model},
booktitle = {The Third {IEEE/ACM} International Workshop on System-Level Interconnect
Prediction {(SLIP} 2001), March 31 - April 1, 2001, DoubleTree Hotel,
Rohnert Park, CA, USA, Proceedings},
pages = {69--87},
publisher = {{ACM}},
year = {2001},
url = {https://doi.org/10.1145/368640.368715},
doi = {10.1145/368640.368715},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/Rose01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/Stoobandt01,
author = {Dirk Stroobandt},
title = {Multi-terminal nets do change conventional wire length distribution
models},
booktitle = {The Third {IEEE/ACM} International Workshop on System-Level Interconnect
Prediction {(SLIP} 2001), March 31 - April 1, 2001, DoubleTree Hotel,
Rohnert Park, CA, USA, Proceedings},
pages = {41--48},
publisher = {{ACM}},
year = {2001},
url = {https://doi.org/10.1145/368640.368679},
doi = {10.1145/368640.368679},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/Stoobandt01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/Stroobandt01,
author = {Dirk Stroobandt},
title = {A priori system-level interconnect prediction: Rent's rule and wire
length distribution models},
booktitle = {The Third {IEEE/ACM} International Workshop on System-Level Interconnect
Prediction {(SLIP} 2001), March 31 - April 1, 2001, DoubleTree Hotel,
Rohnert Park, CA, USA, Proceedings},
pages = {3--21},
publisher = {{ACM}},
year = {2001},
url = {https://doi.org/10.1145/368640.368645},
doi = {10.1145/368640.368645},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/Stroobandt01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/VerplaetseDSC01,
author = {Peter Verplaetse and
Joni Dambre and
Dirk Stroobandt and
Jan Van Campenhout},
title = {On partitioning vs. placement rent properties},
booktitle = {The Third {IEEE/ACM} International Workshop on System-Level Interconnect
Prediction {(SLIP} 2001), March 31 - April 1, 2001, DoubleTree Hotel,
Rohnert Park, CA, USA, Proceedings},
pages = {33--40},
publisher = {{ACM}},
year = {2001},
url = {https://doi.org/10.1145/368640.368665},
doi = {10.1145/368640.368665},
timestamp = {Wed, 14 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/VerplaetseDSC01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/YangBS01,
author = {Xiaojian Yang and
Elaheh Bozorgzadeh and
Majid Sarrafzadeh},
title = {Wirelength estimation based on rent exponents of partitioning and
placement},
booktitle = {The Third {IEEE/ACM} International Workshop on System-Level Interconnect
Prediction {(SLIP} 2001), March 31 - April 1, 2001, DoubleTree Hotel,
Rohnert Park, CA, USA, Proceedings},
pages = {25--31},
publisher = {{ACM}},
year = {2001},
url = {https://doi.org/10.1145/368640.368658},
doi = {10.1145/368640.368658},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/YangBS01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/slip/2001,
title = {The Third {IEEE/ACM} International Workshop on System-Level Interconnect
Prediction {(SLIP} 2001), March 31 - April 1, 2001, DoubleTree Hotel,
Rohnert Park, CA, USA, Proceedings},
publisher = {{ACM}},
year = {2001},
timestamp = {Mon, 21 Oct 2002 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/2001.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/BodapatiN00,
author = {Srinivas Bodapati and
Farid N. Najm},
title = {Pre-layout estimation of individual wire lengths},
booktitle = {The Second {IEEE/ACM} International Workshop on System-Level Interconnect
Prediction {(SLIP} 2000), April 8-9, 2000, San Diego, California,
USA, Proceedings},
pages = {93--98},
publisher = {{ACM}},
year = {2000},
url = {https://doi.org/10.1145/333032.333038},
doi = {10.1145/333032.333038},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/BodapatiN00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/Christie00,
author = {Phillip Christie},
title = {Managing interconnect resources (tutorial)},
booktitle = {The Second {IEEE/ACM} International Workshop on System-Level Interconnect
Prediction {(SLIP} 2000), April 8-9, 2000, San Diego, California,
USA, Proceedings},
pages = {1--51},
publisher = {{ACM}},
year = {2000},
url = {https://doi.org/10.1145/333032.333139},
doi = {10.1145/333032.333139},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/Christie00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/DavisVBM00,
author = {Jeffrey A. Davis and
Raguraman Venkatesan and
Keith A. Bowman and
James D. Meindl},
title = {Gigascale integration {(GSI)} interconnect limits and n-tier multilevel
interconnect architectural solutions (discussion session)},
booktitle = {The Second {IEEE/ACM} International Workshop on System-Level Interconnect
Prediction {(SLIP} 2000), April 8-9, 2000, San Diego, California,
USA, Proceedings},
pages = {147--148},
publisher = {{ACM}},
year = {2000},
url = {https://doi.org/10.1145/333032.333045},
doi = {10.1145/333032.333045},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/DavisVBM00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/DeschachtSHPK00,
author = {Denis Deschacht and
Gr{\'{e}}gory Servel and
Fabrice Huret and
Erick Paleczny and
Patrick Kennis},
title = {Theoretical limits for signal reflections due to inductance for on-chip
interconnections},
booktitle = {The Second {IEEE/ACM} International Workshop on System-Level Interconnect
Prediction {(SLIP} 2000), April 8-9, 2000, San Diego, California,
USA, Proceedings},
pages = {55--60},
publisher = {{ACM}},
year = {2000},
url = {https://doi.org/10.1145/333032.333033},
doi = {10.1145/333032.333033},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/DeschachtSHPK00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/DhaouT00,
author = {Imed Ben Dhaou and
Hannu Tenhunen},
title = {Energy efficient high-speed on-chip signaling in deep-submicron {CMOS}
technology},
booktitle = {The Second {IEEE/ACM} International Workshop on System-Level Interconnect
Prediction {(SLIP} 2000), April 8-9, 2000, San Diego, California,
USA, Proceedings},
pages = {69--76},
publisher = {{ACM}},
year = {2000},
url = {https://doi.org/10.1145/333032.333035},
doi = {10.1145/333032.333035},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/DhaouT00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/Farrahi00,
author = {Amir H. Farrahi},
title = {Estimation and removal or routing congestion (discussion session)},
booktitle = {The Second {IEEE/ACM} International Workshop on System-Level Interconnect
Prediction {(SLIP} 2000), April 8-9, 2000, San Diego, California,
USA, Proceedings},
pages = {149},
publisher = {{ACM}},
year = {2000},
url = {https://doi.org/10.1145/333032.333046},
doi = {10.1145/333032.333046},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/Farrahi00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/GrazianoDZ00,
author = {Mariagrazia Graziano and
Marco Delaurenti and
Maurizio Zamboni},
title = {Power supply design parameters prediction for high performance {IC}
design flows},
booktitle = {The Second {IEEE/ACM} International Workshop on System-Level Interconnect
Prediction {(SLIP} 2000), April 8-9, 2000, San Diego, California,
USA, Proceedings},
pages = {61--67},
publisher = {{ACM}},
year = {2000},
url = {https://doi.org/10.1145/333032.333034},
doi = {10.1145/333032.333034},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/GrazianoDZ00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/JoynerZDM00,
author = {James W. Joyner and
Payman Zarkesh{-}Ha and
Jeffrey A. Davis and
James D. Meindl},
title = {Vertical pitch limitations on performance enhancement in bonded three-dimensional
interconnect architectures},
booktitle = {The Second {IEEE/ACM} International Workshop on System-Level Interconnect
Prediction {(SLIP} 2000), April 8-9, 2000, San Diego, California,
USA, Proceedings},
pages = {123--127},
publisher = {{ACM}},
year = {2000},
url = {https://doi.org/10.1145/333032.333042},
doi = {10.1145/333032.333042},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/JoynerZDM00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/KahngS00,
author = {Andrew B. Kahng and
Dirk Stroobandt},
title = {Wiring layer assignments with consistent stage delays},
booktitle = {The Second {IEEE/ACM} International Workshop on System-Level Interconnect
Prediction {(SLIP} 2000), April 8-9, 2000, San Diego, California,
USA, Proceedings},
pages = {115--122},
publisher = {{ACM}},
year = {2000},
url = {https://doi.org/10.1145/333032.333041},
doi = {10.1145/333032.333041},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/KahngS00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/LiNM00,
author = {Peng Li and
Pranab K. Nag and
Wojciech Maly},
title = {Cost based tradeoff analysis of standard cell designs},
booktitle = {The Second {IEEE/ACM} International Workshop on System-Level Interconnect
Prediction {(SLIP} 2000), April 8-9, 2000, San Diego, California,
USA, Proceedings},
pages = {129--135},
publisher = {{ACM}},
year = {2000},
url = {https://doi.org/10.1145/333032.333043},
doi = {10.1145/333032.333043},
timestamp = {Thu, 31 Oct 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/LiNM00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/SaraswatSBK00,
author = {Krishna Saraswat and
Shukri J. Souri and
Kaustav Banerjee and
Pawan Kapur},
title = {Performance analysis and technology of 3-D ICs},
booktitle = {The Second {IEEE/ACM} International Workshop on System-Level Interconnect
Prediction {(SLIP} 2000), April 8-9, 2000, San Diego, California,
USA, Proceedings},
pages = {85--90},
publisher = {{ACM}},
year = {2000},
url = {https://doi.org/10.1145/333032.333037},
doi = {10.1145/333032.333037},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/SaraswatSBK00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/SchefferN00,
author = {Louis Scheffer and
Eric Nequist},
title = {Why interconnect prediction doesn't work},
booktitle = {The Second {IEEE/ACM} International Workshop on System-Level Interconnect
Prediction {(SLIP} 2000), April 8-9, 2000, San Diego, California,
USA, Proceedings},
pages = {139--144},
publisher = {{ACM}},
year = {2000},
url = {https://doi.org/10.1145/333032.333044},
doi = {10.1145/333032.333044},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/SchefferN00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/StroobandtM00,
author = {Dirk Stroobandt and
Herwig Van Marck},
title = {Efficient representation of interconnection length distributions using
generating polynomials},
booktitle = {The Second {IEEE/ACM} International Workshop on System-Level Interconnect
Prediction {(SLIP} 2000), April 8-9, 2000, San Diego, California,
USA, Proceedings},
pages = {99--105},
publisher = {{ACM}},
year = {2000},
url = {https://doi.org/10.1145/333032.333039},
doi = {10.1145/333032.333039},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/StroobandtM00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/Sylvester00,
author = {Dennis Sylvester},
title = {Measurement techniques and interconnect estimation},
booktitle = {The Second {IEEE/ACM} International Workshop on System-Level Interconnect
Prediction {(SLIP} 2000), April 8-9, 2000, San Diego, California,
USA, Proceedings},
pages = {79--81},
publisher = {{ACM}},
year = {2000},
url = {https://doi.org/10.1145/333032.333036},
doi = {10.1145/333032.333036},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/Sylvester00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/Zarkesh-HaDLM00,
author = {Payman Zarkesh{-}Ha and
Jeffrey A. Davis and
William Loh and
James D. Meindl},
title = {Prediction of interconnect fan-out distribution using Rent's rule},
booktitle = {The Second {IEEE/ACM} International Workshop on System-Level Interconnect
Prediction {(SLIP} 2000), April 8-9, 2000, San Diego, California,
USA, Proceedings},
pages = {107--112},
publisher = {{ACM}},
year = {2000},
url = {https://doi.org/10.1145/333032.333040},
doi = {10.1145/333032.333040},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/Zarkesh-HaDLM00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/slip/2000,
title = {The Second {IEEE/ACM} International Workshop on System-Level Interconnect
Prediction {(SLIP} 2000), April 8-9, 2000, San Diego, California,
USA, Proceedings},
publisher = {{ACM}},
year = {2000},
timestamp = {Thu, 21 Jun 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/slip/2000.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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