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@inproceedings{DBLP:conf/hipeac/AmirshahiAA24,
author = {Alireza Amirshahi and
Giovanni Ansaloni and
David Atienza},
editor = {Jo{\~{a}}o Bispo and
Sotirios Xydis and
Serena Curzel and
Lu{\'{\i}}s Miguel Sousa},
title = {Accelerator-Driven Data Arrangement to Minimize Transformers Run-Time
on Multi-Core Architectures},
booktitle = {15th Workshop on Parallel Programming and Run-Time Management Techniques
for Many-Core Architectures and 13th Workshop on Design Tools and
Architectures for Multicore Embedded Computing Platforms, {PARMA-DITAM}
2024, January 18, 2024, Munich, Germany},
series = {OASIcs},
volume = {116},
pages = {2:1--2:13},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2024},
url = {https://doi.org/10.4230/OASIcs.PARMA-DITAM.2024.2},
doi = {10.4230/OASICS.PARMA-DITAM.2024.2},
timestamp = {Mon, 04 Mar 2024 16:45:15 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/AmirshahiAA24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/DeroueiVSM24,
author = {Mohammadhassan Gholami Derouei and
Paolo Valente and
Marco Solieri and
Andrea Marongiu},
editor = {Patrick Meumeu Yomsi and
Stefan Wildermann},
title = {{HMB:} Scheduling PREM-Like Real-Time Tasks at High Memory Bandwidth
(Invited Paper)},
booktitle = {Fifth Workshop on Next Generation Real-Time Embedded Systems, {NG-RES}
2024, January 17-19, 2024, Munich, Germany},
series = {OASIcs},
volume = {117},
pages = {1:1--1:18},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2024},
url = {https://doi.org/10.4230/OASIcs.NG-RES.2024.1},
doi = {10.4230/OASICS.NG-RES.2024.1},
timestamp = {Mon, 04 Mar 2024 16:45:38 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/DeroueiVSM24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/EsperT24,
author = {Khalil Esper and
J{\"{u}}rgen Teich},
editor = {Patrick Meumeu Yomsi and
Stefan Wildermann},
title = {History-Based Run-Time Requirement Enforcement of Non-Functional Properties
on MPSoCs},
booktitle = {Fifth Workshop on Next Generation Real-Time Embedded Systems, {NG-RES}
2024, January 17-19, 2024, Munich, Germany},
series = {OASIcs},
volume = {117},
pages = {4:1--4:11},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2024},
url = {https://doi.org/10.4230/OASIcs.NG-RES.2024.4},
doi = {10.4230/OASICS.NG-RES.2024.4},
timestamp = {Mon, 04 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/EsperT24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/FerrandiFBGC24,
author = {Fabrizio Ferrandi and
Michele Fiorito and
Claudio Barone and
Giovanni Gozzi and
Serena Curzel},
editor = {Jo{\~{a}}o Bispo and
Sotirios Xydis and
Serena Curzel and
Lu{\'{\i}}s Miguel Sousa},
title = {High-Level Synthesis Developments in the Context of European Space
Technology Research (Invited Talk)},
booktitle = {15th Workshop on Parallel Programming and Run-Time Management Techniques
for Many-Core Architectures and 13th Workshop on Design Tools and
Architectures for Multicore Embedded Computing Platforms, {PARMA-DITAM}
2024, January 18, 2024, Munich, Germany},
series = {OASIcs},
volume = {116},
pages = {1:1--1:12},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2024},
url = {https://doi.org/10.4230/OASIcs.PARMA-DITAM.2024.1},
doi = {10.4230/OASICS.PARMA-DITAM.2024.1},
timestamp = {Mon, 04 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/FerrandiFBGC24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/GrapentinEZPGP24,
author = {Andreas Grapentin and
Felix Eberhardt and
Tobias Zagorni and
Andreas Polze and
Michele Gazzetti and
Christian Pinto},
editor = {Jo{\~{a}}o Bispo and
Sotirios Xydis and
Serena Curzel and
Lu{\'{\i}}s Miguel Sousa},
title = {Zero-Copy, Minimal-Blackout Virtual Machine Migrations Using Disaggregated
Shared Memory},
booktitle = {15th Workshop on Parallel Programming and Run-Time Management Techniques
for Many-Core Architectures and 13th Workshop on Design Tools and
Architectures for Multicore Embedded Computing Platforms, {PARMA-DITAM}
2024, January 18, 2024, Munich, Germany},
series = {OASIcs},
volume = {116},
pages = {3:1--3:13},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2024},
url = {https://doi.org/10.4230/OASIcs.PARMA-DITAM.2024.3},
doi = {10.4230/OASICS.PARMA-DITAM.2024.3},
timestamp = {Mon, 04 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/GrapentinEZPGP24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/KhanamABJ024,
author = {Zeba Khanam and
Vejey Pradeep Suresh Achari and
Issam Boukhennoufa and
Anish Jindal and
Amit Kumar Singh},
editor = {Patrick Meumeu Yomsi and
Stefan Wildermann},
title = {A Multi-Modal Distributed Real-Time IoT System for Urban Traffic Control
(Invited Paper)},
booktitle = {Fifth Workshop on Next Generation Real-Time Embedded Systems, {NG-RES}
2024, January 17-19, 2024, Munich, Germany},
series = {OASIcs},
volume = {117},
pages = {2:1--2:10},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2024},
url = {https://doi.org/10.4230/OASIcs.NG-RES.2024.2},
doi = {10.4230/OASICS.NG-RES.2024.2},
timestamp = {Mon, 04 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/KhanamABJ024.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/KurunathanGST24,
author = {Harrison Kurunathan and
Miguel Guti{\'{e}}rrez Gait{\'{a}}n and
Ramiro S{\'{a}}mano{-}Robles and
Eduardo Tovar},
editor = {Patrick Meumeu Yomsi and
Stefan Wildermann},
title = {DynaVLC - Towards Dynamic {GTS} Allocation in {VLC} Networks (Invited
Paper)},
booktitle = {Fifth Workshop on Next Generation Real-Time Embedded Systems, {NG-RES}
2024, January 17-19, 2024, Munich, Germany},
series = {OASIcs},
volume = {117},
pages = {3:1--3:11},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2024},
url = {https://doi.org/10.4230/OASIcs.NG-RES.2024.3},
doi = {10.4230/OASICS.NG-RES.2024.3},
timestamp = {Mon, 04 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/KurunathanGST24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/MagnaniD0AC24,
author = {Gabriele Magnani and
Lev Denisov and
Daniele Cattaneo and
Giovanni Agosta and
Stefano Cherubin},
editor = {Jo{\~{a}}o Bispo and
Sotirios Xydis and
Serena Curzel and
Lu{\'{\i}}s Miguel Sousa},
title = {Precision Tuning the Rust Memory-Safe Programming Language},
booktitle = {15th Workshop on Parallel Programming and Run-Time Management Techniques
for Many-Core Architectures and 13th Workshop on Design Tools and
Architectures for Multicore Embedded Computing Platforms, {PARMA-DITAM}
2024, January 18, 2024, Munich, Germany},
series = {OASIcs},
volume = {116},
pages = {4:1--4:12},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2024},
url = {https://doi.org/10.4230/OASIcs.PARMA-DITAM.2024.4},
doi = {10.4230/OASICS.PARMA-DITAM.2024.4},
timestamp = {Mon, 04 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/MagnaniD0AC24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/Oey0S024,
author = {Oliver Oey and
Michael H{\"{u}}bner and
Timo Stripf and
J{\"{u}}rgen Becker},
editor = {Jo{\~{a}}o Bispo and
Sotirios Xydis and
Serena Curzel and
Lu{\'{\i}}s Miguel Sousa},
title = {Embedded Multi-Core Code Generation with Cross-Layer Parallelization},
booktitle = {15th Workshop on Parallel Programming and Run-Time Management Techniques
for Many-Core Architectures and 13th Workshop on Design Tools and
Architectures for Multicore Embedded Computing Platforms, {PARMA-DITAM}
2024, January 18, 2024, Munich, Germany},
series = {OASIcs},
volume = {116},
pages = {5:1--5:13},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2024},
url = {https://doi.org/10.4230/OASIcs.PARMA-DITAM.2024.5},
doi = {10.4230/OASICS.PARMA-DITAM.2024.5},
timestamp = {Mon, 04 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/Oey0S024.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/ProcacciniSBLGG24,
author = {Marco Procaccini and
Amin Sahebi and
Marco Barbone and
Wayne Luk and
Georgi Gaydadjiev and
Roberto Giorgi},
editor = {Jo{\~{a}}o Bispo and
Sotirios Xydis and
Serena Curzel and
Lu{\'{\i}}s Miguel Sousa},
title = {Accelerating Large-Scale Graph Processing with FPGAs: Lesson Learned
and Future Directions},
booktitle = {15th Workshop on Parallel Programming and Run-Time Management Techniques
for Many-Core Architectures and 13th Workshop on Design Tools and
Architectures for Multicore Embedded Computing Platforms, {PARMA-DITAM}
2024, January 18, 2024, Munich, Germany},
series = {OASIcs},
volume = {116},
pages = {6:1--6:12},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2024},
url = {https://doi.org/10.4230/OASIcs.PARMA-DITAM.2024.6},
doi = {10.4230/OASICS.PARMA-DITAM.2024.6},
timestamp = {Mon, 04 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/ProcacciniSBLGG24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/X24,
editor = {Jo{\~{a}}o Bispo and
Sotirios Xydis and
Serena Curzel and
Lu{\'{\i}}s Miguel Sousa},
title = {Front Matter, Table of Contents, Preface, Conference Organization},
booktitle = {15th Workshop on Parallel Programming and Run-Time Management Techniques
for Many-Core Architectures and 13th Workshop on Design Tools and
Architectures for Multicore Embedded Computing Platforms, {PARMA-DITAM}
2024, January 18, 2024, Munich, Germany},
series = {OASIcs},
volume = {116},
pages = {0:1--0:10},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2024},
url = {https://doi.org/10.4230/OASIcs.PARMA-DITAM.2024.0},
doi = {10.4230/OASICS.PARMA-DITAM.2024.0},
timestamp = {Mon, 04 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/X24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/X24a,
editor = {Patrick Meumeu Yomsi and
Stefan Wildermann},
title = {Front Matter, Table of Contents, Preface, Conference Organization},
booktitle = {Fifth Workshop on Next Generation Real-Time Embedded Systems, {NG-RES}
2024, January 17-19, 2024, Munich, Germany},
series = {OASIcs},
volume = {117},
pages = {0:1--0:10},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2024},
url = {https://doi.org/10.4230/OASIcs.NG-RES.2024.0},
doi = {10.4230/OASICS.NG-RES.2024.0},
timestamp = {Mon, 04 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/X24a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rapido/BosbachS0BZPL24,
author = {Nils Bosbach and
Alwalid Salama and
Lukas J{\"{u}}nger and
Mark Burton and
Niko Zurstra{\ss}en and
Rebecca Pelke and
Rainer Leupers},
editor = {Lilia Zaourar and
Daniel Chillet and
Daniel Gracia P{\'{e}}rez and
Morteza Biglari{-}Abhari and
R{\'{e}}da Nouacer and
Matthias Jung and
Gianluca Palermo},
title = {NQC{\({^2}\)}: {A} Non-Intrusive {QEMU} Code Coverage Plugin},
booktitle = {Proceedings of the 16th Workshop on Rapid Simulation and Performance
Evaluation for Design, {RAPIDO} 2024, Munich, Germany, 18 January
2024},
pages = {16--21},
publisher = {{ACM}},
year = {2024},
url = {https://doi.org/10.1145/3642921.3642924},
doi = {10.1145/3642921.3642924},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/rapido/BosbachS0BZPL24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rapido/FuZKD24,
author = {Vincent Fu and
Lilia Zaourar and
Alix Munier Kordon and
Marc Duranton},
editor = {Lilia Zaourar and
Daniel Chillet and
Daniel Gracia P{\'{e}}rez and
Morteza Biglari{-}Abhari and
R{\'{e}}da Nouacer and
Matthias Jung and
Gianluca Palermo},
title = {Design Space Exploration of {HPC} Systems with Random Forest-based
Bayesian Optimization},
booktitle = {Proceedings of the 16th Workshop on Rapid Simulation and Performance
Evaluation for Design, {RAPIDO} 2024, Munich, Germany, 18 January
2024},
pages = {9--15},
publisher = {{ACM}},
year = {2024},
url = {https://doi.org/10.1145/3642921.3642923},
doi = {10.1145/3642921.3642923},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/rapido/FuZKD24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rapido/HenriquesB024,
author = {Miguel Henriques and
Jo{\~{a}}o Bispo and
Nuno Paulino},
editor = {Lilia Zaourar and
Daniel Chillet and
Daniel Gracia P{\'{e}}rez and
Morteza Biglari{-}Abhari and
R{\'{e}}da Nouacer and
Matthias Jung and
Gianluca Palermo},
title = {Using Source-to-Source to Target {RISC-V} Custom Extensions: {UVE}
Case-Study},
booktitle = {Proceedings of the 16th Workshop on Rapid Simulation and Performance
Evaluation for Design, {RAPIDO} 2024, Munich, Germany, 18 January
2024},
pages = {42--50},
publisher = {{ACM}},
year = {2024},
url = {https://doi.org/10.1145/3642921.3642930},
doi = {10.1145/3642921.3642930},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/rapido/HenriquesB024.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rapido/ManninoHPMB24,
author = {Mirco Mannino and
Yinting Huang and
Biagio Peccerillo and
Alessio Medaglini and
Sandro Bartolini},
editor = {Lilia Zaourar and
Daniel Chillet and
Daniel Gracia P{\'{e}}rez and
Morteza Biglari{-}Abhari and
R{\'{e}}da Nouacer and
Matthias Jung and
Gianluca Palermo},
title = {Integration of {RISC-V} Page Table Walk in gem5 {SE} Mode},
booktitle = {Proceedings of the 16th Workshop on Rapid Simulation and Performance
Evaluation for Design, {RAPIDO} 2024, Munich, Germany, 18 January
2024},
pages = {22--28},
publisher = {{ACM}},
year = {2024},
url = {https://doi.org/10.1145/3642921.3642926},
doi = {10.1145/3642921.3642926},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/rapido/ManninoHPMB24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rapido/MatosBS24,
author = {Jo{\~{a}}o N. Matos and
Jo{\~{a}}o Bispo and
Lu{\'{\i}}s Miguel Sousa},
editor = {Lilia Zaourar and
Daniel Chillet and
Daniel Gracia P{\'{e}}rez and
Morteza Biglari{-}Abhari and
R{\'{e}}da Nouacer and
Matthias Jung and
Gianluca Palermo},
title = {A {C} Subset for Ergonomic Source-to-Source Analyses and Transformations},
booktitle = {Proceedings of the 16th Workshop on Rapid Simulation and Performance
Evaluation for Design, {RAPIDO} 2024, Munich, Germany, 18 January
2024},
pages = {1--8},
publisher = {{ACM}},
year = {2024},
url = {https://doi.org/10.1145/3642921.3642922},
doi = {10.1145/3642921.3642922},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/rapido/MatosBS24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rapido/PerdomoKLZCB024,
author = {Elias Perdomo and
Alexander Kropotov and
Francelly Katherine Cano Ladino and
Syed Zafar and
Teresa Cervero and
Xavier Martorell Bofill and
Behzad Salami},
editor = {Lilia Zaourar and
Daniel Chillet and
Daniel Gracia P{\'{e}}rez and
Morteza Biglari{-}Abhari and
R{\'{e}}da Nouacer and
Matthias Jung and
Gianluca Palermo},
title = {Makinote: An FPGA-Based {HW/SW} Platform for Pre-Silicon Emulation
of {RISC-V} Designs},
booktitle = {Proceedings of the 16th Workshop on Rapid Simulation and Performance
Evaluation for Design, {RAPIDO} 2024, Munich, Germany, 18 January
2024},
pages = {29--34},
publisher = {{ACM}},
year = {2024},
url = {https://doi.org/10.1145/3642921.3642928},
doi = {10.1145/3642921.3642928},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/rapido/PerdomoKLZCB024.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rapido/SchatzleFHHPSBW24,
author = {Fabian Sch{\"{a}}tzle and
Carlos Falquez and
Stefan Heinen and
Nam Ho and
Antoni Portero and
Estela Suarez and
Johannes Van Den Boom and
Stefan van Waasen},
editor = {Lilia Zaourar and
Daniel Chillet and
Daniel Gracia P{\'{e}}rez and
Morteza Biglari{-}Abhari and
R{\'{e}}da Nouacer and
Matthias Jung and
Gianluca Palermo},
title = {Modeling methodology for multi-die chip design based on gem5/SystemC
co-simulation},
booktitle = {Proceedings of the 16th Workshop on Rapid Simulation and Performance
Evaluation for Design, {RAPIDO} 2024, Munich, Germany, 18 January
2024},
pages = {35--41},
publisher = {{ACM}},
year = {2024},
url = {https://doi.org/10.1145/3642921.3642956},
doi = {10.1145/3642921.3642956},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/rapido/SchatzleFHHPSBW24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/hipeac/2024ngres,
editor = {Patrick Meumeu Yomsi and
Stefan Wildermann},
title = {Fifth Workshop on Next Generation Real-Time Embedded Systems, {NG-RES}
2024, January 17-19, 2024, Munich, Germany},
series = {OASIcs},
volume = {117},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2024},
url = {https://www.dagstuhl.de/dagpub/978-3-95977-313-3},
isbn = {978-3-95977-313-3},
timestamp = {Mon, 04 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/2024ngres.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/hipeac/2024parma,
editor = {Jo{\~{a}}o Bispo and
Sotirios Xydis and
Serena Curzel and
Lu{\'{\i}}s Miguel Sousa},
title = {15th Workshop on Parallel Programming and Run-Time Management Techniques
for Many-Core Architectures and 13th Workshop on Design Tools and
Architectures for Multicore Embedded Computing Platforms, {PARMA-DITAM}
2024, January 18, 2024, Munich, Germany},
series = {OASIcs},
volume = {116},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2024},
url = {https://www.dagstuhl.de/dagpub/978-3-95977-307-2},
isbn = {978-3-95977-307-2},
timestamp = {Mon, 04 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/2024parma.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/rapido/2024,
editor = {Lilia Zaourar and
Daniel Chillet and
Daniel Gracia P{\'{e}}rez and
Morteza Biglari{-}Abhari and
R{\'{e}}da Nouacer and
Matthias Jung and
Gianluca Palermo},
title = {Proceedings of the 16th Workshop on Rapid Simulation and Performance
Evaluation for Design, {RAPIDO} 2024, Munich, Germany, 18 January
2024},
publisher = {{ACM}},
year = {2024},
url = {https://doi.org/10.1145/3642921},
doi = {10.1145/3642921},
timestamp = {Fri, 12 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/rapido/2024.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/BadarouxDP23,
author = {Marie Badaroux and
Julie Dumas and
Fr{\'{e}}d{\'{e}}ric P{\'{e}}trot},
title = {Fast Instruction Cache Simulation is Trickier than You Think},
booktitle = {Proceedings of the DroneSE and {RAPIDO:} System Engineering for constrained
embedded systems, {RAPIDO} 2023, Toulouse, France, January 17-18,
2023},
pages = {48--53},
publisher = {{ACM}},
year = {2023},
url = {https://doi.org/10.1145/3579170.3579261},
doi = {10.1145/3579170.3579261},
timestamp = {Sat, 29 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/BadarouxDP23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/BarchiPPTBA23,
author = {Francesco Barchi and
Giacomo Pasini and
Emanuele Parisi and
Giuseppe Tagliavini and
Andrea Bartolini and
Andrea Acquaviva},
editor = {Jo{\~{a}}o Bispo and
Henri{-}Pierre Charles and
Stefano Cherubin and
Giuseppe Massari},
title = {RUST-Encoded Stream Ciphers on a {RISC-V} Parallel Ultra-Low-Power
Processor (Invited Paper)},
booktitle = {14th Workshop on Parallel Programming and Run-Time Management Techniques
for Many-Core Architectures and 12th Workshop on Design Tools and
Architectures for Multicore Embedded Computing Platforms, {PARMA-DITAM}
2023, January 17, 2023, Toulouse, France},
series = {OASIcs},
volume = {107},
pages = {3:1--3:12},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2023},
url = {https://doi.org/10.4230/OASIcs.PARMA-DITAM.2023.3},
doi = {10.4230/OASICS.PARMA-DITAM.2023.3},
timestamp = {Wed, 15 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/BarchiPPTBA23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/Bispo0S23,
author = {Jo{\~{a}}o Bispo and
Nuno Paulino and
Lu{\'{\i}}s Miguel Sousa},
editor = {Jo{\~{a}}o Bispo and
Henri{-}Pierre Charles and
Stefano Cherubin and
Giuseppe Massari},
title = {Challenges and Opportunities in {C/C++} Source-To-Source Compilation
(Invited Paper)},
booktitle = {14th Workshop on Parallel Programming and Run-Time Management Techniques
for Many-Core Architectures and 12th Workshop on Design Tools and
Architectures for Multicore Embedded Computing Platforms, {PARMA-DITAM}
2023, January 17, 2023, Toulouse, France},
series = {OASIcs},
volume = {107},
pages = {2:1--2:15},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2023},
url = {https://doi.org/10.4230/OASIcs.PARMA-DITAM.2023.2},
doi = {10.4230/OASICS.PARMA-DITAM.2023.2},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/Bispo0S23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/BorgstromRB23,
author = {Gustaf Borgstr{\"{o}}m and
Christian Rohner and
David Black{-}Schaffer},
title = {Faster Functional Warming with Cache Merging},
booktitle = {Proceedings of the DroneSE and {RAPIDO:} System Engineering for constrained
embedded systems, {RAPIDO} 2023, Toulouse, France, January 17-18,
2023},
pages = {39--47},
publisher = {{ACM}},
year = {2023},
url = {https://doi.org/10.1145/3579170.3579256},
doi = {10.1145/3579170.3579256},
timestamp = {Sat, 29 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/BorgstromRB23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/Bosbach0PZL23,
author = {Nils Bosbach and
Lukas J{\"{u}}nger and
Rebecca Pelke and
Niko Zurstra{\ss}en and
Rainer Leupers},
title = {Entropy-Based Analysis of Benchmarks for Instruction Set Simulators},
booktitle = {Proceedings of the DroneSE and {RAPIDO:} System Engineering for constrained
embedded systems, {RAPIDO} 2023, Toulouse, France, January 17-18,
2023},
pages = {54--59},
publisher = {{ACM}},
year = {2023},
url = {https://doi.org/10.1145/3579170.3579267},
doi = {10.1145/3579170.3579267},
timestamp = {Sat, 29 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/Bosbach0PZL23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/CaironiC23,
author = {Fabio Caironi and
Niccol{\`{o}} Andrea Castelli},
editor = {Jo{\~{a}}o Bispo and
Henri{-}Pierre Charles and
Stefano Cherubin and
Giuseppe Massari},
title = {ByteNite: {A} New Business Model for Grid Computing (Invited Paper)},
booktitle = {14th Workshop on Parallel Programming and Run-Time Management Techniques
for Many-Core Architectures and 12th Workshop on Design Tools and
Architectures for Multicore Embedded Computing Platforms, {PARMA-DITAM}
2023, January 17, 2023, Toulouse, France},
series = {OASIcs},
volume = {107},
pages = {1:1--1:12},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2023},
url = {https://doi.org/10.4230/OASIcs.PARMA-DITAM.2023.1},
doi = {10.4230/OASICS.PARMA-DITAM.2023.1},
timestamp = {Wed, 15 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/CaironiC23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/CostaC0SMMTB023,
author = {Diogo Costa and
Luca Cuomo and
Daniel Oliveira and
Ida Maria Savino and
Bruno Morelli and
Jos{\'{e}} Martins and
Fabrizio Tronci and
Alessandro Biasci and
Sandro Pinto},
editor = {Federico Terraneo and
Daniele Cattaneo},
title = {{IRQ} Coloring: Mitigating Interrupt-Generated Interference on {ARM}
Multicore Platforms},
booktitle = {Fourth Workshop on Next Generation Real-Time Embedded Systems, {NG-RES}
2023, January 18, 2023, Toulouse, France},
series = {OASIcs},
volume = {108},
pages = {2:1--2:13},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2023},
url = {https://doi.org/10.4230/OASIcs.NG-RES.2023.2},
doi = {10.4230/OASICS.NG-RES.2023.2},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/CostaC0SMMTB023.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/DariolNHSPG23,
author = {Quentin Dariol and
S{\'{e}}bastien Le Nours and
Domenik Helms and
Ralf Stemmer and
S{\'{e}}bastien Pillement and
Kim Gr{\"{u}}ttner},
title = {Fast Yet Accurate Timing and Power Prediction of Artificial Neural
Networks Deployed on Clock-Gated Multi-Core Platforms},
booktitle = {Proceedings of the DroneSE and {RAPIDO:} System Engineering for constrained
embedded systems, {RAPIDO} 2023, Toulouse, France, January 17-18,
2023},
pages = {79--86},
publisher = {{ACM}},
year = {2023},
url = {https://doi.org/10.1145/3579170.3579263},
doi = {10.1145/3579170.3579263},
timestamp = {Sat, 29 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/DariolNHSPG23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/EsperSSWT23,
author = {Khalil Esper and
Jan Spieck and
Pierre{-}Louis Sixdenier and
Stefan Wildermann and
J{\"{u}}rgen Teich},
editor = {Federico Terraneo and
Daniele Cattaneo},
title = {{RAVEN:} Reinforcement Learning for Generating Verifiable Run-Time
Requirement Enforcers for MPSoCs},
booktitle = {Fourth Workshop on Next Generation Real-Time Embedded Systems, {NG-RES}
2023, January 18, 2023, Toulouse, France},
series = {OASIcs},
volume = {108},
pages = {7:1--7:16},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2023},
url = {https://doi.org/10.4230/OASIcs.NG-RES.2023.7},
doi = {10.4230/OASICS.NG-RES.2023.7},
timestamp = {Fri, 17 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/EsperSSWT23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/GalimbertiMFZ23,
author = {Andrea Galimberti and
Gabriele Montanaro and
William Fornaciari and
Davide Zoni},
editor = {Jo{\~{a}}o Bispo and
Henri{-}Pierre Charles and
Stefano Cherubin and
Giuseppe Massari},
title = {An Evaluation of the State-Of-The-Art Software and Hardware Implementations
of {BIKE}},
booktitle = {14th Workshop on Parallel Programming and Run-Time Management Techniques
for Many-Core Architectures and 12th Workshop on Design Tools and
Architectures for Multicore Embedded Computing Platforms, {PARMA-DITAM}
2023, January 17, 2023, Toulouse, France},
series = {OASIcs},
volume = {107},
pages = {4:1--4:12},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2023},
url = {https://doi.org/10.4230/OASIcs.PARMA-DITAM.2023.4},
doi = {10.4230/OASICS.PARMA-DITAM.2023.4},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/GalimbertiMFZ23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/HotfilterSHKH023,
author = {Tim Hotfilter and
Patrick Schmidt and
Julian H{\"{o}}fer and
Fabian Kre{\ss} and
Tanja Harbaum and
J{\"{u}}rgen Becker},
title = {An Analytical Model of Configurable Systolic Arrays to find the Best-Fitting
Accelerator for a given {DNN} Workload},
booktitle = {Proceedings of the DroneSE and {RAPIDO:} System Engineering for constrained
embedded systems, {RAPIDO} 2023, Toulouse, France, January 17-18,
2023},
pages = {73--78},
publisher = {{ACM}},
year = {2023},
url = {https://doi.org/10.1145/3579170.3579258},
doi = {10.1145/3579170.3579258},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/HotfilterSHKH023.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/JellumLDSSBOLL23,
author = {Erling Rennemo Jellum and
Shaokai Lin and
Peter Donovan and
Efsane Soyer and
Fuzail Shakir and
Torleiv H. Bryne and
Milica Orlandic and
Marten Lohstroh and
Edward A. Lee},
editor = {Federico Terraneo and
Daniele Cattaneo},
title = {Beyond the Threaded Programming Model on Real-Time Operating Systems},
booktitle = {Fourth Workshop on Next Generation Real-Time Embedded Systems, {NG-RES}
2023, January 18, 2023, Toulouse, France},
series = {OASIcs},
volume = {108},
pages = {3:1--3:13},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2023},
url = {https://doi.org/10.4230/OASIcs.NG-RES.2023.3},
doi = {10.4230/OASICS.NG-RES.2023.3},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/JellumLDSSBOLL23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/KatsaragakisSMP23,
author = {Manolis Katsaragakis and
Konstantinos Stavrakakis and
Dimosthenis Masouros and
Lazaros Papadopoulos and
Dimitrios Soudris},
editor = {Jo{\~{a}}o Bispo and
Henri{-}Pierre Charles and
Stefano Cherubin and
Giuseppe Massari},
title = {Adjacent LSTM-Based Page Scheduling for Hybrid {DRAM/NVM} Memory Systems},
booktitle = {14th Workshop on Parallel Programming and Run-Time Management Techniques
for Many-Core Architectures and 12th Workshop on Design Tools and
Architectures for Multicore Embedded Computing Platforms, {PARMA-DITAM}
2023, January 17, 2023, Toulouse, France},
series = {OASIcs},
volume = {107},
pages = {7:1--7:12},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2023},
url = {https://doi.org/10.4230/OASIcs.PARMA-DITAM.2023.7},
doi = {10.4230/OASICS.PARMA-DITAM.2023.7},
timestamp = {Wed, 15 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/KatsaragakisSMP23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/KnodtelR23,
author = {Johannes Kn{\"{o}}dtel and
Marc Reichenbach},
title = {Datapath Optimization for Embedded Signal Processing Architectures
utilizing Design Space Exploration},
booktitle = {Proceedings of the DroneSE and {RAPIDO:} System Engineering for constrained
embedded systems, {RAPIDO} 2023, Toulouse, France, January 17-18,
2023},
pages = {60--65},
publisher = {{ACM}},
year = {2023},
url = {https://doi.org/10.1145/3579170.3579257},
doi = {10.1145/3579170.3579257},
timestamp = {Sat, 29 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/KnodtelR23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/LesniakAH023,
author = {Fabian Lesniak and
Nidhi Anantharajaiah and
Tanja Harbaum and
J{\"{u}}rgen Becker},
title = {Non-Intrusive Runtime Monitoring for Manycore Prototypes},
booktitle = {Proceedings of the DroneSE and {RAPIDO:} System Engineering for constrained
embedded systems, {RAPIDO} 2023, Toulouse, France, January 17-18,
2023},
pages = {31--38},
publisher = {{ACM}},
year = {2023},
url = {https://doi.org/10.1145/3579170.3579262},
doi = {10.1145/3579170.3579262},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/LesniakAH023.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/LetrasFT23,
author = {Mart{\'{\i}}n Letras and
Joachim Falk and
J{\"{u}}rgen Teich},
editor = {Federico Terraneo and
Daniele Cattaneo},
title = {Throughput and Memory Optimization for Parallel Implementations of
Dataflow Networks Using Multi-Reader Buffers},
booktitle = {Fourth Workshop on Next Generation Real-Time Embedded Systems, {NG-RES}
2023, January 18, 2023, Toulouse, France},
series = {OASIcs},
volume = {108},
pages = {6:1--6:13},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2023},
url = {https://doi.org/10.4230/OASIcs.NG-RES.2023.6},
doi = {10.4230/OASICS.NG-RES.2023.6},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/LetrasFT23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/Maggio23,
author = {Martina Maggio},
editor = {Federico Terraneo and
Daniele Cattaneo},
title = {Control Systems in the Presence of Computational Problems (Invited
Talk)},
booktitle = {Fourth Workshop on Next Generation Real-Time Embedded Systems, {NG-RES}
2023, January 18, 2023, Toulouse, France},
series = {OASIcs},
volume = {108},
pages = {1:1--1:1},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2023},
url = {https://doi.org/10.4230/OASIcs.NG-RES.2023.1},
doi = {10.4230/OASICS.NG-RES.2023.1},
timestamp = {Fri, 17 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/Maggio23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/MettlerRKMHS23,
author = {Marcel Mettler and
Martin Rapp and
Heba Khdr and
Daniel Mueller{-}Gritschneder and
J{\"{o}}rg Henkel and
Ulf Schlichtmann},
editor = {Jo{\~{a}}o Bispo and
Henri{-}Pierre Charles and
Stefano Cherubin and
Giuseppe Massari},
title = {MonTM: Monitoring-Based Thermal Management for Mixed-Criticality Systems},
booktitle = {14th Workshop on Parallel Programming and Run-Time Management Techniques
for Many-Core Architectures and 12th Workshop on Design Tools and
Architectures for Multicore Embedded Computing Platforms, {PARMA-DITAM}
2023, January 17, 2023, Toulouse, France},
series = {OASIcs},
volume = {107},
pages = {5:1--5:12},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2023},
url = {https://doi.org/10.4230/OASIcs.PARMA-DITAM.2023.5},
doi = {10.4230/OASICS.PARMA-DITAM.2023.5},
timestamp = {Wed, 15 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/MettlerRKMHS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/NouacerHDVHTG23,
author = {R{\'{e}}da Nouacer and
Mahmoud Hussein and
Paul Detterer and
Eugenio Villar and
Fernando Herrera and
Carlo Tieri and
Emmanuel Grolleau},
title = {Towards a European Network of Enabling Technologies for Drones},
booktitle = {Proceedings of the DroneSE and {RAPIDO:} System Engineering for constrained
embedded systems, {RAPIDO} 2023, Toulouse, France, January 17-18,
2023},
pages = {1--11},
publisher = {{ACM}},
year = {2023},
url = {https://doi.org/10.1145/3579170.3579264},
doi = {10.1145/3579170.3579264},
timestamp = {Sat, 29 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/NouacerHDVHTG23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/OllierAALGM23,
author = {Guillaume Ollier and
Fabio Arnez and
Morayo Adedjouma and
Rapha{\"{e}}l Lallement and
Simos Gerasimou and
Chokri Mraidha},
title = {Towards an Ontological Methodology for Dynamic Dependability Management
of Unmanned Aerial Vehicles},
booktitle = {Proceedings of the DroneSE and {RAPIDO:} System Engineering for constrained
embedded systems, {RAPIDO} 2023, Toulouse, France, January 17-18,
2023},
pages = {12--19},
publisher = {{ACM}},
year = {2023},
url = {https://doi.org/10.1145/3579170.3579265},
doi = {10.1145/3579170.3579265},
timestamp = {Sat, 29 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/OllierAALGM23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/PiccoliZFMCRSR23,
author = {Michele Piccoli and
Davide Zoni and
William Fornaciari and
Giuseppe Massari and
Marco Cococcioni and
Federico Rossi and
Sergio Saponara and
Emanuele Ruffaldi},
editor = {Jo{\~{a}}o Bispo and
Henri{-}Pierre Charles and
Stefano Cherubin and
Giuseppe Massari},
title = {Dynamic Power Consumption of the Full Posit Processing Unit: Analysis
and Experiments},
booktitle = {14th Workshop on Parallel Programming and Run-Time Management Techniques
for Many-Core Architectures and 12th Workshop on Design Tools and
Architectures for Multicore Embedded Computing Platforms, {PARMA-DITAM}
2023, January 17, 2023, Toulouse, France},
series = {OASIcs},
volume = {107},
pages = {6:1--6:11},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2023},
url = {https://doi.org/10.4230/OASIcs.PARMA-DITAM.2023.6},
doi = {10.4230/OASICS.PARMA-DITAM.2023.6},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/PiccoliZFMCRSR23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/RahnGPNSRTSTWP23,
author = {Sebastian Rahn and
Philipp Gehricke and
Can{-}Leon Peterm{\"{o}}ller and
Eric Neumann and
Philipp Schlinge and
Leon Rabius and
Henning Term{\"{u}}hlen and
Christopher Sieh and
Marco Tassemeier and
Thomas Wiemann and
Mario Porrmann},
title = {ReDroSe - Reconfigurable Drone Setup for Resource-Efficient {SLAM}},
booktitle = {Proceedings of the DroneSE and {RAPIDO:} System Engineering for constrained
embedded systems, {RAPIDO} 2023, Toulouse, France, January 17-18,
2023},
pages = {20--30},
publisher = {{ACM}},
year = {2023},
url = {https://doi.org/10.1145/3579170.3579266},
doi = {10.1145/3579170.3579266},
timestamp = {Sat, 29 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/RahnGPNSRTSTWP23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/ShahriP023,
author = {Ehsan Shahri and
Paulo Pedreiras and
Lu{\'{\i}}s Almeida},
editor = {Federico Terraneo and
Daniele Cattaneo},
title = {Response Time Analysis for {RT-MQTT} Protocol Grounded on {SDN}},
booktitle = {Fourth Workshop on Next Generation Real-Time Embedded Systems, {NG-RES}
2023, January 18, 2023, Toulouse, France},
series = {OASIcs},
volume = {108},
pages = {5:1--5:15},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2023},
url = {https://doi.org/10.4230/OASIcs.NG-RES.2023.5},
doi = {10.4230/OASICS.NG-RES.2023.5},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/ShahriP023.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/SorrentinoTL23,
author = {Alessandro Sorrentino and
Federico Terraneo and
Alberto Leva},
editor = {Federico Terraneo and
Daniele Cattaneo},
title = {Efficient Abstraction of Clock Synchronization at the Operating System
Level},
booktitle = {Fourth Workshop on Next Generation Real-Time Embedded Systems, {NG-RES}
2023, January 18, 2023, Toulouse, France},
series = {OASIcs},
volume = {108},
pages = {4:1--4:11},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2023},
url = {https://doi.org/10.4230/OASIcs.NG-RES.2023.4},
doi = {10.4230/OASICS.NG-RES.2023.4},
timestamp = {Fri, 17 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/SorrentinoTL23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/SteinerDS0W23,
author = {Lukas Steiner and
Gustavo Delazeri and
Iron Prando da Silva and
Matthias Jung and
Norbert Wehn},
title = {Automatic {DRAM} Subsystem Configuration with irace},
booktitle = {Proceedings of the DroneSE and {RAPIDO:} System Engineering for constrained
embedded systems, {RAPIDO} 2023, Toulouse, France, January 17-18,
2023},
pages = {66--72},
publisher = {{ACM}},
year = {2023},
url = {https://doi.org/10.1145/3579170.3579259},
doi = {10.1145/3579170.3579259},
timestamp = {Sat, 29 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/SteinerDS0W23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/X23,
editor = {Jo{\~{a}}o Bispo and
Henri{-}Pierre Charles and
Stefano Cherubin and
Giuseppe Massari},
title = {Front Matter, Table of Contents, Preface, Conference Organization},
booktitle = {14th Workshop on Parallel Programming and Run-Time Management Techniques
for Many-Core Architectures and 12th Workshop on Design Tools and
Architectures for Multicore Embedded Computing Platforms, {PARMA-DITAM}
2023, January 17, 2023, Toulouse, France},
series = {OASIcs},
volume = {107},
pages = {0:1--0:10},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2023},
url = {https://doi.org/10.4230/OASIcs.PARMA-DITAM.2023.0},
doi = {10.4230/OASICS.PARMA-DITAM.2023.0},
timestamp = {Wed, 15 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/X23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/X23a,
editor = {Federico Terraneo and
Daniele Cattaneo},
title = {Front Matter, Table of Contents, Preface, Conference Organization},
booktitle = {Fourth Workshop on Next Generation Real-Time Embedded Systems, {NG-RES}
2023, January 18, 2023, Toulouse, France},
series = {OASIcs},
volume = {108},
pages = {0:1--0:10},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2023},
url = {https://doi.org/10.4230/OASIcs.NG-RES.2023.0},
doi = {10.4230/OASICS.NG-RES.2023.0},
timestamp = {Fri, 17 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/X23a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/hipeac/2023dronese,
title = {Proceedings of the DroneSE and {RAPIDO:} System Engineering for constrained
embedded systems, {RAPIDO} 2023, Toulouse, France, January 17-18,
2023},
publisher = {{ACM}},
year = {2023},
url = {https://doi.org/10.1145/3579170},
doi = {10.1145/3579170},
timestamp = {Tue, 25 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/2023dronese.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/hipeac/2023ngres,
editor = {Federico Terraneo and
Daniele Cattaneo},
title = {Fourth Workshop on Next Generation Real-Time Embedded Systems, {NG-RES}
2023, January 18, 2023, Toulouse, France},
series = {OASIcs},
volume = {108},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2023},
url = {https://www.dagstuhl.de/dagpub/978-3-95977-268-6},
isbn = {978-3-95977-268-6},
timestamp = {Fri, 17 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/2023ngres.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/hipeac/2023parma,
editor = {Jo{\~{a}}o Bispo and
Henri{-}Pierre Charles and
Stefano Cherubin and
Giuseppe Massari},
title = {14th Workshop on Parallel Programming and Run-Time Management Techniques
for Many-Core Architectures and 12th Workshop on Design Tools and
Architectures for Multicore Embedded Computing Platforms, {PARMA-DITAM}
2023, January 17, 2023, Toulouse, France},
series = {OASIcs},
volume = {107},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2023},
url = {https://www.dagstuhl.de/dagpub/978-3-95977-269-3},
isbn = {978-3-95977-269-3},
timestamp = {Mon, 13 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/2023parma.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/0002MCA22,
author = {Daniele Cattaneo and
Gabriele Magnani and
Stefano Cherubin and
Giovanni Agosta},
editor = {Marko Bertogna and
Federico Terraneo and
Federico Reghenzani},
title = {Ahead-Of-Real-Time {(ART):} {A} Methodology for Static Reduction of
Worst-Case Execution Time},
booktitle = {Third Workshop on Next Generation Real-Time Embedded Systems, NG-RES@HiPEAC
2022, June 22, 2022, Budapest, Hungary},
series = {OASIcs},
volume = {98},
pages = {4:1--4:10},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2022},
url = {https://doi.org/10.4230/OASIcs.NG-RES.2022.4},
doi = {10.4230/OASICS.NG-RES.2022.4},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/0002MCA22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/BerezovAZS22,
author = {Maksim Berezov and
Corinne Ancourt and
Justyna Zawalska and
Maryna Savchenko},
editor = {Francesca Palumbo and
Jo{\~{a}}o Bispo and
Stefano Cherubin},
title = {COLA-Gen: Active Learning Techniques for Automatic Code Generation
of Benchmarks},
booktitle = {13th Workshop on Parallel Programming and Run-Time Management Techniques
for Many-Core Architectures and 11th Workshop on Design Tools and
Architectures for Multicore Embedded Computing Platforms, {PARMA-DITAM}
2022, June 22, 2022, Budapest, Hungary},
series = {OASIcs},
volume = {100},
pages = {3:1--3:14},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2022},
url = {https://doi.org/10.4230/OASIcs.PARMA-DITAM.2022.3},
doi = {10.4230/OASICS.PARMA-DITAM.2022.3},
timestamp = {Thu, 09 Jun 2022 16:07:29 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/BerezovAZS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/Buttazzo22,
author = {Giorgio C. Buttazzo},
editor = {Marko Bertogna and
Federico Terraneo and
Federico Reghenzani},
title = {Can We Trust AI-Powered Real-Time Embedded Systems? (Invited Paper)},
booktitle = {Third Workshop on Next Generation Real-Time Embedded Systems, NG-RES@HiPEAC
2022, June 22, 2022, Budapest, Hungary},
series = {OASIcs},
volume = {98},
pages = {1:1--1:14},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2022},
url = {https://doi.org/10.4230/OASIcs.NG-RES.2022.1},
doi = {10.4230/OASICS.NG-RES.2022.1},
timestamp = {Mon, 13 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/Buttazzo22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/CatalVWHD22,
author = {Ozan {\c{C}}atal and
Tim Verbelen and
Ni Wang and
Matthias Hartmann and
Bart Dhoedt},
title = {Bio-inspired monocular drone {SLAM}},
booktitle = {DroneSE and {RAPIDO} '22: System Engineering for constrained embedded
systems, Budapest Hungary, January 17 - 19, 2022},
pages = {21--26},
publisher = {{ACM}},
year = {2022},
url = {https://doi.org/10.1145/3522784.3522788},
doi = {10.1145/3522784.3522788},
timestamp = {Tue, 30 Aug 2022 17:58:59 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/CatalVWHD22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/CorradiF22,
author = {Federico Corradi and
Francesco Fioranelli},
title = {Radar Perception for Autonomous Unmanned Aerial Vehicles: a Survey},
booktitle = {DroneSE and {RAPIDO} '22: System Engineering for constrained embedded
systems, Budapest Hungary, January 17 - 19, 2022},
pages = {14--20},
publisher = {{ACM}},
year = {2022},
url = {https://doi.org/10.1145/3522784.3522787},
doi = {10.1145/3522784.3522787},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/CorradiF22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/DupeyrouxDWC22,
author = {Julien Dupeyroux and
Raoul Dinaux and
Nikhil Wessendorp and
Guido de Croon},
title = {A Novel Obstacle Detection and Avoidance Dataset for Drones},
booktitle = {DroneSE and {RAPIDO} '22: System Engineering for constrained embedded
systems, Budapest Hungary, January 17 - 19, 2022},
pages = {8--13},
publisher = {{ACM}},
year = {2022},
url = {https://doi.org/10.1145/3522784.3522786},
doi = {10.1145/3522784.3522786},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/DupeyrouxDWC22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/EscuinKIMVC22,
author = {Carlos Escuin and
Asif Ali Khan and
Pablo Ib{\'{a}}{\~{n}}ez and
Teresa Monreal and
V{\'{\i}}ctor Vi{\~{n}}als and
Jer{\'{o}}nimo Castrill{\'{o}}n},
title = {HyCSim: {A} rapid design space exploration tool for emerging hybrid
last-level caches},
booktitle = {DroneSE and {RAPIDO} '22: System Engineering for constrained embedded
systems, Budapest Hungary, January 17 - 19, 2022},
pages = {53--58},
publisher = {{ACM}},
year = {2022},
url = {https://doi.org/10.1145/3522784.3522801},
doi = {10.1145/3522784.3522801},
timestamp = {Tue, 30 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/EscuinKIMVC22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/EsperWT22,
author = {Khalil Esper and
Stefan Wildermann and
J{\"{u}}rgen Teich},
editor = {Marko Bertogna and
Federico Terraneo and
Federico Reghenzani},
title = {Multi-Requirement Enforcement of Non-Functional Properties on MPSoCs
Using Enforcement FSMs - {A} Case Study},
booktitle = {Third Workshop on Next Generation Real-Time Embedded Systems, NG-RES@HiPEAC
2022, June 22, 2022, Budapest, Hungary},
series = {OASIcs},
volume = {98},
pages = {2:1--2:13},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2022},
url = {https://doi.org/10.4230/OASIcs.NG-RES.2022.2},
doi = {10.4230/OASICS.NG-RES.2022.2},
timestamp = {Mon, 13 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/EsperWT22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/JebaliMWCZ22,
author = {Fatma Jebali and
Oumaima Matoussi and
Arief Wicaksana and
Amir Charif and
Lilia Zaourar},
title = {Decoupling processor and memory hierarchy simulators for efficient
design space exploration},
booktitle = {DroneSE and {RAPIDO} '22: System Engineering for constrained embedded
systems, Budapest Hungary, January 17 - 19, 2022},
pages = {47--52},
publisher = {{ACM}},
year = {2022},
url = {https://doi.org/10.1145/3522784.3522796},
doi = {10.1145/3522784.3522796},
timestamp = {Tue, 30 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/JebaliMWCZ22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/KhernacheBBM22,
author = {Mohammed Bey Ahmed Khernache and
Jalil Boukhobza and
Yahia Benmoussa and
Daniel M{\'{e}}nard},
editor = {Francesca Palumbo and
Jo{\~{a}}o Bispo and
Stefano Cherubin},
title = {Energy-Aware {HEVC} Software Decoding On Mobile Heterogeneous Multi-Cores
Architectures},
booktitle = {13th Workshop on Parallel Programming and Run-Time Management Techniques
for Many-Core Architectures and 11th Workshop on Design Tools and
Architectures for Multicore Embedded Computing Platforms, {PARMA-DITAM}
2022, June 22, 2022, Budapest, Hungary},
series = {OASIcs},
volume = {100},
pages = {4:1--4:13},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2022},
url = {https://doi.org/10.4230/OASIcs.PARMA-DITAM.2022.4},
doi = {10.4230/OASICS.PARMA-DITAM.2022.4},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/KhernacheBBM22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/LevaFS22,
author = {Alberto Leva and
Simone Formentin and
Silvano Seva},
editor = {Marko Bertogna and
Federico Terraneo and
Federico Reghenzani},
title = {Overlapping-Horizon {MPC:} {A} Novel Approach to Computational Constraints
in Real-Time Predictive Control},
booktitle = {Third Workshop on Next Generation Real-Time Embedded Systems, NG-RES@HiPEAC
2022, June 22, 2022, Budapest, Hungary},
series = {OASIcs},
volume = {98},
pages = {3:1--3:10},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2022},
url = {https://doi.org/10.4230/OASIcs.NG-RES.2022.3},
doi = {10.4230/OASICS.NG-RES.2022.3},
timestamp = {Mon, 13 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/LevaFS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/MagnaniD0A22,
author = {Gabriele Magnani and
Lev Denisov and
Daniele Cattaneo and
Giovanni Agosta},
editor = {Francesca Palumbo and
Jo{\~{a}}o Bispo and
Stefano Cherubin},
title = {Precision Tuning in Parallel Applications},
booktitle = {13th Workshop on Parallel Programming and Run-Time Management Techniques
for Many-Core Architectures and 11th Workshop on Design Tools and
Architectures for Multicore Embedded Computing Platforms, {PARMA-DITAM}
2022, June 22, 2022, Budapest, Hungary},
series = {OASIcs},
volume = {100},
pages = {5:1--5:9},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2022},
url = {https://doi.org/10.4230/OASIcs.PARMA-DITAM.2022.5},
doi = {10.4230/OASICS.PARMA-DITAM.2022.5},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/MagnaniD0A22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/RaliteraG22,
author = {Tahina Ralitera and
{\"{O}}nder G{\"{u}}rcan},
title = {On Using Blockchains for Beyond Visual Line of Sight {(BVLOS)} Drones
Operation: An Architectural Study},
booktitle = {DroneSE and {RAPIDO} '22: System Engineering for constrained embedded
systems, Budapest Hungary, January 17 - 19, 2022},
pages = {27--32},
publisher = {{ACM}},
year = {2022},
url = {https://doi.org/10.1145/3522784.3522794},
doi = {10.1145/3522784.3522794},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/RaliteraG22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/RattoESRP22,
author = {Francesco Ratto and
Stefano Esposito and
Carlo Sau and
Luigi Raffo and
Francesca Palumbo},
editor = {Francesca Palumbo and
Jo{\~{a}}o Bispo and
Stefano Cherubin},
title = {Multithread Accelerators on FPGAs: {A} Dataflow-Based Approach},
booktitle = {13th Workshop on Parallel Programming and Run-Time Management Techniques
for Many-Core Architectures and 11th Workshop on Design Tools and
Architectures for Multicore Embedded Computing Platforms, {PARMA-DITAM}
2022, June 22, 2022, Budapest, Hungary},
series = {OASIcs},
volume = {100},
pages = {6:1--6:14},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2022},
url = {https://doi.org/10.4230/OASIcs.PARMA-DITAM.2022.6},
doi = {10.4230/OASICS.PARMA-DITAM.2022.6},
timestamp = {Sat, 02 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/RattoESRP22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/RuaroM22,
author = {Marcelo Ruaro and
Kevin J. M. Martin},
title = {ManyGUI: {A} Graphical Tool to Accelerate Many-core Debugging Through
Communication, Memory, and Energy Profiling},
booktitle = {DroneSE and {RAPIDO} '22: System Engineering for constrained embedded
systems, Budapest Hungary, January 17 - 19, 2022},
pages = {39--46},
publisher = {{ACM}},
year = {2022},
url = {https://doi.org/10.1145/3522784.3522791},
doi = {10.1145/3522784.3522791},
timestamp = {Tue, 30 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/RuaroM22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/SafaOCG22,
author = {Ali Safa and
Ilja Ocket and
Francky Catthoor and
Georges G. E. Gielen},
title = {Exploring Cross-fusion and Curriculum Learning for Multi-modal Human
Detection on Drones},
booktitle = {DroneSE and {RAPIDO} '22: System Engineering for constrained embedded
systems, Budapest Hungary, January 17 - 19, 2022},
pages = {1--7},
publisher = {{ACM}},
year = {2022},
url = {https://doi.org/10.1145/3522784.3522785},
doi = {10.1145/3522784.3522785},
timestamp = {Tue, 30 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/SafaOCG22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/ScuttariC0TA22,
author = {Michele Scuttari and
Nicola Camillucci and
Daniele Cattaneo and
Federico Terraneo and
Giovanni Agosta},
editor = {Francesca Palumbo and
Jo{\~{a}}o Bispo and
Stefano Cherubin},
title = {Efficient Memory Management for Modelica Simulations},
booktitle = {13th Workshop on Parallel Programming and Run-Time Management Techniques
for Many-Core Architectures and 11th Workshop on Design Tools and
Architectures for Multicore Embedded Computing Platforms, {PARMA-DITAM}
2022, June 22, 2022, Budapest, Hungary},
series = {OASIcs},
volume = {100},
pages = {7:1--7:13},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2022},
url = {https://doi.org/10.4230/OASIcs.PARMA-DITAM.2022.7},
doi = {10.4230/OASICS.PARMA-DITAM.2022.7},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/ScuttariC0TA22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/SeveraBNBMF22,
author = {Ondrej Severa and
Zdenek Boucek and
Petr Neduchal and
Luk{\'{a}}s Bl{\'{a}}ha and
Tom{\'{a}}s Myslivec and
Miroslav Fl{\'{\i}}dr},
title = {Droneport: From Concept To Simulation},
booktitle = {DroneSE and {RAPIDO} '22: System Engineering for constrained embedded
systems, Budapest Hungary, January 17 - 19, 2022},
pages = {33--38},
publisher = {{ACM}},
year = {2022},
url = {https://doi.org/10.1145/3522784.3522800},
doi = {10.1145/3522784.3522800},
timestamp = {Tue, 30 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/SeveraBNBMF22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/TumeoACL0AMCLM22,
author = {Antonino Tumeo and
Nicolas Bohm Agostini and
Serena Curzel and
Ankur Limaye and
Cheng Tan and
Vinay Amatya and
Marco Minutoli and
Vito Giovanni Castellana and
Ang Li and
Joseph B. Manzano},
editor = {Francesca Palumbo and
Jo{\~{a}}o Bispo and
Stefano Cherubin},
title = {SO(DA)\({}^{\mbox{2}}\): End-to-end Generation of Specialized Reconfigurable
Architectures (Invited Talk)},
booktitle = {13th Workshop on Parallel Programming and Run-Time Management Techniques
for Many-Core Architectures and 11th Workshop on Design Tools and
Architectures for Multicore Embedded Computing Platforms, {PARMA-DITAM}
2022, June 22, 2022, Budapest, Hungary},
series = {OASIcs},
volume = {100},
pages = {1:1--1:15},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2022},
url = {https://doi.org/10.4230/OASIcs.PARMA-DITAM.2022.1},
doi = {10.4230/OASICS.PARMA-DITAM.2022.1},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/TumeoACL0AMCLM22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/X22,
editor = {Francesca Palumbo and
Jo{\~{a}}o Bispo and
Stefano Cherubin},
title = {Front Matter, Table of Contents, Preface, Conference Organization},
booktitle = {13th Workshop on Parallel Programming and Run-Time Management Techniques
for Many-Core Architectures and 11th Workshop on Design Tools and
Architectures for Multicore Embedded Computing Platforms, {PARMA-DITAM}
2022, June 22, 2022, Budapest, Hungary},
series = {OASIcs},
volume = {100},
pages = {0:1--0:8},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2022},
url = {https://doi.org/10.4230/OASIcs.PARMA-DITAM.2022.0},
doi = {10.4230/OASICS.PARMA-DITAM.2022.0},
timestamp = {Thu, 09 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/X22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/X22a,
editor = {Marko Bertogna and
Federico Terraneo and
Federico Reghenzani},
title = {Front Matter, Table of Contents, Preface, Conference Organization},
booktitle = {Third Workshop on Next Generation Real-Time Embedded Systems, NG-RES@HiPEAC
2022, June 22, 2022, Budapest, Hungary},
series = {OASIcs},
volume = {98},
pages = {0:1--0:10},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2022},
url = {https://doi.org/10.4230/OASIcs.NG-RES.2022.0},
doi = {10.4230/OASICS.NG-RES.2022.0},
timestamp = {Mon, 13 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/X22a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/ZamacolaO0T22,
author = {Rafael Zamacola and
Andr{\'{e}}s Otero and
Alfonso Rodr{\'{\i}}guez and
Eduardo de la Torre},
editor = {Francesca Palumbo and
Jo{\~{a}}o Bispo and
Stefano Cherubin},
title = {Just-In-Time Composition of Reconfigurable Overlays (Invited Talk)},
booktitle = {13th Workshop on Parallel Programming and Run-Time Management Techniques
for Many-Core Architectures and 11th Workshop on Design Tools and
Architectures for Multicore Embedded Computing Platforms, {PARMA-DITAM}
2022, June 22, 2022, Budapest, Hungary},
series = {OASIcs},
volume = {100},
pages = {2:1--2:13},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2022},
url = {https://doi.org/10.4230/OASIcs.PARMA-DITAM.2022.2},
doi = {10.4230/OASICS.PARMA-DITAM.2022.2},
timestamp = {Thu, 09 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/ZamacolaO0T22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/hipeac/2022dronese,
title = {DroneSE and {RAPIDO} '22: System Engineering for constrained embedded
systems, Budapest Hungary, January 17 - 19, 2022},
publisher = {{ACM}},
year = {2022},
url = {https://doi.org/10.1145/3522784},
doi = {10.1145/3522784},
isbn = {978-1-4503-9566-3},
timestamp = {Tue, 30 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/2022dronese.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/hipeac/2022ngres,
editor = {Marko Bertogna and
Federico Terraneo and
Federico Reghenzani},
title = {Third Workshop on Next Generation Real-Time Embedded Systems, NG-RES@HiPEAC
2022, June 22, 2022, Budapest, Hungary},
series = {OASIcs},
volume = {98},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2022},
url = {https://www.dagstuhl.de/dagpub/978-3-95977-221-1},
isbn = {978-3-95977-221-1},
timestamp = {Mon, 13 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/2022ngres.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/hipeac/2022parma,
editor = {Francesca Palumbo and
Jo{\~{a}}o Bispo and
Stefano Cherubin},
title = {13th Workshop on Parallel Programming and Run-Time Management Techniques
for Many-Core Architectures and 11th Workshop on Design Tools and
Architectures for Multicore Embedded Computing Platforms, {PARMA-DITAM}
2022, June 22, 2022, Budapest, Hungary},
series = {OASIcs},
volume = {100},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2022},
url = {https://www.dagstuhl.de/dagpub/978-3-95977-231-0},
isbn = {978-3-95977-231-0},
timestamp = {Thu, 09 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/2022parma.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/BouhaliONC21,
author = {Noureddine Bouhali and
Hamza Ouarnoughi and
Sma{\"{\i}}l Niar and
Abdessamad Ait El Cadi},
title = {Execution Time Modeling for {CNN} Inference on Embedded GPUs},
booktitle = {DroneSE and {RAPIDO} '21: Methods and Tools, Budapest, Hungary, January
18, 2021},
pages = {59--65},
publisher = {{ACM}},
year = {2021},
url = {https://doi.org/10.1145/3444950.3447284},
doi = {10.1145/3444950.3447284},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/BouhaliONC21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/BouraouiJC21,
author = {Hasna Bouraoui and
Chadlia Jerad and
Jer{\'{o}}nimo Castrill{\'{o}}n},
editor = {Jo{\~{a}}o Bispo and
Stefano Cherubin and
Jos{\'{e}} Flich},
title = {Towards Adaptive Multi-Alternative Process Network},
booktitle = {12th Workshop on Parallel Programming and Run-Time Management Techniques
for Many-core Architectures and 10th Workshop on Design Tools and
Architectures for Multicore Embedded Computing Platforms, {PARMA-DITAM}
2021, January 19, 2021, Budapest, Hungary},
series = {OASIcs},
volume = {88},
pages = {1:1--1:11},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2021},
url = {https://doi.org/10.4230/OASIcs.PARMA-DITAM.2021.1},
doi = {10.4230/OASICS.PARMA-DITAM.2021.1},
timestamp = {Tue, 02 Mar 2021 22:30:50 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/BouraouiJC21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/CappuzzoPMTL21,
author = {Federico Cappuzzo and
Kenedy Matiasso Portella and
Jean{-}Patrick Mascom{\`{e}}re and
Guillaume Thalmann and
Rapha{\"{e}}l Lallement},
title = {System Simulation for Autonomous {UAV} Design},
booktitle = {DroneSE and {RAPIDO} '21: Methods and Tools, Budapest, Hungary, January
18, 2021},
pages = {36--45},
publisher = {{ACM}},
year = {2021},
url = {https://doi.org/10.1145/3444950.3444952},
doi = {10.1145/3444950.3444952},
timestamp = {Fri, 22 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/CappuzzoPMTL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/ColonnelliCEPSA21,
author = {Iacopo Colonnelli and
Barbara Cantalupo and
Roberto Esposito and
Matteo Pennisi and
Concetto Spampinato and
Marco Aldinucci},
editor = {Jo{\~{a}}o Bispo and
Stefano Cherubin and
Jos{\'{e}} Flich},
title = {{HPC} Application Cloudification: The StreamFlow Toolkit (Invited
Paper)},
booktitle = {12th Workshop on Parallel Programming and Run-Time Management Techniques
for Many-core Architectures and 10th Workshop on Design Tools and
Architectures for Multicore Embedded Computing Platforms, {PARMA-DITAM}
2021, January 19, 2021, Budapest, Hungary},
series = {OASIcs},
volume = {88},
pages = {5:1--5:13},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2021},
url = {https://doi.org/10.4230/OASIcs.PARMA-DITAM.2021.5},
doi = {10.4230/OASICS.PARMA-DITAM.2021.5},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/ColonnelliCEPSA21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/CorradiAS21,
author = {Federico Corradi and
Guido Adriaans and
Sander Stuijk},
title = {Gyro: {A} Digital Spiking Neural Network Architecture for Multi-Sensory
Data Analytics},
booktitle = {DroneSE and {RAPIDO} '21: Methods and Tools, Budapest, Hungary, January
18, 2021},
pages = {9--15},
publisher = {{ACM}},
year = {2021},
url = {https://doi.org/10.1145/3444950.3444951},
doi = {10.1145/3444950.3444951},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/CorradiAS21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/EisoldtHTFVWGRP21,
author = {Marc Eisoldt and
Steffen Hinderink and
Marco Tassemeier and
Marcel Flottmann and
Juri Vana and
Thomas Wiemann and
Julian Gaal and
Marc Rothmann and
Mario Porrmann},
title = {ReconfROS: Running {ROS} on Reconfigurable SoCs},
booktitle = {DroneSE and {RAPIDO} '21: Methods and Tools, Budapest, Hungary, January
18, 2021},
pages = {16--21},
publisher = {{ACM}},
year = {2021},
url = {https://doi.org/10.1145/3444950.3444959},
doi = {10.1145/3444950.3444959},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/EisoldtHTFVWGRP21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/EsperWT21,
author = {Khalil Esper and
Stefan Wildermann and
J{\"{u}}rgen Teich},
editor = {Marko Bertogna and
Federico Terraneo},
title = {A Comparative Evaluation of Latency-Aware Energy Optimization Approaches
in Many-Core Systems (Invited Paper)},
booktitle = {Second Workshop on Next Generation Real-Time Embedded Systems, NG-RES@HiPEAC
2021, January 20, 2021, Budapest, Hungary},
series = {OASIcs},
volume = {87},
pages = {1:1--1:12},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2021},
url = {https://doi.org/10.4230/OASIcs.NG-RES.2021.1},
doi = {10.4230/OASICS.NG-RES.2021.1},
timestamp = {Thu, 16 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/EsperWT21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/FerikoglouMTXS21,
author = {Aggelos Ferikoglou and
Dimosthenis Masouros and
Achilleas Tzenetopoulos and
Sotirios Xydis and
Dimitrios Soudris},
editor = {Jo{\~{a}}o Bispo and
Stefano Cherubin and
Jos{\'{e}} Flich},
title = {Resource Aware {GPU} Scheduling in Kubernetes Infrastructure},
booktitle = {12th Workshop on Parallel Programming and Run-Time Management Techniques
for Many-core Architectures and 10th Workshop on Design Tools and
Architectures for Multicore Embedded Computing Platforms, {PARMA-DITAM}
2021, January 19, 2021, Budapest, Hungary},
series = {OASIcs},
volume = {88},
pages = {4:1--4:12},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2021},
url = {https://doi.org/10.4230/OASIcs.PARMA-DITAM.2021.4},
doi = {10.4230/OASICS.PARMA-DITAM.2021.4},
timestamp = {Tue, 02 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/FerikoglouMTXS21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/FinkhauserL21,
author = {Jens Finkh{\"{a}}user and
Morten Larsen},
title = {Reliable Command, Control and Communication Links for Unmanned Aircraft
Systems: Towards compliance of commercial drones},
booktitle = {DroneSE and {RAPIDO} '21: Methods and Tools, Budapest, Hungary, January
18, 2021},
pages = {22--28},
publisher = {{ACM}},
year = {2021},
url = {https://doi.org/10.1145/3444950.3444954},
doi = {10.1145/3444950.3444954},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/FinkhauserL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/Gutierrez-Gaitan21,
author = {Miguel Guti{\'{e}}rrez{-}Gait{\'{a}}n and
Lu{\'{\i}}s Almeida and
Pedro M. Santos and
Patrick Meumeu Yomsi},
editor = {Marko Bertogna and
Federico Terraneo},
title = {{EDF} Scheduling and Minimal-Overlap Shortest-Path Routing for Real-Time
{TSCH} Networks},
booktitle = {Second Workshop on Next Generation Real-Time Embedded Systems, NG-RES@HiPEAC
2021, January 20, 2021, Budapest, Hungary},
series = {OASIcs},
volume = {87},
pages = {2:1--2:12},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2021},
url = {https://doi.org/10.4230/OASIcs.NG-RES.2021.2},
doi = {10.4230/OASICS.NG-RES.2021.2},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/Gutierrez-Gaitan21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/IrvingPBP21,
author = {Samuel Irving and
Lu Peng and
Costas Busch and
Jih{-}Kwon Peir},
editor = {Jo{\~{a}}o Bispo and
Stefano Cherubin and
Jos{\'{e}} Flich},
title = {BifurKTM: Approximately Consistent Distributed Transactional Memory
for GPUs},
booktitle = {12th Workshop on Parallel Programming and Run-Time Management Techniques
for Many-core Architectures and 10th Workshop on Design Tools and
Architectures for Multicore Embedded Computing Platforms, {PARMA-DITAM}
2021, January 19, 2021, Budapest, Hungary},
series = {OASIcs},
volume = {88},
pages = {2:1--2:15},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2021},
url = {https://doi.org/10.4230/OASIcs.PARMA-DITAM.2021.2},
doi = {10.4230/OASICS.PARMA-DITAM.2021.2},
timestamp = {Thu, 09 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/IrvingPBP21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/JungklassB21,
author = {Philipp Jungklass and
Mladen Berekovic},
editor = {Marko Bertogna and
Federico Terraneo},
title = {Static Allocation of Basic Blocks Based on Runtime and Memory Requirements
in Embedded Real-Time Systems with Hierarchical Memory Layout},
booktitle = {Second Workshop on Next Generation Real-Time Embedded Systems, NG-RES@HiPEAC
2021, January 20, 2021, Budapest, Hungary},
series = {OASIcs},
volume = {87},
pages = {3:1--3:14},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2021},
url = {https://doi.org/10.4230/OASIcs.NG-RES.2021.3},
doi = {10.4230/OASICS.NG-RES.2021.3},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/JungklassB21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/MadronalPCM21,
author = {Daniel Madro{\~{n}}al and
Francesca Palumbo and
Alessandro Capotondi and
Andrea Marongiu},
title = {Unmanned Vehicles in Smart Farming: a Survey and a Glance at Future
Horizons},
booktitle = {DroneSE and {RAPIDO} '21: Methods and Tools, Budapest, Hungary, January
18, 2021},
pages = {1--8},
publisher = {{ACM}},
year = {2021},
url = {https://doi.org/10.1145/3444950.3444958},
doi = {10.1145/3444950.3444958},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/MadronalPCM21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/Magnani0CA21,
author = {Gabriele Magnani and
Daniele Cattaneo and
Michele Chiari and
Giovanni Agosta},
editor = {Jo{\~{a}}o Bispo and
Stefano Cherubin and
Jos{\'{e}} Flich},
title = {The Impact of Precision Tuning on Embedded Systems Performance: {A}
Case Study on Field-Oriented Control},
booktitle = {12th Workshop on Parallel Programming and Run-Time Management Techniques
for Many-core Architectures and 10th Workshop on Design Tools and
Architectures for Multicore Embedded Computing Platforms, {PARMA-DITAM}
2021, January 19, 2021, Budapest, Hungary},
series = {OASIcs},
volume = {88},
pages = {3:1--3:13},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2021},
url = {https://doi.org/10.4230/OASIcs.PARMA-DITAM.2021.3},
doi = {10.4230/OASICS.PARMA-DITAM.2021.3},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/Magnani0CA21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/MenardGHKRTC21,
author = {Christian Menard and
Andr{\'{e}}s Goens and
Gerald Hempel and
Robert Khasanov and
Julian Robledo and
Felix Teweleitt and
Jer{\'{o}}nimo Castrill{\'{o}}n},
title = {Mocasin - Rapid Prototyping of Rapid Prototyping Tools: {A} Framework
for Exploring New Approaches in Mapping Software to Heterogeneous
Multi-cores},
booktitle = {DroneSE and {RAPIDO} '21: Methods and Tools, Budapest, Hungary, January
18, 2021},
pages = {66--73},
publisher = {{ACM}},
year = {2021},
url = {https://doi.org/10.1145/3444950.3447285},
doi = {10.1145/3444950.3447285},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/MenardGHKRTC21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/MirkaPSG21,
author = {Maxime Mirka and
Maxime France{-}Pillois and
Gilles Sassatelli and
Abdoulaye Gamati{\'{e}}},
title = {GANNoC: {A} Framework for Automatic Generation of NoC Topologies using
Generative Adversarial Networks},
booktitle = {DroneSE and {RAPIDO} '21: Methods and Tools, Budapest, Hungary, January
18, 2021},
pages = {51--58},
publisher = {{ACM}},
year = {2021},
url = {https://doi.org/10.1145/3444950.3447283},
doi = {10.1145/3444950.3447283},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/MirkaPSG21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/RadermacherMHN21,
author = {Ansgar Radermacher and
Matteo Morelli and
Mahmoud Hussein and
R{\'{e}}da Nouacer},
title = {Designing Drone Systems with Papyrus for Robotics},
booktitle = {DroneSE and {RAPIDO} '21: Methods and Tools, Budapest, Hungary, January
18, 2021},
pages = {29--35},
publisher = {{ACM}},
year = {2021},
url = {https://doi.org/10.1145/3444950.3444956},
doi = {10.1145/3444950.3444956},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/RadermacherMHN21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/RubattuPBP21,
author = {Claudio Rubattu and
Francesca Palumbo and
Shuvra S. Bhattacharyya and
Maxime Pelcat},
title = {PathTracing: Raising the Level of Understanding of Processing Latency
in Heterogeneous MPSoCs},
booktitle = {DroneSE and {RAPIDO} '21: Methods and Tools, Budapest, Hungary, January
18, 2021},
pages = {46--50},
publisher = {{ACM}},
year = {2021},
url = {https://doi.org/10.1145/3444950.3447282},
doi = {10.1145/3444950.3447282},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/RubattuPBP21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/SevaFL21,
author = {Silvano Seva and
William Fornaciari and
Alberto Leva},
editor = {Marko Bertogna and
Federico Terraneo},
title = {Event-Based Control Enters the Real-Time World: Perspectives and Pitfalls},
booktitle = {Second Workshop on Next Generation Real-Time Embedded Systems, NG-RES@HiPEAC
2021, January 20, 2021, Budapest, Hungary},
series = {OASIcs},
volume = {87},
pages = {4:1--4:11},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2021},
url = {https://doi.org/10.4230/OASIcs.NG-RES.2021.4},
doi = {10.4230/OASICS.NG-RES.2021.4},
timestamp = {Thu, 16 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/SevaFL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/VillaescusaRH21,
author = {David Garc{\'{\i}}a Villaescusa and
Mario Aldea Rivas and
Michael Gonz{\'{a}}lez Harbour},
editor = {Marko Bertogna and
Federico Terraneo},
title = {M2OS-Mc: An {RTOS} for Many-Core Processors},
booktitle = {Second Workshop on Next Generation Real-Time Embedded Systems, NG-RES@HiPEAC
2021, January 20, 2021, Budapest, Hungary},
series = {OASIcs},
volume = {87},
pages = {5:1--5:13},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2021},
url = {https://doi.org/10.4230/OASIcs.NG-RES.2021.5},
doi = {10.4230/OASICS.NG-RES.2021.5},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/VillaescusaRH21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/X21,
editor = {Marko Bertogna and
Federico Terraneo},
title = {Front Matter, Table of Contents, Preface, Conference Organization},
booktitle = {Second Workshop on Next Generation Real-Time Embedded Systems, NG-RES@HiPEAC
2021, January 20, 2021, Budapest, Hungary},
series = {OASIcs},
volume = {87},
pages = {0:1--0:10},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2021},
url = {https://doi.org/10.4230/OASIcs.NG-RES.2021.0},
doi = {10.4230/OASICS.NG-RES.2021.0},
timestamp = {Thu, 14 Jan 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/X21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/X21a,
editor = {Jo{\~{a}}o Bispo and
Stefano Cherubin and
Jos{\'{e}} Flich},
title = {Front Matter, Table of Contents, Preface, Conference Organization},
booktitle = {12th Workshop on Parallel Programming and Run-Time Management Techniques
for Many-core Architectures and 10th Workshop on Design Tools and
Architectures for Multicore Embedded Computing Platforms, {PARMA-DITAM}
2021, January 19, 2021, Budapest, Hungary},
series = {OASIcs},
volume = {88},
pages = {0:1--0:10},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2021},
url = {https://doi.org/10.4230/OASIcs.PARMA-DITAM.2021.0},
doi = {10.4230/OASICS.PARMA-DITAM.2021.0},
timestamp = {Tue, 02 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/X21a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/hipeac/2021dronese,
title = {DroneSE and {RAPIDO} '21: Methods and Tools, Budapest, Hungary, January
18, 2021},
publisher = {{ACM}},
year = {2021},
url = {https://doi.org/10.1145/3444950},
doi = {10.1145/3444950},
isbn = {978-1-4503-8952-5},
timestamp = {Fri, 22 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/2021dronese.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/hipeac/2021ngres,
editor = {Marko Bertogna and
Federico Terraneo},
title = {Second Workshop on Next Generation Real-Time Embedded Systems, NG-RES@HiPEAC
2021, January 20, 2021, Budapest, Hungary},
series = {OASIcs},
volume = {87},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2021},
url = {https://www.dagstuhl.de/dagpub/978-3-95977-178-8},
isbn = {978-3-95977-178-8},
timestamp = {Thu, 14 Jan 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/2021ngres.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/hipeac/2021parma,
editor = {Jo{\~{a}}o Bispo and
Stefano Cherubin and
Jos{\'{e}} Flich},
title = {12th Workshop on Parallel Programming and Run-Time Management Techniques
for Many-core Architectures and 10th Workshop on Design Tools and
Architectures for Multicore Embedded Computing Platforms, {PARMA-DITAM}
2021, January 19, 2021, Budapest, Hungary},
series = {OASIcs},
volume = {88},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2021},
url = {https://www.dagstuhl.de/dagpub/978-3-95977-181-8},
isbn = {978-3-95977-181-8},
timestamp = {Tue, 02 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/2021parma.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/000120,
author = {Lu{\'{\i}}s Almeida},
editor = {Marko Bertogna and
Federico Terraneo},
title = {{SDN} for Dynamic Reservations on Real-Time Networks (Invited Talk)},
booktitle = {Workshop on Next Generation Real-Time Embedded Systems, NG-RES@HiPEAC
2020, January 21, 2020, Bologna, Italy},
series = {OASIcs},
volume = {77},
pages = {1:1--1:1},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2020},
url = {https://doi.org/10.4230/OASIcs.NG-RES.2020.1},
doi = {10.4230/OASICS.NG-RES.2020.1},
timestamp = {Tue, 15 Feb 2022 09:40:05 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/000120.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/DobiasCS20,
author = {Petr Dobi{\'{a}}s and
Emmanuel Casseau and
Oliver Sinnen},
title = {Fault-Tolerant Online Scheduling Algorithms for CubeSats},
booktitle = {11th Workshop on Parallel Programming and Run-Time Management Techniques
for Many-core Architectures / 9th Workshop on Design Tools and Architectures
for Multicore Embedded Computing Platforms, PARMA-DITAM@HiPEAC 2020,
Bologna, Italy, January, 2020},
pages = {3:1--3:6},
publisher = {{ACM}},
year = {2020},
url = {https://doi.org/10.1145/3381427.3381430},
doi = {10.1145/3381427.3381430},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/DobiasCS20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/FossatiCCCA20,
author = {Nicola Fossati and
Daniele Cattaneo and
Michele Chiari and
Stefano Cherubin and
Giovanni Agosta},
title = {Automated Precision Tuning in Activity Classification Systems: {A}
Case Study},
booktitle = {11th Workshop on Parallel Programming and Run-Time Management Techniques
for Many-core Architectures / 9th Workshop on Design Tools and Architectures
for Multicore Embedded Computing Platforms, PARMA-DITAM@HiPEAC 2020,
Bologna, Italy, January, 2020},
pages = {5:1--5:6},
publisher = {{ACM}},
year = {2020},
url = {https://doi.org/10.1145/3381427.3381432},
doi = {10.1145/3381427.3381432},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/FossatiCCCA20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/HosseinabadyN20,
author = {Mohammad Hosseinabady and
Jos{\'{e}} L. N{\'{u}}{\~{n}}ez{-}Y{\'{a}}{\~{n}}ez},
title = {Sparse Matrix-Dense Matrix Multiplication on Heterogeneous {CPU+FPGA}
Embedded System},
booktitle = {11th Workshop on Parallel Programming and Run-Time Management Techniques
for Many-core Architectures / 9th Workshop on Design Tools and Architectures
for Multicore Embedded Computing Platforms, PARMA-DITAM@HiPEAC 2020,
Bologna, Italy, January, 2020},
pages = {1:1--1:6},
publisher = {{ACM}},
year = {2020},
url = {https://doi.org/10.1145/3381427.3381428},
doi = {10.1145/3381427.3381428},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/HosseinabadyN20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/MartinsTSBP20,
author = {Jos{\'{e}} Martins and
Adriano Tavares and
Marco Solieri and
Marko Bertogna and
Sandro Pinto},
editor = {Marko Bertogna and
Federico Terraneo},
title = {Bao: {A} Lightweight Static Partitioning Hypervisor for Modern Multi-Core
Embedded Systems},
booktitle = {Workshop on Next Generation Real-Time Embedded Systems, NG-RES@HiPEAC
2020, January 21, 2020, Bologna, Italy},
series = {OASIcs},
volume = {77},
pages = {3:1--3:14},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2020},
url = {https://doi.org/10.4230/OASIcs.NG-RES.2020.3},
doi = {10.4230/OASICS.NG-RES.2020.3},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/MartinsTSBP20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/MuttilloGFP20,
author = {Vittoriano Muttillo and
Paolo Giammatteo and
Giuseppe Fiorilli and
Luigi Pomante},
title = {An OpenMP Parallel Genetic Algorithm for Design Space Exploration
of Heterogeneous Multi-processor Embedded Systems},
booktitle = {11th Workshop on Parallel Programming and Run-Time Management Techniques
for Many-core Architectures / 9th Workshop on Design Tools and Architectures
for Multicore Embedded Computing Platforms, PARMA-DITAM@HiPEAC 2020,
Bologna, Italy, January, 2020},
pages = {4:1--4:6},
publisher = {{ACM}},
year = {2020},
url = {https://doi.org/10.1145/3381427.3381431},
doi = {10.1145/3381427.3381431},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/MuttilloGFP20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/Nunez-YanezNEH20,
author = {Jos{\'{e}} L. N{\'{u}}{\~{n}}ez{-}Y{\'{a}}{\~{n}}ez and
Kris Nikov and
Kerstin Eder and
Mohammad Hosseinabady},
title = {Run-Time Power Modelling in Embedded GPUs with Dynamic Voltage and
Frequency Scaling},
booktitle = {11th Workshop on Parallel Programming and Run-Time Management Techniques
for Many-core Architectures / 9th Workshop on Design Tools and Architectures
for Multicore Embedded Computing Platforms, PARMA-DITAM@HiPEAC 2020,
Bologna, Italy, January, 2020},
pages = {2:1--2:6},
publisher = {{ACM}},
year = {2020},
url = {https://doi.org/10.1145/3381427.3381429},
doi = {10.1145/3381427.3381429},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/Nunez-YanezNEH20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/PourmohseniSWT20,
author = {Behnaz Pourmohseni and
Fedor Smirnov and
Stefan Wildermann and
J{\"{u}}rgen Teich},
editor = {Marko Bertogna and
Federico Terraneo},
title = {Real-Time Task Migration for Dynamic Resource Management in Many-Core
Systems},
booktitle = {Workshop on Next Generation Real-Time Embedded Systems, NG-RES@HiPEAC
2020, January 21, 2020, Bologna, Italy},
series = {OASIcs},
volume = {77},
pages = {5:1--5:14},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2020},
url = {https://doi.org/10.4230/OASIcs.NG-RES.2020.5},
doi = {10.4230/OASICS.NG-RES.2020.5},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/PourmohseniSWT20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/SevaMFL20,
author = {Silvano Seva and
Claudia Esther Lukaschewsky Mauriziano and
William Fornaciari and
Alberto Leva},
editor = {Marko Bertogna and
Federico Terraneo},
title = {A Low Energy {FPGA} Platform for Real-Time Event-Based Control},
booktitle = {Workshop on Next Generation Real-Time Embedded Systems, NG-RES@HiPEAC
2020, January 21, 2020, Bologna, Italy},
series = {OASIcs},
volume = {77},
pages = {4:1--4:11},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2020},
url = {https://doi.org/10.4230/OASIcs.NG-RES.2020.4},
doi = {10.4230/OASICS.NG-RES.2020.4},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/SevaMFL20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/SimonFMT20,
author = {Bertrand Simon and
Joachim Falk and
Nicole Megow and
J{\"{u}}rgen Teich},
editor = {Marko Bertogna and
Federico Terraneo},
title = {Energy Minimization in {DAG} Scheduling on MPSoCs at Run-Time: Theory
and Practice},
booktitle = {Workshop on Next Generation Real-Time Embedded Systems, NG-RES@HiPEAC
2020, January 21, 2020, Bologna, Italy},
series = {OASIcs},
volume = {77},
pages = {2:1--2:13},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2020},
url = {https://doi.org/10.4230/OASIcs.NG-RES.2020.2},
doi = {10.4230/OASICS.NG-RES.2020.2},
timestamp = {Fri, 12 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/SimonFMT20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/X20,
editor = {Marko Bertogna and
Federico Terraneo},
title = {Front Matter, Table of Contents, Preface, Conference Organization},
booktitle = {Workshop on Next Generation Real-Time Embedded Systems, NG-RES@HiPEAC
2020, January 21, 2020, Bologna, Italy},
series = {OASIcs},
volume = {77},
pages = {0:1--0:10},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2020},
url = {https://doi.org/10.4230/OASIcs.NG-RES.2020.0},
doi = {10.4230/OASICS.NG-RES.2020.0},
timestamp = {Tue, 21 Jan 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/X20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/hipeac/2020ngres,
editor = {Marko Bertogna and
Federico Terraneo},
title = {Workshop on Next Generation Real-Time Embedded Systems, NG-RES@HiPEAC
2020, January 21, 2020, Bologna, Italy},
series = {OASIcs},
volume = {77},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2020},
url = {http://www.dagstuhl.de/dagpub/978-3-95977-136-8},
isbn = {978-3-95977-136-8},
timestamp = {Tue, 15 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/2020ngres.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/hipeac/2020parma,
title = {11th Workshop on Parallel Programming and Run-Time Management Techniques
for Many-core Architectures / 9th Workshop on Design Tools and Architectures
for Multicore Embedded Computing Platforms, PARMA-DITAM@HiPEAC 2020,
Bologna, Italy, January, 2020},
publisher = {{ACM}},
year = {2020},
url = {https://doi.org/10.1145/3381427},
doi = {10.1145/3381427},
isbn = {978-1-4503-7545-0},
timestamp = {Tue, 02 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/2020parma.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/AgostaFMPRZ18,
author = {Giovanni Agosta and
William Fornaciari and
Giuseppe Massari and
Anna Pupykina and
Federico Reghenzani and
Michele Zanella},
title = {Managing Heterogeneous Resources in {HPC} Systems},
booktitle = {Proceedings of the 9th Workshop on Parallel Programming and RunTime
Management Techniques for Manycore Architectures and 7th Workshop
on Design Tools and Architectures for Multicore Embedded Computing
Platforms, PARMA-DITAM@HiPEAC 2018, Manchester, United Kingdom, January
23-23, 2018},
pages = {7--12},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3183767.3183769},
doi = {10.1145/3183767.3183769},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/AgostaFMPRZ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/ArabnejadBBC18,
author = {Hamid Arabnejad and
Jo{\~{a}}o Bispo and
Jorge G. Barbosa and
Jo{\~{a}}o M. P. Cardoso},
title = {AutoPar-Clava: An Automatic Parallelization source-to-source tool
for {C} code applications},
booktitle = {Proceedings of the 9th Workshop on Parallel Programming and RunTime
Management Techniques for Manycore Architectures and 7th Workshop
on Design Tools and Architectures for Multicore Embedded Computing
Platforms, PARMA-DITAM@HiPEAC 2018, Manchester, United Kingdom, January
23-23, 2018},
pages = {13--19},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3183767.3183770},
doi = {10.1145/3183767.3183770},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/ArabnejadBBC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/Atabaki18,
author = {Amir Atabaki},
editor = {S{\"{o}}ren Sonntag and
Jos{\'{e}} Manuel Garc{\'{\i}}a Carrasco and
S{\'{e}}bastien Rumley and
Alessandro Cilardo},
title = {Monolithic Optical Interconnects in Zero-Change {CMOS}},
booktitle = {Proceedings of the 3rd International Workshop on Advanced Interconnect
Solutions and Technologies for Emerging Computing Systems, {AISTECS}
2018, Manchester, United Kingdom, January 22-22, 2018},
pages = {4:1--4:5},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3186608.3186612},
doi = {10.1145/3186608.3186612},
timestamp = {Wed, 21 Nov 2018 12:44:20 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/Atabaki18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/BeckerYK018,
author = {Thomas Becker and
Dai Yang and
Tilman K{\"{u}}stner and
Martin Schulz},
editor = {Carsten Trinitis and
Josef Weidendorfer},
title = {Co-Scheduling in a Task-Based Programming Model},
booktitle = {Proceedings of the 3rd Workshop on Co-Scheduling of {HPC} Applications,
COSH@HiPEAC 2018, Manchester, United Kingdom, January 23, 2018},
pages = {9--14},
publisher = {{TUM} Library},
year = {2018},
url = {https://doi.org/10.14459/2018md1428536},
doi = {10.14459/2018MD1428536},
timestamp = {Thu, 19 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/BeckerYK018.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/BlancheL18,
author = {Andreas de Blanche and
Thomas Lundqvist},
editor = {Carsten Trinitis and
Josef Weidendorfer},
title = {Node Sharing for Increased Throughput and Shorter Runtimes - an Industrial
Co-Scheduling Case Study},
booktitle = {Proceedings of the 3rd Workshop on Co-Scheduling of {HPC} Applications,
COSH@HiPEAC 2018, Manchester, United Kingdom, January 23, 2018},
pages = {15--20},
publisher = {{TUM} Library},
year = {2018},
url = {https://doi.org/10.14459/2018md1428537},
doi = {10.14459/2018MD1428537},
timestamp = {Wed, 31 Jan 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/BlancheL18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/BozziGPPSST18,
author = {Luciano Bozzi and
Lorenzo Di Giuseppe and
Luigi Pomante and
Marco Pugliese and
Marco Santic and
Fortunato Santucci and
Walter Tiberti},
editor = {John Goodacre and
Mikel Luj{\'{a}}n and
Giovanni Agosta and
Alessandro Barenghi and
Israel Koren and
Gerardo Pelosi},
title = {TinyWIDS: a WPM-based Intrusion Detection System for TinyOS2.x/802.15.4
Wireless Sensor Networks},
booktitle = {Proceedings of the Fifth Workshop on Cryptography and Security in
Computing Systems, {CS2} 2018, Manchester, United Kingdom, January
24, 2018},
pages = {13--16},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3178291.3178293},
doi = {10.1145/3178291.3178293},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/BozziGPPSST18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/CaloBKFBBBP18,
author = {Giovanna Cal{\`{o}} and
Gaetano Bellanca and
Ali Emre Kaplan and
Franco Fuschini and
Marina Barbiroli and
Michele Bozzetti and
Paolo Bassi and
Vincenzo Petruzzelli},
editor = {S{\"{o}}ren Sonntag and
Jos{\'{e}} Manuel Garc{\'{\i}}a Carrasco and
S{\'{e}}bastien Rumley and
Alessandro Cilardo},
title = {Integrated Vivaldi antennas, an enabling technology for optical wireless
networks on chip},
booktitle = {Proceedings of the 3rd International Workshop on Advanced Interconnect
Solutions and Technologies for Emerging Computing Systems, {AISTECS}
2018, Manchester, United Kingdom, January 22-22, 2018},
pages = {1:1--1:4},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3186608.3186609},
doi = {10.1145/3186608.3186609},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/CaloBKFBBBP18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/CimaBMDJAAC18,
author = {Vojtech Cima and
Stanislav B{\"{o}}hm and
Jan Martinovic and
Jiri Dvorsk{\'{y}} and
Katerina Janurov{\'{a}} and
Tom Vander Aa and
Thomas J. Ashby and
Vladimir I. Chupakhin},
title = {HyperLoom: {A} Platform for Defining and Executing Scientific Pipelines
in Distributed Environments},
booktitle = {Proceedings of the 9th Workshop on Parallel Programming and RunTime
Management Techniques for Manycore Architectures and 7th Workshop
on Design Tools and Architectures for Multicore Embedded Computing
Platforms, PARMA-DITAM@HiPEAC 2018, Manchester, United Kingdom, January
23-23, 2018},
pages = {1--6},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3183767.3183768},
doi = {10.1145/3183767.3183768},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/CimaBMDJAAC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/CourousseBRBJPB18,
author = {Damien Courouss{\'{e}} and
Thierno Barry and
Bruno Robisson and
Nicolas Belleville and
Philippe Jaillon and
Olivier Potin and
H{\'{e}}l{\`{e}}ne Le Bouder and
Jean{-}Louis Lanet and
Karine Heydemann},
editor = {John Goodacre and
Mikel Luj{\'{a}}n and
Giovanni Agosta and
Alessandro Barenghi and
Israel Koren and
Gerardo Pelosi},
title = {All paths lead to Rome: Polymorphic Runtime Code Generation for Embedded
Systems},
booktitle = {Proceedings of the Fifth Workshop on Cryptography and Security in
Computing Systems, {CS2} 2018, Manchester, United Kingdom, January
24, 2018},
pages = {17--18},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3178291.3178296},
doi = {10.1145/3178291.3178296},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/CourousseBRBJPB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/Federico18,
author = {Alessandro Di Federico},
editor = {John Goodacre and
Mikel Luj{\'{a}}n and
Giovanni Agosta and
Alessandro Barenghi and
Israel Koren and
Gerardo Pelosi},
title = {rev.ng: {A} Tale of Reverse Engineering, Dynamic Analysis and Translation
of Binaries Using {QEMU} and {LLVM}},
booktitle = {Proceedings of the Fifth Workshop on Cryptography and Security in
Computing Systems, {CS2} 2018, Manchester, United Kingdom, January
24, 2018},
pages = {20},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3178291.3178297},
doi = {10.1145/3178291.3178297},
timestamp = {Tue, 18 Dec 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/Federico18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/Garcia18,
author = {Flavio D. Garcia},
editor = {John Goodacre and
Mikel Luj{\'{a}}n and
Giovanni Agosta and
Alessandro Barenghi and
Israel Koren and
Gerardo Pelosi},
title = {Automotive Cyber Security: Lessons Learned and Research Challenges},
booktitle = {Proceedings of the Fifth Workshop on Cryptography and Security in
Computing Systems, {CS2} 2018, Manchester, United Kingdom, January
24, 2018},
pages = {19},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3178291.3178295},
doi = {10.1145/3178291.3178295},
timestamp = {Tue, 18 Dec 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/Garcia18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/KalmsHG18,
author = {Lester Kalms and
Tim Hebbeler and
Diana G{\"{o}}hringer},
title = {Automatic OpenCL Code Generation from {LLVM-IR} using Polyhedral Optimization},
booktitle = {Proceedings of the 9th Workshop on Parallel Programming and RunTime
Management Techniques for Manycore Architectures and 7th Workshop
on Design Tools and Architectures for Multicore Embedded Computing
Platforms, PARMA-DITAM@HiPEAC 2018, Manchester, United Kingdom, January
23-23, 2018},
pages = {45--50},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3183767.3183779},
doi = {10.1145/3183767.3183779},
timestamp = {Wed, 21 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/KalmsHG18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/KhasanovGC18,
author = {Robert Khasanov and
Andr{\'{e}}s Goens and
Jer{\'{o}}nimo Castrill{\'{o}}n},
title = {Implicit Data-Parallelism in Kahn Process Networks: Bridging the MacQueen
Gap},
booktitle = {Proceedings of the 9th Workshop on Parallel Programming and RunTime
Management Techniques for Manycore Architectures and 7th Workshop
on Design Tools and Architectures for Multicore Embedded Computing
Platforms, PARMA-DITAM@HiPEAC 2018, Manchester, United Kingdom, January
23-23, 2018},
pages = {20--25},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3183767.3183790},
doi = {10.1145/3183767.3183790},
timestamp = {Wed, 25 Sep 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/KhasanovGC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/LebiednikAKK18,
author = {Brian Lebiednik and
Sergi Abadal and
Hyoukjun Kwon and
Tushar Krishna},
editor = {S{\"{o}}ren Sonntag and
Jos{\'{e}} Manuel Garc{\'{\i}}a Carrasco and
S{\'{e}}bastien Rumley and
Alessandro Cilardo},
title = {Spoofing Prevention via {RF} Power Profiling in Wireless Network-on-Chip},
booktitle = {Proceedings of the 3rd International Workshop on Advanced Interconnect
Solutions and Technologies for Emerging Computing Systems, {AISTECS}
2018, Manchester, United Kingdom, January 22-22, 2018},
pages = {2:1--2:4},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3186608.3186610},
doi = {10.1145/3186608.3186610},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/LebiednikAKK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/MaS18,
author = {Mingze Ma and
Rizos Sakellariou},
title = {Reducing Code Size in Scheduling Synchronous Dataflow Graphs on Multicore
Systems},
booktitle = {Proceedings of the 9th Workshop on Parallel Programming and RunTime
Management Techniques for Manycore Architectures and 7th Workshop
on Design Tools and Architectures for Multicore Embedded Computing
Platforms, PARMA-DITAM@HiPEAC 2018, Manchester, United Kingdom, January
23-23, 2018},
pages = {57--62},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3183767.3183781},
doi = {10.1145/3183767.3183781},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/MaS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/MiomandreHDMDN18,
author = {Hugo Miomandre and
Julien Hasco{\"{e}}t and
Karol Desnos and
Kevin J. M. Martin and
Beno{\^{\i}}t Dupont de Dinechin and
Jean{-}Fran{\c{c}}ois Nezan},
title = {Embedded Runtime for Reconfigurable Dataflow Graphs on Manycore Architectures},
booktitle = {Proceedings of the 9th Workshop on Parallel Programming and RunTime
Management Techniques for Manycore Architectures and 7th Workshop
on Design Tools and Architectures for Multicore Embedded Computing
Platforms, PARMA-DITAM@HiPEAC 2018, Manchester, United Kingdom, January
23-23, 2018},
pages = {51--56},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3183767.3183780},
doi = {10.1145/3183767.3183780},
timestamp = {Wed, 21 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/MiomandreHDMDN18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/MuttilloVP18,
author = {Vittoriano Muttillo and
Giacomo Valente and
Luigi Pomante},
title = {Criticality-driven Design Space Exploration for Mixed-Criticality
Heterogeneous Parallel Embedded Systems},
booktitle = {Proceedings of the 9th Workshop on Parallel Programming and RunTime
Management Techniques for Manycore Architectures and 7th Workshop
on Design Tools and Architectures for Multicore Embedded Computing
Platforms, PARMA-DITAM@HiPEAC 2018, Manchester, United Kingdom, January
23-23, 2018},
pages = {63--68},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3183767.3183782},
doi = {10.1145/3183767.3183782},
timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/MuttilloVP18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/NobreRBCCCA18,
author = {Ricardo Nobre and
Lu{\'{\i}}s Reis and
Jo{\~{a}}o Bispo and
Tiago Carvalho and
Jo{\~{a}}o M. P. Cardoso and
Stefano Cherubin and
Giovanni Agosta},
title = {Aspect-Driven Mixed-Precision Tuning Targeting GPUs},
booktitle = {Proceedings of the 9th Workshop on Parallel Programming and RunTime
Management Techniques for Manycore Architectures and 7th Workshop
on Design Tools and Architectures for Multicore Embedded Computing
Platforms, PARMA-DITAM@HiPEAC 2018, Manchester, United Kingdom, January
23-23, 2018},
pages = {26--31},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3183767.3183776},
doi = {10.1145/3183767.3183776},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/NobreRBCCCA18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/ReisNC18,
author = {Lu{\'{\i}}s Reis and
Ricardo Nobre and
Jo{\~{a}}o M. P. Cardoso},
title = {Impact of Vectorization Over 16-bit Data-Types on GPUs},
booktitle = {Proceedings of the 9th Workshop on Parallel Programming and RunTime
Management Techniques for Manycore Architectures and 7th Workshop
on Design Tools and Architectures for Multicore Embedded Computing
Platforms, PARMA-DITAM@HiPEAC 2018, Manchester, United Kingdom, January
23-23, 2018},
pages = {32--38},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3183767.3183777},
doi = {10.1145/3183767.3183777},
timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/ReisNC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/SchreiberW18,
author = {Martin Schreiber and
Tobias Weinzierl},
editor = {Carsten Trinitis and
Josef Weidendorfer},
title = {A Case Study for a New Invasive Extension of Intel's Threading Building
Blocks},
booktitle = {Proceedings of the 3rd Workshop on Co-Scheduling of {HPC} Applications,
COSH@HiPEAC 2018, Manchester, United Kingdom, January 23, 2018},
pages = {21--26},
publisher = {{TUM} Library},
year = {2018},
url = {https://doi.org/10.14459/2018md1428538},
doi = {10.14459/2018MD1428538},
timestamp = {Thu, 18 Jul 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/SchreiberW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/SyrivelisRKP18,
author = {Dimitris Syrivelis and
Andrea Reale and
Kostas Katrinis and
Christian Pinto},
editor = {S{\"{o}}ren Sonntag and
Jos{\'{e}} Manuel Garc{\'{\i}}a Carrasco and
S{\'{e}}bastien Rumley and
Alessandro Cilardo},
title = {A Software-defined SoC Memory Bus Bridge Architecture for Disaggregated
Computing},
booktitle = {Proceedings of the 3rd International Workshop on Advanced Interconnect
Solutions and Technologies for Emerging Computing Systems, {AISTECS}
2018, Manchester, United Kingdom, January 22-22, 2018},
pages = {3:1--3:4},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3186608.3186611},
doi = {10.1145/3186608.3186611},
timestamp = {Wed, 21 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/SyrivelisRKP18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/TaskinC18,
author = {Halil Kemal Taskin and
Murat Cenk},
editor = {John Goodacre and
Mikel Luj{\'{a}}n and
Giovanni Agosta and
Alessandro Barenghi and
Israel Koren and
Gerardo Pelosi},
title = {Speeding up Curve25519 using Toeplitz Matrix-vector Multiplication},
booktitle = {Proceedings of the Fifth Workshop on Cryptography and Security in
Computing Systems, {CS2} 2018, Manchester, United Kingdom, January
24, 2018},
pages = {1--6},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3178291.3178292},
doi = {10.1145/3178291.3178292},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/TaskinC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/TrinitisW18,
author = {Carsten Trinitis and
Josef Weidendorfer},
editor = {Carsten Trinitis and
Josef Weidendorfer},
title = {Foreword by Editors / Workshop Description / {TPC} List},
booktitle = {Proceedings of the 3rd Workshop on Co-Scheduling of {HPC} Applications,
COSH@HiPEAC 2018, Manchester, United Kingdom, January 23, 2018},
pages = {5--8},
publisher = {{TUM} Library},
year = {2018},
timestamp = {Wed, 31 Jan 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/TrinitisW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/ValenciaOGR18,
author = {Felipe Valencia and
Tobias Oder and
Tim G{\"{u}}neysu and
Francesco Regazzoni},
editor = {John Goodacre and
Mikel Luj{\'{a}}n and
Giovanni Agosta and
Alessandro Barenghi and
Israel Koren and
Gerardo Pelosi},
title = {Exploring the Vulnerability of {R-LWE} Encryption to Fault Attacks},
booktitle = {Proceedings of the Fifth Workshop on Cryptography and Security in
Computing Systems, {CS2} 2018, Manchester, United Kingdom, January
24, 2018},
pages = {7--12},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3178291.3178294},
doi = {10.1145/3178291.3178294},
timestamp = {Tue, 31 Mar 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/ValenciaOGR18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/ZanellaMF18,
author = {Michele Zanella and
Giuseppe Massari and
William Fornaciari},
title = {Enabling Run-Time Managed Distributed Mobile Computing},
booktitle = {Proceedings of the 9th Workshop on Parallel Programming and RunTime
Management Techniques for Manycore Architectures and 7th Workshop
on Design Tools and Architectures for Multicore Embedded Computing
Platforms, PARMA-DITAM@HiPEAC 2018, Manchester, United Kingdom, January
23-23, 2018},
pages = {39--44},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3183767.3183778},
doi = {10.1145/3183767.3183778},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/ZanellaMF18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/hipeac/2018aistecs,
editor = {S{\"{o}}ren Sonntag and
Jos{\'{e}} Manuel Garc{\'{\i}}a Carrasco and
S{\'{e}}bastien Rumley and
Alessandro Cilardo},
title = {Proceedings of the 3rd International Workshop on Advanced Interconnect
Solutions and Technologies for Emerging Computing Systems, {AISTECS}
2018, Manchester, United Kingdom, January 22-22, 2018},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3186608},
doi = {10.1145/3186608},
timestamp = {Wed, 21 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/2018aistecs.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/hipeac/2018cosh,
editor = {Carsten Trinitis and
Josef Weidendorfer},
title = {Proceedings of the 3rd Workshop on Co-Scheduling of {HPC} Applications,
COSH@HiPEAC 2018, Manchester, United Kingdom, January 23, 2018},
publisher = {{TUM} Library},
year = {2018},
timestamp = {Wed, 31 Jan 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/2018cosh.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/hipeac/2018cs,
editor = {John Goodacre and
Mikel Luj{\'{a}}n and
Giovanni Agosta and
Alessandro Barenghi and
Israel Koren and
Gerardo Pelosi},
title = {Proceedings of the Fifth Workshop on Cryptography and Security in
Computing Systems, {CS2} 2018, Manchester, United Kingdom, January
24, 2018},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3178291},
doi = {10.1145/3178291},
isbn = {978-1-4503-6374-7},
timestamp = {Tue, 18 Dec 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/2018cs.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/hipeac/2018parma,
title = {Proceedings of the 9th Workshop on Parallel Programming and RunTime
Management Techniques for Manycore Architectures and 7th Workshop
on Design Tools and Architectures for Multicore Embedded Computing
Platforms, PARMA-DITAM@HiPEAC 2018, Manchester, United Kingdom, January
23-23, 2018},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3183767},
doi = {10.1145/3183767},
isbn = {978-1-4503-6444-7},
timestamp = {Wed, 21 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/2018parma.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/AbdellatifCPJ17,
author = {Karim M. Abdellatif and
Damien Courouss{\'{e}} and
Olivier Potin and
Philippe Jaillon},
editor = {Mats Brorsson and
Zhonghai Lu and
Giovanni Agosta and
Alessandro Barenghi and
Gerardo Pelosi},
title = {Filtering-based {CPA:} a successful side-channel attack against desynchronization
countermeasures},
booktitle = {Proceedings of the Fourth Workshop on Cryptography and Security in
Computing Systems, CS2@HiPEAC 2017, Stockholm, Sweden, January 24,
2017},
pages = {29--32},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3031836.3031842},
doi = {10.1145/3031836.3031842},
timestamp = {Tue, 06 Nov 2018 16:58:21 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/AbdellatifCPJ17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/AbelD17,
author = {Fran{\c{c}}ois Abel and
Andreas Doering},
editor = {S{\"{o}}ren Sonntag and
Jos{\'{e}} Manuel Garc{\'{\i}}a Carrasco and
Jos{\'{e}} Luis Abell{\'{a}}n Miguel and
Daniel M{\"{u}}ller{-}Gritschneder},
title = {Microserver + micro-switch = micro-datacenter},
booktitle = {Proceedings of the 2nd International Workshop on Advanced Interconnect
Solutions and Technologies for Emerging Computing Systems, AISTECS@HiPEAC
2017, Stockholm, Sweden, January 25, 2017},
pages = {3},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3073763.3073772},
doi = {10.1145/3073763.3073772},
timestamp = {Tue, 06 Nov 2018 16:58:22 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/AbelD17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/Auras-Rodriguez17,
author = {Mar{\'{\i}}a H. Auras{-}Rodr{\'{\i}}guez and
Anthony Zimmermann and
Gerd Ascheid and
Rainer Leupers},
title = {Using PEGs for Automatic Extraction of Memory Access Descriptions
to Support Data-Parallel Pattern Recognition},
booktitle = {Proceedings of the 8th Workshop and 6th Workshop on Parallel Programming
and Run-Time Management Techniques for Many-core Architectures and
Design Tools and Architectures for Multicore Embedded Computing Platforms,
PARMA-DITAM@HiPEAC 2017, Stockholm, Sweden, January 25, 2017},
pages = {13--18},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3029580.3029583},
doi = {10.1145/3029580.3029583},
timestamp = {Tue, 06 Nov 2018 16:58:22 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/Auras-Rodriguez17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/BalboniB17,
author = {Marco Balboni and
Davide Bertozzi},
editor = {S{\"{o}}ren Sonntag and
Jos{\'{e}} Manuel Garc{\'{\i}}a Carrasco and
Jos{\'{e}} Luis Abell{\'{a}}n Miguel and
Daniel M{\"{u}}ller{-}Gritschneder},
title = {Transparent lifetime built-in self-testing of networks-on-chip through
the selective non-concurrent testing of their communication channels},
booktitle = {Proceedings of the 2nd International Workshop on Advanced Interconnect
Solutions and Technologies for Emerging Computing Systems, AISTECS@HiPEAC
2017, Stockholm, Sweden, January 25, 2017},
pages = {12--17},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3073763.3073765},
doi = {10.1145/3073763.3073765},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/BalboniB17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/BlancheL17,
author = {Andreas de Blanche and
Thomas Lundqvist},
editor = {Carsten Clauss and
Stefan Lankes and
Carsten Trinitis and
Josef Weidendorfer},
title = {Disallowing Same-program Co-schedules to Improve Efficiency in Quad-core
Servers},
booktitle = {Proceedings of the Joined Workshops {COSH} 2017 and VisorHPC 2017,
COSH/VisorHPC@HiPEAC 2017, Stockholm, Sweden, January 24, 2017},
pages = {13--20},
publisher = {{TUM} Library},
year = {2017},
url = {https://doi.org/10.14459/2017md1344414},
doi = {10.14459/2017MD1344414},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/BlancheL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/ClarkW17,
author = {Kari Clark and
Phill Watt},
editor = {S{\"{o}}ren Sonntag and
Jos{\'{e}} Manuel Garc{\'{\i}}a Carrasco and
Jos{\'{e}} Luis Abell{\'{a}}n Miguel and
Daniel M{\"{u}}ller{-}Gritschneder},
title = {Enabling high performance rack-scale optical switching through global
synchronisation},
booktitle = {Proceedings of the 2nd International Workshop on Advanced Interconnect
Solutions and Technologies for Emerging Computing Systems, AISTECS@HiPEAC
2017, Stockholm, Sweden, January 25, 2017},
pages = {4},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3073763.3073773},
doi = {10.1145/3073763.3073773},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/ClarkW17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/DebnathKNDLL17,
author = {Monobrata Debnath and
Dimitris Konstantinou and
Chrysostomos Nicopoulos and
Giorgos Dimitrakopoulos and
Wei{-}Ming Lin and
Junghee Lee},
editor = {S{\"{o}}ren Sonntag and
Jos{\'{e}} Manuel Garc{\'{\i}}a Carrasco and
Jos{\'{e}} Luis Abell{\'{a}}n Miguel and
Daniel M{\"{u}}ller{-}Gritschneder},
title = {Low-cost congestion management in networks-on-chip using edge and
in-network traffic throttling},
booktitle = {Proceedings of the 2nd International Workshop on Advanced Interconnect
Solutions and Technologies for Emerging Computing Systems, AISTECS@HiPEAC
2017, Stockholm, Sweden, January 25, 2017},
pages = {8--11},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3073763.3073764},
doi = {10.1145/3073763.3073764},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/DebnathKNDLL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/DinechinG17,
author = {Beno{\^{\i}}t Dupont de Dinechin and
Amaury Graillat},
editor = {S{\"{o}}ren Sonntag and
Jos{\'{e}} Manuel Garc{\'{\i}}a Carrasco and
Jos{\'{e}} Luis Abell{\'{a}}n Miguel and
Daniel M{\"{u}}ller{-}Gritschneder},
title = {Network-on-chip service guarantees on the kalray {MPPA-256} bostan
processor},
booktitle = {Proceedings of the 2nd International Workshop on Advanced Interconnect
Solutions and Technologies for Emerging Computing Systems, AISTECS@HiPEAC
2017, Stockholm, Sweden, January 25, 2017},
pages = {35--40},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3073763.3073770},
doi = {10.1145/3073763.3073770},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/DinechinG17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/DoukasXS17,
author = {Michail Doukas and
Sotirios Xydis and
Dimitrios Soudris},
title = {Dataflow Acceleration of scikit-learn Gaussian Process Regression},
booktitle = {Proceedings of the 8th Workshop and 6th Workshop on Parallel Programming
and Run-Time Management Techniques for Many-core Architectures and
Design Tools and Architectures for Multicore Embedded Computing Platforms,
PARMA-DITAM@HiPEAC 2017, Stockholm, Sweden, January 25, 2017},
pages = {1--6},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3029580.3029587},
doi = {10.1145/3029580.3029587},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/DoukasXS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/FanCRHSS17,
author = {Shiqing Fan and
Fang Chen and
Holm Rauchfuss and
Nadav Har'El and
Uwe Schilling and
Nico Struckmann},
editor = {Carsten Clauss and
Stefan Lankes and
Carsten Trinitis and
Josef Weidendorfer},
title = {Towards a Lightweight {RDMA} Para-Virtualization for {HPC}},
booktitle = {Proceedings of the Joined Workshops {COSH} 2017 and VisorHPC 2017,
COSH/VisorHPC@HiPEAC 2017, Stockholm, Sweden, January 24, 2017},
pages = {39--44},
publisher = {{TUM} Library},
year = {2017},
url = {https://doi.org/10.14459/2017md1344417},
doi = {10.14459/2017MD1344417},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/FanCRHSS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/FraserUGBLJV17,
author = {Nicholas J. Fraser and
Yaman Umuroglu and
Giulio Gambardella and
Michaela Blott and
Philip Heng Wai Leong and
Magnus Jahre and
Kees A. Vissers},
title = {Scaling Binarized Neural Networks on Reconfigurable Logic},
booktitle = {Proceedings of the 8th Workshop and 6th Workshop on Parallel Programming
and Run-Time Management Techniques for Many-core Architectures and
Design Tools and Architectures for Multicore Embedded Computing Platforms,
PARMA-DITAM@HiPEAC 2017, Stockholm, Sweden, January 25, 2017},
pages = {25--30},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3029580.3029586},
doi = {10.1145/3029580.3029586},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/FraserUGBLJV17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/FurgelS17,
author = {Igor Furgel and
Viola Saftig},
editor = {Sergey Tverdyshev},
title = {{MILS} Complete Separation Platform Protection Profile},
booktitle = {International Workshop on {MILS:} Architecture and Assurance for Secure
Systems, {MILS} 2017, N{\"{u}}rnberg, Germany, March 14, 2017},
publisher = {Zenodo},
year = {2017},
url = {https://doi.org/10.5281/zenodo.571161},
doi = {10.5281/ZENODO.571161},
timestamp = {Fri, 21 Sep 2018 12:12:34 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/FurgelS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/GentilalMS17,
author = {Miraje Gentilal and
Paulo Martins and
Leonel Sousa},
editor = {Mats Brorsson and
Zhonghai Lu and
Giovanni Agosta and
Alessandro Barenghi and
Gerardo Pelosi},
title = {TrustZone-backed bitcoin wallet},
booktitle = {Proceedings of the Fourth Workshop on Cryptography and Security in
Computing Systems, CS2@HiPEAC 2017, Stockholm, Sweden, January 24,
2017},
pages = {25--28},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3031836.3031841},
doi = {10.1145/3031836.3031841},
timestamp = {Tue, 16 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/GentilalMS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/GurkaynakSM0MB17,
author = {Frank K. G{\"{u}}rkaynak and
Robert Schilling and
Michael Muehlberghuber and
Francesco Conti and
Stefan Mangard and
Luca Benini},
editor = {Mats Brorsson and
Zhonghai Lu and
Giovanni Agosta and
Alessandro Barenghi and
Gerardo Pelosi},
title = {Multi-core data analytics SoC with a flexible 1.76 Gbit/s {AES-XTS}
cryptographic accelerator in 65 nm {CMOS}},
booktitle = {Proceedings of the Fourth Workshop on Cryptography and Security in
Computing Systems, CS2@HiPEAC 2017, Stockholm, Sweden, January 24,
2017},
pages = {19--24},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3031836.3031840},
doi = {10.1145/3031836.3031840},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/GurkaynakSM0MB17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/HuMS17,
author = {Yong Hu and
Daniel M{\"{u}}ller{-}Gritschneder and
Ulf Schlichtmann},
editor = {S{\"{o}}ren Sonntag and
Jos{\'{e}} Manuel Garc{\'{\i}}a Carrasco and
Jos{\'{e}} Luis Abell{\'{a}}n Miguel and
Daniel M{\"{u}}ller{-}Gritschneder},
title = {Model-based framework for networks-on-chip design space exploration},
booktitle = {Proceedings of the 2nd International Workshop on Advanced Interconnect
Solutions and Technologies for Emerging Computing Systems, AISTECS@HiPEAC
2017, Stockholm, Sweden, January 25, 2017},
pages = {32--35},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3073763.3073769},
doi = {10.1145/3073763.3073769},
timestamp = {Wed, 25 Sep 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/HuMS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/KortKR17,
author = {Semen Kort and
Dmitry Kulagin and
Ekaterina Rudina},
editor = {Sergey Tverdyshev},
title = {An approach to Separation of Duties validation for {MILS} security
configurations},
booktitle = {International Workshop on {MILS:} Architecture and Assurance for Secure
Systems, {MILS} 2017, N{\"{u}}rnberg, Germany, March 14, 2017},
publisher = {Zenodo},
year = {2017},
url = {https://doi.org/10.5281/zenodo.571156},
doi = {10.5281/ZENODO.571156},
timestamp = {Fri, 21 Sep 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/KortKR17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/KustnerTWBKJ17,
author = {Tilman K{\"{u}}stner and
Carsten Trinitis and
Josef Weidendorfer and
Andreas Blaszczyk and
Patrik Kaufmann and
Marcus Johansson},
editor = {Carsten Clauss and
Stefan Lankes and
Carsten Trinitis and
Josef Weidendorfer},
title = {On the Applicability of Virtualization in an Industrial {HPC} Environment},
booktitle = {Proceedings of the Joined Workshops {COSH} 2017 and VisorHPC 2017,
COSH/VisorHPC@HiPEAC 2017, Stockholm, Sweden, January 24, 2017},
pages = {33--38},
publisher = {{TUM} Library},
year = {2017},
url = {https://doi.org/10.14459/2017md1344416},
doi = {10.14459/2017MD1344416},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/KustnerTWBKJ17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/LiK17,
author = {Lu Li and
Christoph W. Kessler},
title = {VectorPU: {A} Generic and Efficient Data-container and Component Model
for Transparent Data Transfer on GPU-based Heterogeneous Systems},
booktitle = {Proceedings of the 8th Workshop and 6th Workshop on Parallel Programming
and Run-Time Management Techniques for Many-core Architectures and
Design Tools and Architectures for Multicore Embedded Computing Platforms,
PARMA-DITAM@HiPEAC 2017, Stockholm, Sweden, January 25, 2017},
pages = {7--12},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3029580.3029582},
doi = {10.1145/3029580.3029582},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/LiK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/MeriacY17,
author = {Milosch Meriac and
Joseph Yiu},
editor = {Sergey Tverdyshev},
title = {High-End Security Features for Low-End Microcontrollers},
booktitle = {International Workshop on {MILS:} Architecture and Assurance for Secure
Systems, {MILS} 2017, N{\"{u}}rnberg, Germany, March 14, 2017},
publisher = {Zenodo},
year = {2017},
url = {https://doi.org/10.5281/zenodo.571158},
doi = {10.5281/ZENODO.571158},
timestamp = {Fri, 21 Sep 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/MeriacY17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/MuchGLBW17,
author = {Alexander Much and
Rudolf Grave and
Robert Leibinger and
Martin B{\"{o}}hner and
Elisabeth Waitz},
editor = {Sergey Tverdyshev},
title = {Current Trends and Solutions in Securing Automotive Software},
booktitle = {International Workshop on {MILS:} Architecture and Assurance for Secure
Systems, {MILS} 2017, N{\"{u}}rnberg, Germany, March 14, 2017},
publisher = {Zenodo},
year = {2017},
url = {https://doi.org/10.5281/zenodo.571167},
doi = {10.5281/ZENODO.571167},
timestamp = {Fri, 21 Sep 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/MuchGLBW17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/Mueller17,
author = {Kevin Mueller},
editor = {Sergey Tverdyshev},
title = {Hardening High-Assurance Systems: {MILS} as Software Design for Avionics},
booktitle = {International Workshop on {MILS:} Architecture and Assurance for Secure
Systems, {MILS} 2017, N{\"{u}}rnberg, Germany, March 14, 2017},
publisher = {Zenodo},
year = {2017},
url = {https://doi.org/10.5281/zenodo.571160},
doi = {10.5281/ZENODO.571160},
timestamp = {Fri, 21 Sep 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/Mueller17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/NollW17,
author = {Thomas Noll and
Louis Wachtmeister},
editor = {Sergey Tverdyshev},
title = {Analysing Cryptographically-Masked Information Flows in {MILS-AADL}
Specifications},
booktitle = {International Workshop on {MILS:} Architecture and Assurance for Secure
Systems, {MILS} 2017, N{\"{u}}rnberg, Germany, March 14, 2017},
publisher = {Zenodo},
year = {2017},
url = {https://doi.org/10.5281/zenodo.571173},
doi = {10.5281/ZENODO.571173},
timestamp = {Sat, 05 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/NollW17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/NordhoffB17,
author = {Sven Nordhoff and
Holger Blasum},
editor = {Sergey Tverdyshev},
title = {Ease Standard Compliance by Technical Means via {MILS}},
booktitle = {International Workshop on {MILS:} Architecture and Assurance for Secure
Systems, {MILS} 2017, N{\"{u}}rnberg, Germany, March 14, 2017},
publisher = {Zenodo},
year = {2017},
url = {https://doi.org/10.5281/zenodo.571175},
doi = {10.5281/ZENODO.571175},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/NordhoffB17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/ObaidullahK17,
author = {Muhammad Obaidullah and
Gul N. Khan},
editor = {S{\"{o}}ren Sonntag and
Jos{\'{e}} Manuel Garc{\'{\i}}a Carrasco and
Jos{\'{e}} Luis Abell{\'{a}}n Miguel and
Daniel M{\"{u}}ller{-}Gritschneder},
title = {Optimal application mapping to 2D-mesh NoCs by using a tabu-based
particle swarm methodology},
booktitle = {Proceedings of the 2nd International Workshop on Advanced Interconnect
Solutions and Technologies for Emerging Computing Systems, AISTECS@HiPEAC
2017, Stockholm, Sweden, January 25, 2017},
pages = {17--22},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3073763.3073766},
doi = {10.1145/3073763.3073766},
timestamp = {Fri, 05 Apr 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/ObaidullahK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/Ofori-AttahA17,
author = {Emmanuel Ofori{-}Attah and
Michael Opoku Agyeman},
editor = {S{\"{o}}ren Sonntag and
Jos{\'{e}} Manuel Garc{\'{\i}}a Carrasco and
Jos{\'{e}} Luis Abell{\'{a}}n Miguel and
Daniel M{\"{u}}ller{-}Gritschneder},
title = {A survey of low power NoC design techniques},
booktitle = {Proceedings of the 2nd International Workshop on Advanced Interconnect
Solutions and Technologies for Emerging Computing Systems, AISTECS@HiPEAC
2017, Stockholm, Sweden, January 25, 2017},
pages = {22--27},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3073763.3073767},
doi = {10.1145/3073763.3073767},
timestamp = {Wed, 25 Sep 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/Ofori-AttahA17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/Panziera17,
author = {Jean{-}Pierre Panziera},
editor = {S{\"{o}}ren Sonntag and
Jos{\'{e}} Manuel Garc{\'{\i}}a Carrasco and
Jos{\'{e}} Luis Abell{\'{a}}n Miguel and
Daniel M{\"{u}}ller{-}Gritschneder},
title = {{BXI:} designing a network for eXascale},
booktitle = {Proceedings of the 2nd International Workshop on Advanced Interconnect
Solutions and Technologies for Emerging Computing Systems, AISTECS@HiPEAC
2017, Stockholm, Sweden, January 25, 2017},
pages = {2},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3073763.3073774},
doi = {10.1145/3073763.3073774},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/Panziera17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/PapadakisNKGK17,
author = {Ioannis A. Papadakis and
Konstantinos Nikas and
Vasileios Karakostas and
Georgios I. Goumas and
Nectarios Koziris},
editor = {Carsten Clauss and
Stefan Lankes and
Carsten Trinitis and
Josef Weidendorfer},
title = {Improving QoS and Utilisation in modern multi-core servers with Dynamic
Cache Partitioning},
booktitle = {Proceedings of the Joined Workshops {COSH} 2017 and VisorHPC 2017,
COSH/VisorHPC@HiPEAC 2017, Stockholm, Sweden, January 24, 2017},
pages = {21--26},
publisher = {{TUM} Library},
year = {2017},
url = {https://doi.org/10.14459/2017md1344298},
doi = {10.14459/2017MD1344298},
timestamp = {Wed, 19 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/PapadakisNKGK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/PereiraIS17,
author = {David Pereira and
Aleksandar Ilic and
Leonel Sousa},
title = {On Boosting Energy-Efficiency of Heterogeneous Embedded Systems via
Game Theory},
booktitle = {Proceedings of the 8th Workshop and 6th Workshop on Parallel Programming
and Run-Time Management Techniques for Many-core Architectures and
Design Tools and Architectures for Multicore Embedded Computing Platforms,
PARMA-DITAM@HiPEAC 2017, Stockholm, Sweden, January 25, 2017},
pages = {19--24},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3029580.3029584},
doi = {10.1145/3029580.3029584},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/PereiraIS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/Pereniguez-Garcia17,
author = {Fernando Pere{\~{n}}{\'{\i}}guez{-}Garcia and
Jos{\'{e}} L. Abell{\'{a}}n},
editor = {S{\"{o}}ren Sonntag and
Jos{\'{e}} Manuel Garc{\'{\i}}a Carrasco and
Jos{\'{e}} Luis Abell{\'{a}}n Miguel and
Daniel M{\"{u}}ller{-}Gritschneder},
title = {Secure communications in wireless network-on-chips},
booktitle = {Proceedings of the 2nd International Workshop on Advanced Interconnect
Solutions and Technologies for Emerging Computing Systems, AISTECS@HiPEAC
2017, Stockholm, Sweden, January 25, 2017},
pages = {27--32},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3073763.3073768},
doi = {10.1145/3073763.3073768},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/Pereniguez-Garcia17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/PickartzBL17,
author = {Simon Pickartz and
Jens Breitbart and
Stefan Lankes},
editor = {Carsten Clauss and
Stefan Lankes and
Carsten Trinitis and
Josef Weidendorfer},
title = {Co-scheduling on Upcoming Many-Core Architectures},
booktitle = {Proceedings of the Joined Workshops {COSH} 2017 and VisorHPC 2017,
COSH/VisorHPC@HiPEAC 2017, Stockholm, Sweden, January 24, 2017},
pages = {27--32},
publisher = {{TUM} Library},
year = {2017},
url = {https://doi.org/10.14459/2017md1344415},
doi = {10.14459/2017MD1344415},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/PickartzBL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/PlerosTAVKS17,
author = {Nikos Pleros and
Nikos Terzenidis and
Theoni Alexoudi and
K. Vyrsokinos and
George T. Kanellos and
Dimitris Syrivelis},
editor = {S{\"{o}}ren Sonntag and
Jos{\'{e}} Manuel Garc{\'{\i}}a Carrasco and
Jos{\'{e}} Luis Abell{\'{a}}n Miguel and
Daniel M{\"{u}}ller{-}Gritschneder},
title = {Software-defined board- and chip-level optical interconnects for multi-socket
communication and disaggregated computing},
booktitle = {Proceedings of the 2nd International Workshop on Advanced Interconnect
Solutions and Technologies for Emerging Computing Systems, AISTECS@HiPEAC
2017, Stockholm, Sweden, January 25, 2017},
pages = {6--7},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3073763.3073776},
doi = {10.1145/3073763.3073776},
timestamp = {Wed, 20 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/PlerosTAVKS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/SeuschekSG17,
author = {Hermann Seuschek and
Fabrizio De Santis and
Oscar M. Guillen},
editor = {Mats Brorsson and
Zhonghai Lu and
Giovanni Agosta and
Alessandro Barenghi and
Gerardo Pelosi},
title = {Side-channel leakage aware instruction scheduling},
booktitle = {Proceedings of the Fourth Workshop on Cryptography and Security in
Computing Systems, CS2@HiPEAC 2017, Stockholm, Sweden, January 24,
2017},
pages = {7--12},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3031836.3031838},
doi = {10.1145/3031836.3031838},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/SeuschekSG17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/Shah17,
author = {Syed Ijlal Shah},
editor = {S{\"{o}}ren Sonntag and
Jos{\'{e}} Manuel Garc{\'{\i}}a Carrasco and
Jos{\'{e}} Luis Abell{\'{a}}n Miguel and
Daniel M{\"{u}}ller{-}Gritschneder},
title = {Interconnects for next generation SoC designs},
booktitle = {Proceedings of the 2nd International Workshop on Advanced Interconnect
Solutions and Technologies for Emerging Computing Systems, AISTECS@HiPEAC
2017, Stockholm, Sweden, January 25, 2017},
pages = {1},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3073763.3073771},
doi = {10.1145/3073763.3073771},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/Shah17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/Steiner17,
author = {Wilfred Steiner},
editor = {Sergey Tverdyshev},
title = {Fog Computing as Enabler for the Industrial Internet of Things / Industrie
4.0: Slides},
booktitle = {International Workshop on {MILS:} Architecture and Assurance for Secure
Systems, {MILS} 2017, N{\"{u}}rnberg, Germany, March 14, 2017},
publisher = {Zenodo},
year = {2017},
url = {https://doi.org/10.5281/zenodo.571163},
doi = {10.5281/ZENODO.571163},
timestamp = {Fri, 21 Sep 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/Steiner17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/TaoD17,
author = {Sha Tao and
Elena Dubrova},
editor = {Mats Brorsson and
Zhonghai Lu and
Giovanni Agosta and
Alessandro Barenghi and
Gerardo Pelosi},
title = {Reliable low-overhead arbiter-based physical unclonable functions
for resource-constrained IoT devices},
booktitle = {Proceedings of the Fourth Workshop on Cryptography and Security in
Computing Systems, CS2@HiPEAC 2017, Stockholm, Sweden, January 24,
2017},
pages = {1--6},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3031836.3031837},
doi = {10.1145/3031836.3031837},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/TaoD17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/Tverdyshev17,
author = {Sergey Tverdyshev},
editor = {Sergey Tverdyshev},
title = {Security by Design: Introduction to {MILS}},
booktitle = {International Workshop on {MILS:} Architecture and Assurance for Secure
Systems, {MILS} 2017, N{\"{u}}rnberg, Germany, March 14, 2017},
publisher = {Zenodo},
year = {2017},
url = {https://doi.org/10.5281/zenodo.571164},
doi = {10.5281/ZENODO.571164},
timestamp = {Fri, 21 Sep 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/Tverdyshev17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/Waters17,
author = {Geoff Waters},
editor = {Sergey Tverdyshev},
title = {Hardware enforced separation in embedded multicore SoCs},
booktitle = {International Workshop on {MILS:} Architecture and Assurance for Secure
Systems, {MILS} 2017, N{\"{u}}rnberg, Germany, March 14, 2017},
publisher = {Zenodo},
year = {2017},
url = {https://doi.org/10.5281/zenodo.571172},
doi = {10.5281/ZENODO.571172},
timestamp = {Fri, 21 Sep 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/Waters17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/Wilde17,
author = {Florian Wilde},
editor = {Mats Brorsson and
Zhonghai Lu and
Giovanni Agosta and
Alessandro Barenghi and
Gerardo Pelosi},
title = {Large scale characterization of {SRAM} on infineon {XMC} microcontrollers
as {PUF}},
booktitle = {Proceedings of the Fourth Workshop on Cryptography and Security in
Computing Systems, CS2@HiPEAC 2017, Stockholm, Sweden, January 24,
2017},
pages = {13--18},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3031836.3031839},
doi = {10.1145/3031836.3031839},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/Wilde17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/Wilke17,
author = {Jeremiah J. Wilke},
editor = {S{\"{o}}ren Sonntag and
Jos{\'{e}} Manuel Garc{\'{\i}}a Carrasco and
Jos{\'{e}} Luis Abell{\'{a}}n Miguel and
Daniel M{\"{u}}ller{-}Gritschneder},
title = {Bringing minimal routing back to {HPC} through silicon photonics:
a study of "flexfly" architectures with the structural simulation
toolkit {(SST)}},
booktitle = {Proceedings of the 2nd International Workshop on Advanced Interconnect
Solutions and Technologies for Emerging Computing Systems, AISTECS@HiPEAC
2017, Stockholm, Sweden, January 25, 2017},
pages = {5},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3073763.3073775},
doi = {10.1145/3073763.3073775},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/Wilke17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/YangJHS17,
author = {Yu Yang and
Syed M. A. H. Jafri and
Ahmed Hemani and
Dimitrios Stathis},
title = {MTP-Caffe: Memory, Timing, and Power aware tool for mapping CNNs to
GPUs},
booktitle = {Proceedings of the 8th Workshop and 6th Workshop on Parallel Programming
and Run-Time Management Techniques for Many-core Architectures and
Design Tools and Architectures for Multicore Embedded Computing Platforms,
PARMA-DITAM@HiPEAC 2017, Stockholm, Sweden, January 25, 2017},
pages = {31--36},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3029580.3029585},
doi = {10.1145/3029580.3029585},
timestamp = {Fri, 07 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/YangJHS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/hipeac/2016coshr,
editor = {Carsten Trinitis and
Josef Weidendorfer},
title = {Co-Scheduling of {HPC} Applications [extended versions of all papers
from COSH@HiPEAC 2016, Prague, Czech Republic, January 19, 2016]},
series = {Advances in Parallel Computing},
volume = {28},
publisher = {{IOS} Press},
year = {2017},
isbn = {978-1-61499-729-0},
timestamp = {Wed, 22 Mar 2017 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/2016coshr.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/hipeac/2017aistecs,
editor = {S{\"{o}}ren Sonntag and
Jos{\'{e}} Manuel Garc{\'{\i}}a Carrasco and
Jos{\'{e}} Luis Abell{\'{a}}n Miguel and
Daniel M{\"{u}}ller{-}Gritschneder},
title = {Proceedings of the 2nd International Workshop on Advanced Interconnect
Solutions and Technologies for Emerging Computing Systems, AISTECS@HiPEAC
2017, Stockholm, Sweden, January 25, 2017},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3073763},
doi = {10.1145/3073763},
isbn = {978-1-4503-5226-0},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/2017aistecs.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/hipeac/2017coshvisorhpc,
editor = {Carsten Clauss and
Stefan Lankes and
Carsten Trinitis and
Josef Weidendorfer},
title = {Proceedings of the Joined Workshops {COSH} 2017 and VisorHPC 2017,
COSH/VisorHPC@HiPEAC 2017, Stockholm, Sweden, January 24, 2017},
publisher = {{TUM} Library},
year = {2017},
isbn = {978-3-00-055564-0},
timestamp = {Mon, 06 Feb 2017 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/2017coshvisorhpc.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/hipeac/2017cs,
editor = {Mats Brorsson and
Zhonghai Lu and
Giovanni Agosta and
Alessandro Barenghi and
Gerardo Pelosi},
title = {Proceedings of the Fourth Workshop on Cryptography and Security in
Computing Systems, CS2@HiPEAC 2017, Stockholm, Sweden, January 24,
2017},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3031836},
doi = {10.1145/3031836},
isbn = {978-1-4503-4869-0},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/2017cs.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/hipeac/2017mils,
editor = {Sergey Tverdyshev},
title = {International Workshop on {MILS:} Architecture and Assurance for Secure
Systems, {MILS} 2017, N{\"{u}}rnberg, Germany, March 14, 2017},
publisher = {Zenodo},
year = {2017},
url = {http://mils-workshop-2017.mils.community/},
timestamp = {Fri, 21 Sep 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/2017mils.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/hipeac/2017parma,
title = {Proceedings of the 8th Workshop and 6th Workshop on Parallel Programming
and Run-Time Management Techniques for Many-core Architectures and
Design Tools and Architectures for Multicore Embedded Computing Platforms,
PARMA-DITAM@HiPEAC 2017, Stockholm, Sweden, January 25, 2017},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3029580},
doi = {10.1145/3029580},
isbn = {978-1-4503-4877-5},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/2017parma.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/0003SEUGSZODI16,
author = {Khalid Latif and
Manuel Selva and
Charles Effiong and
Roman Ursu and
Abdoulaye Gamati{\'{e}} and
Gilles Sassatelli and
Leonardo Bonet Zordan and
Luciano Ost and
Piotr Dziurzanski and
Leandro Soares Indrusiak},
title = {Design space exploration for complex automotive applications: an engine
control system case study},
booktitle = {Proceedings of the 2016 Workshop on Rapid Simulation and Performance
Evaluation - Methods and Tools, RAPIDO@HiPEAC 2016, Prague, Czech
Republic, January 18, 2016},
pages = {2:1--2:7},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2852339.2852341},
doi = {10.1145/2852339.2852341},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/0003SEUGSZODI16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/AbdellatifCM16,
author = {Karim M. Abdellatif and
Roselyne Chotin{-}Avot and
Habib Mehrez},
editor = {Martin Palkovic and
Giovanni Agosta and
Alessandro Barenghi and
Israel Koren and
Gerardo Pelosi},
title = {AEGIS-Based Efficient Solution for Secure Reconfiguration of FPGAs},
booktitle = {Proceedings of the Third Workshop on Cryptography and Security in
Computing Systems, CS2@HiPEAC, Prague, Czech Republic, January 20,
2016},
pages = {37--40},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2858930.2858937},
doi = {10.1145/2858930.2858937},
timestamp = {Tue, 06 Nov 2018 16:58:21 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/AbdellatifCM16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/AshouriBPS16,
author = {Amir Hossein Ashouri and
Andrea Bignoli and
Gianluca Palermo and
Cristina Silvano},
editor = {Cristina Silvano and
Jo{\~{a}}o M. P. Cardoso and
Giovanni Agosta and
Michael H{\"{u}}bner},
title = {Predictive modeling methodology for compiler phase-ordering},
booktitle = {Proceedings of the 7th Workshop on Parallel Programming and Run-Time
Management Techniques for Many-core Architectures and the 5th Workshop
on Design Tools and Architectures For Multicore Embedded Computing
Platforms, {PARMA-DITAM} 2016, Prague, Czech Republic, January 18,
2016},
pages = {7--12},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2872421.2872424},
doi = {10.1145/2872421.2872424},
timestamp = {Wed, 28 Apr 2021 16:06:57 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/AshouriBPS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/AzarderakhshK16,
author = {Reza Azarderakhsh and
Koray Karabina},
editor = {Martin Palkovic and
Giovanni Agosta and
Alessandro Barenghi and
Israel Koren and
Gerardo Pelosi},
title = {Efficient Algorithms and Architectures for Double Point Multiplication
on Elliptic Curves},
booktitle = {Proceedings of the Third Workshop on Cryptography and Security in
Computing Systems, CS2@HiPEAC, Prague, Czech Republic, January 20,
2016},
pages = {25--30},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2858930.2858935},
doi = {10.1145/2858930.2858935},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/AzarderakhshK16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/BarryCR16,
author = {Thierno Barry and
Damien Courouss{\'{e}} and
Bruno Robisson},
editor = {Martin Palkovic and
Giovanni Agosta and
Alessandro Barenghi and
Israel Koren and
Gerardo Pelosi},
title = {Compilation of a Countermeasure Against Instruction-Skip Fault Attacks},
booktitle = {Proceedings of the Third Workshop on Cryptography and Security in
Computing Systems, CS2@HiPEAC, Prague, Czech Republic, January 20,
2016},
pages = {1--6},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2858930.2858931},
doi = {10.1145/2858930.2858931},
timestamp = {Sat, 02 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/BarryCR16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/Beringuier-Boher16,
author = {Noemie Beringuier{-}Boher and
Marc Lacruche and
David El{-}Baze and
Jean{-}Max Dutertre and
Jean{-}Baptiste Rigaud and
Philippe Maurine},
editor = {Martin Palkovic and
Giovanni Agosta and
Alessandro Barenghi and
Israel Koren and
Gerardo Pelosi},
title = {Body Biasing Injection Attacks in Practice},
booktitle = {Proceedings of the Third Workshop on Cryptography and Security in
Computing Systems, CS2@HiPEAC, Prague, Czech Republic, January 20,
2016},
pages = {49--54},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2858930.2858940},
doi = {10.1145/2858930.2858940},
timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/Beringuier-Boher16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/BlancheL16,
author = {Andreas de Blanche and
Thomas Lundqvist},
editor = {Carsten Trinitis and
Josef Weidendorfer},
title = {Terrible Twins: {A} Simple Scheme to Avoid Bad Co-Schedules},
booktitle = {Proceedings of the 1st {COSH} Workshop on Co-Scheduling of {HPC} Applications,
COSH@HiPEAC 2016, Prague, Czech Republic, January 19, 2016},
pages = {25--30},
publisher = {{TUM} Library},
year = {2016},
url = {https://doi.org/10.14459/2016md1286952},
doi = {10.14459/2016MD1286952},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/BlancheL16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/BlancheL16a,
author = {Andreas de Blanche and
Thomas Lundqvist},
editor = {Carsten Trinitis and
Josef Weidendorfer},
title = {Initial Formulation of Why Disallowing Same Program Co-Schedules Improves
Performance},
booktitle = {Co-Scheduling of {HPC} Applications [extended versions of all papers
from COSH@HiPEAC 2016, Prague, Czech Republic, January 19, 2016]},
series = {Advances in Parallel Computing},
volume = {28},
pages = {95--113},
publisher = {{IOS} Press},
year = {2016},
url = {https://doi.org/10.3233/978-1-61499-730-6-95},
doi = {10.3233/978-1-61499-730-6-95},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/BlancheL16a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/BreitbartW16,
author = {Jens Breitbart and
Josef Weidendorfer},
editor = {Carsten Trinitis and
Josef Weidendorfer},
title = {Detailed Application Characterization and Its Use for Effective Co-Scheduling},
booktitle = {Co-Scheduling of {HPC} Applications [extended versions of all papers
from COSH@HiPEAC 2016, Prague, Czech Republic, January 19, 2016]},
series = {Advances in Parallel Computing},
volume = {28},
pages = {69--94},
publisher = {{IOS} Press},
year = {2016},
url = {https://doi.org/10.3233/978-1-61499-730-6-69},
doi = {10.3233/978-1-61499-730-6-69},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/BreitbartW16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/CherubinSA16,
author = {Stefano Cherubin and
Michele Scandale and
Giovanni Agosta},
editor = {Cristina Silvano and
Jo{\~{a}}o M. P. Cardoso and
Giovanni Agosta and
Michael H{\"{u}}bner},
title = {Stack size estimation on machine-independent intermediate code for
OpenCL kernels},
booktitle = {Proceedings of the 7th Workshop on Parallel Programming and Run-Time
Management Techniques for Many-core Architectures and the 5th Workshop
on Design Tools and Architectures For Multicore Embedded Computing
Platforms, {PARMA-DITAM} 2016, Prague, Czech Republic, January 18,
2016},
pages = {1--6},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2872421.2872425},
doi = {10.1145/2872421.2872425},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/CherubinSA16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/ClaussME16,
author = {Carsten Clauss and
Thomas Moschny and
Norbert Eicker},
editor = {Carsten Trinitis and
Josef Weidendorfer},
title = {Allocation-Internal Co-Scheduling - Interaction and Orchestration
of Multiple Concurrent {MPI} Sessions},
booktitle = {Co-Scheduling of {HPC} Applications [extended versions of all papers
from COSH@HiPEAC 2016, Prague, Czech Republic, January 19, 2016]},
series = {Advances in Parallel Computing},
volume = {28},
pages = {46--68},
publisher = {{IOS} Press},
year = {2016},
url = {https://doi.org/10.3233/978-1-61499-730-6-46},
doi = {10.3233/978-1-61499-730-6-46},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/ClaussME16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/DelangeNFK16,
author = {Julien Delange and
Min{-}Young Nam and
Peter H. Feiler and
Will Klieber},
editor = {Sergey Tverdyshev},
title = {An Architecture-Centric Process for {MILS} Development},
booktitle = {International Workshop on {MILS:} Architecture and Assurance for Secure
Systems, MILS@HiPEAC 2016, Prague, Czech Republic, January 19, 2016},
publisher = {Zenodo},
year = {2016},
url = {https://doi.org/10.5281/zenodo.47976},
doi = {10.5281/ZENODO.47976},
timestamp = {Thu, 02 Aug 2018 14:39:18 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/DelangeNFK16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/FlasskampSAKJKT16,
author = {Martin Flasskamp and
Gregor Sievers and
Johannes Ax and
Christian Klarhorst and
Thorsten Jungeblut and
Wayne Kelly and
Michael Thies and
Mario Porrmann},
title = {Performance estimation of streaming applications for hierarchical
MPSoCs},
booktitle = {Proceedings of the 2016 Workshop on Rapid Simulation and Performance
Evaluation - Methods and Tools, RAPIDO@HiPEAC 2016, Prague, Czech
Republic, January 18, 2016},
pages = {3:1--3:6},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2852339.2852342},
doi = {10.1145/2852339.2852342},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/FlasskampSAKJKT16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/FornaciariPRMB16,
author = {William Fornaciari and
Gianmario Pozzi and
Federico Reghenzani and
Andrea Marchese and
Mauro Belluschi},
editor = {Cristina Silvano and
Jo{\~{a}}o M. P. Cardoso and
Giovanni Agosta and
Michael H{\"{u}}bner},
title = {Runtime resource management for embedded and {HPC} systems},
booktitle = {Proceedings of the 7th Workshop on Parallel Programming and Run-Time
Management Techniques for Many-core Architectures and the 5th Workshop
on Design Tools and Architectures For Multicore Embedded Computing
Platforms, {PARMA-DITAM} 2016, Prague, Czech Republic, January 18,
2016},
pages = {31--36},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2872421.2893173},
doi = {10.1145/2872421.2893173},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/FornaciariPRMB16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/FournarisSK16,
author = {Apostolos P. Fournaris and
Nicolas Sklavos and
Christos Koulamas},
editor = {Martin Palkovic and
Giovanni Agosta and
Alessandro Barenghi and
Israel Koren and
Gerardo Pelosi},
title = {A High Speed Scalar Multiplier for Binary Edwards Curves},
booktitle = {Proceedings of the Third Workshop on Cryptography and Security in
Computing Systems, CS2@HiPEAC, Prague, Czech Republic, January 20,
2016},
pages = {41--44},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2858930.2858938},
doi = {10.1145/2858930.2858938},
timestamp = {Fri, 15 Jan 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/FournarisSK16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/FurgelSWMSB16,
author = {Igor Furgel and
Viola Saftig and
Tobias Wagner and
Kevin M{\"{u}}ller and
Reinhard Schwarz and
Axel S{\"{o}}ding{-}Freiherr von Blomberg},
editor = {Sergey Tverdyshev},
title = {Non-Interfering Composed Evaluation},
booktitle = {International Workshop on {MILS:} Architecture and Assurance for Secure
Systems, MILS@HiPEAC 2016, Prague, Czech Republic, January 19, 2016},
publisher = {Zenodo},
year = {2016},
url = {https://doi.org/10.5281/zenodo.47979},
doi = {10.5281/ZENODO.47979},
timestamp = {Thu, 02 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/FurgelSWMSB16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/GeorgiadisXS16,
author = {Andreas{-}Lazaros Georgiadis and
Sotirios Xydis and
Dimitrios Soudris},
editor = {Cristina Silvano and
Jo{\~{a}}o M. P. Cardoso and
Giovanni Agosta and
Michael H{\"{u}}bner},
title = {Deploying and monitoring hadoop MapReduce analytics on single-chip
cloud computer},
booktitle = {Proceedings of the 7th Workshop on Parallel Programming and Run-Time
Management Techniques for Many-core Architectures and the 5th Workshop
on Design Tools and Architectures For Multicore Embedded Computing
Platforms, {PARMA-DITAM} 2016, Prague, Czech Republic, January 18,
2016},
pages = {25--30},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2872421.2872423},
doi = {10.1145/2872421.2872423},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/GeorgiadisXS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/HaritatosNGK16,
author = {Alexandros{-}Herodotos Haritatos and
Konstantinos Nikas and
Georgios I. Goumas and
Nectarios Koziris},
editor = {Carsten Trinitis and
Josef Weidendorfer},
title = {A resource-centric Application Classification Approach},
booktitle = {Proceedings of the 1st {COSH} Workshop on Co-Scheduling of {HPC} Applications,
COSH@HiPEAC 2016, Prague, Czech Republic, January 19, 2016},
pages = {7--12},
publisher = {{TUM} Library},
year = {2016},
url = {https://doi.org/10.14459/2016md1286948},
doi = {10.14459/2016MD1286948},
timestamp = {Mon, 10 Jul 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/HaritatosNGK16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/HaritatosPNGK16,
author = {Alexandros{-}Herodotos Haritatos and
Nikela Papadopoulou and
Konstantinos Nikas and
Georgios I. Goumas and
Nectarios Koziris},
editor = {Carsten Trinitis and
Josef Weidendorfer},
title = {Contention-Aware Scheduling Policies for Fairness and Throughput},
booktitle = {Co-Scheduling of {HPC} Applications [extended versions of all papers
from COSH@HiPEAC 2016, Prague, Czech Republic, January 19, 2016]},
series = {Advances in Parallel Computing},
volume = {28},
pages = {22--45},
publisher = {{IOS} Press},
year = {2016},
url = {https://doi.org/10.3233/978-1-61499-730-6-22},
doi = {10.3233/978-1-61499-730-6-22},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/HaritatosPNGK16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/HerpelKMESK16,
author = {Hans{-}J{\"{u}}rgen Herpel and
M. Kerep and
G. Montano and
Knut Eckstein and
M. Sch{\"{o}}n and
A. Krutak},
editor = {Sergey Tverdyshev},
title = {{MILS} Compliant Software Architecture for Satellites},
booktitle = {International Workshop on {MILS:} Architecture and Assurance for Secure
Systems, MILS@HiPEAC 2016, Prague, Czech Republic, January 19, 2016},
publisher = {Zenodo},
year = {2016},
url = {https://doi.org/10.5281/zenodo.47973},
doi = {10.5281/ZENODO.47973},
timestamp = {Thu, 02 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/HerpelKMESK16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/HesseJ16,
author = {Robert Hesse and
Natalie D. Enright Jerger},
editor = {S{\"{o}}ren Sonntag and
Sandro Bartolini and
Giorgos Dimitrakopoulos and
Jos{\'{e}} M. Garc{\'{\i}}a},
title = {Hierarchical Clustering for On-Chip Networks},
booktitle = {Proceedings of the 1st International Workshop on Advanced Interconnect
Solutions and Technologies for Emerging Computing Systems, AISTECS@HiPEAC
2016, Prague, Czech Republic, January 18, 2016},
pages = {2:1--2:6},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2857058.2857064},
doi = {10.1145/2857058.2857064},
timestamp = {Tue, 06 Nov 2018 16:58:21 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/HesseJ16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/ImmlerHKS16,
author = {Vincent Immler and
Maxim Hennig and
Ludwig K{\"{u}}rzinger and
Georg Sigl},
editor = {Martin Palkovic and
Giovanni Agosta and
Alessandro Barenghi and
Israel Koren and
Gerardo Pelosi},
title = {Practical Aspects of Quantization and Tamper-Sensitivity for Physically
Obfuscated Keys},
booktitle = {Proceedings of the Third Workshop on Cryptography and Security in
Computing Systems, CS2@HiPEAC, Prague, Czech Republic, January 20,
2016},
pages = {13--18},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2858930.2858933},
doi = {10.1145/2858930.2858933},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/ImmlerHKS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/KlemmD16,
author = {Michael Klemm and
Christopher Dahnken},
editor = {Carsten Trinitis and
Josef Weidendorfer},
title = {Recent Processor Technologies and Co-Scheduling},
booktitle = {Co-Scheduling of {HPC} Applications [extended versions of all papers
from COSH@HiPEAC 2016, Prague, Czech Republic, January 19, 2016]},
series = {Advances in Parallel Computing},
volume = {28},
pages = {12--21},
publisher = {{IOS} Press},
year = {2016},
url = {https://doi.org/10.3233/978-1-61499-730-6-12},
doi = {10.3233/978-1-61499-730-6-12},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/KlemmD16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/KoolenS16,
author = {Ruud Koolen and
Julien Schmaltz},
editor = {Sergey Tverdyshev},
title = {Modeling Information Routing with Noninterference},
booktitle = {International Workshop on {MILS:} Architecture and Assurance for Secure
Systems, MILS@HiPEAC 2016, Prague, Czech Republic, January 19, 2016},
publisher = {Zenodo},
year = {2016},
url = {https://doi.org/10.5281/zenodo.47980},
doi = {10.5281/ZENODO.47980},
timestamp = {Thu, 02 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/KoolenS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/KortR16,
author = {Semen Kort and
Ekaterina Rudina},
editor = {Sergey Tverdyshev},
title = {The Security for Safety Problem in Cyberphysical Systems},
booktitle = {International Workshop on {MILS:} Architecture and Assurance for Secure
Systems, MILS@HiPEAC 2016, Prague, Czech Republic, January 19, 2016},
publisher = {Zenodo},
year = {2016},
url = {https://doi.org/10.5281/zenodo.47977},
doi = {10.5281/ZENODO.47977},
timestamp = {Thu, 02 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/KortR16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/KoteshwaraKP16,
author = {Sandhya Koteshwara and
Chris H. Kim and
Keshab K. Parhi},
editor = {Martin Palkovic and
Giovanni Agosta and
Alessandro Barenghi and
Israel Koren and
Gerardo Pelosi},
title = {Mode-based Obfuscation using Control-Flow Modifications},
booktitle = {Proceedings of the Third Workshop on Cryptography and Security in
Computing Systems, CS2@HiPEAC, Prague, Czech Republic, January 20,
2016},
pages = {19--24},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2858930.2858934},
doi = {10.1145/2858930.2858934},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/KoteshwaraKP16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/MaciazekNN16,
author = {Tomasz Maciazek and
Hanne Riis Nielson and
Flemming Nielson},
editor = {Sergey Tverdyshev},
title = {Content-Dependent Security Policies in Avionics},
booktitle = {International Workshop on {MILS:} Architecture and Assurance for Secure
Systems, MILS@HiPEAC 2016, Prague, Czech Republic, January 19, 2016},
publisher = {Zenodo},
year = {2016},
url = {https://doi.org/10.5281/zenodo.47981},
doi = {10.5281/ZENODO.47981},
timestamp = {Thu, 02 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/MaciazekNN16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/MadarbuxLW016,
author = {Muhammad Ridwan Madarbux and
Anouk Van Laer and
Philip M. Watts and
Timothy M. Jones},
editor = {S{\"{o}}ren Sonntag and
Sandro Bartolini and
Giorgos Dimitrakopoulos and
Jos{\'{e}} M. Garc{\'{\i}}a},
title = {Energy Efficient And Low Latency Interconnection Network For Multicast
Invalidates In Shared Memory Systems},
booktitle = {Proceedings of the 1st International Workshop on Advanced Interconnect
Solutions and Technologies for Emerging Computing Systems, AISTECS@HiPEAC
2016, Prague, Czech Republic, January 18, 2016},
pages = {1:1--1:6},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2857058.2857065},
doi = {10.1145/2857058.2857065},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/MadarbuxLW016.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/MadhuRDMNN16,
author = {Kavitha T. Madhu and
Anuj Rao and
Saptarsi Das and
Krishna C. Madhava and
S. K. Nandy and
Ranjani Narayan},
editor = {Cristina Silvano and
Jo{\~{a}}o M. P. Cardoso and
Giovanni Agosta and
Michael H{\"{u}}bner},
title = {Flexible resource allocation and management for application graphs
on ReN{\'{E}} MPSoC},
booktitle = {Proceedings of the 7th Workshop on Parallel Programming and Run-Time
Management Techniques for Many-core Architectures and the 5th Workshop
on Design Tools and Architectures For Multicore Embedded Computing
Platforms, {PARMA-DITAM} 2016, Prague, Czech Republic, January 18,
2016},
pages = {13--18},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2872421.2872426},
doi = {10.1145/2872421.2872426},
timestamp = {Tue, 27 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/MadhuRDMNN16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/MaedaYWW0WLDW16,
author = {Rafael K. V. Maeda and
Peng Yang and
Xiaowen Wu and
Zhe Wang and
Jiang Xu and
Zhehui Wang and
Haoran Li and
Luan H. K. Duong and
Zhifei Wang},
editor = {S{\"{o}}ren Sonntag and
Sandro Bartolini and
Giorgos Dimitrakopoulos and
Jos{\'{e}} M. Garc{\'{\i}}a},
title = {{JADE:} a Heterogeneous Multiprocessor System Simulation Platform
Using Recorded and Statistical Application Models},
booktitle = {Proceedings of the 1st International Workshop on Advanced Interconnect
Solutions and Technologies for Emerging Computing Systems, AISTECS@HiPEAC
2016, Prague, Czech Republic, January 18, 2016},
pages = {8:1--8:6},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2857058.2857066},
doi = {10.1145/2857058.2857066},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/MaedaYWW0WLDW16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/MendisI16,
author = {Hashan Roshantha Mendis and
Leandro Soares Indrusiak},
editor = {Cristina Silvano and
Jo{\~{a}}o M. P. Cardoso and
Giovanni Agosta and
Michael H{\"{u}}bner},
title = {Low communication overhead dynamic mapping of multiple {HEVC} video
stream decoding on NoCs},
booktitle = {Proceedings of the 7th Workshop on Parallel Programming and Run-Time
Management Techniques for Many-core Architectures and the 5th Workshop
on Design Tools and Architectures For Multicore Embedded Computing
Platforms, {PARMA-DITAM} 2016, Prague, Czech Republic, January 18,
2016},
pages = {19--24},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2872421.2872422},
doi = {10.1145/2872421.2872422},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/MendisI16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/MiorandiTBRB16,
author = {Gabriele Miorandi and
Mahdi Tala and
Marco Balboni and
Luca Ramini and
Davide Bertozzi},
editor = {S{\"{o}}ren Sonntag and
Sandro Bartolini and
Giorgos Dimitrakopoulos and
Jos{\'{e}} M. Garc{\'{\i}}a},
title = {Evolutionary vs. Revolutionary Interconnect Technologies for Future
Low-Power Multi-Core Systems},
booktitle = {Proceedings of the 1st International Workshop on Advanced Interconnect
Solutions and Technologies for Emerging Computing Systems, AISTECS@HiPEAC
2016, Prague, Czech Republic, January 18, 2016},
pages = {3:1--3:6},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2857058.2857063},
doi = {10.1145/2857058.2857063},
timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/MiorandiTBRB16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/MustafaON16,
author = {Naveed Ul Mustafa and
Ozcan Ozturk and
Sma{\"{\i}}l Niar},
title = {Adaptive routing framework for network on chip architectures},
booktitle = {Proceedings of the 2016 Workshop on Rapid Simulation and Performance
Evaluation - Methods and Tools, RAPIDO@HiPEAC 2016, Prague, Czech
Republic, January 18, 2016},
pages = {5:1--5:5},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2852339.2852344},
doi = {10.1145/2852339.2852344},
timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/MustafaON16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/NallaSS16,
author = {Venu Nalla and
Rajeev Anand Sahu and
Vishal Saraswat},
editor = {Martin Palkovic and
Giovanni Agosta and
Alessandro Barenghi and
Israel Koren and
Gerardo Pelosi},
title = {Differential Fault Attack on {SIMECK}},
booktitle = {Proceedings of the Third Workshop on Cryptography and Security in
Computing Systems, CS2@HiPEAC, Prague, Czech Republic, January 20,
2016},
pages = {45--48},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2858930.2858939},
doi = {10.1145/2858930.2858939},
timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/NallaSS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/OnnebrinkSWLACH16,
author = {Gereon Onnebrink and
Stefan Sch{\"{u}}rmans and
Florian Walbroel and
Rainer Leupers and
Gerd Ascheid and
Xiaotao Chen and
YwhPyng Harn},
title = {Black box power estimation for digital signal processors using virtual
platforms},
booktitle = {Proceedings of the 2016 Workshop on Rapid Simulation and Performance
Evaluation - Methods and Tools, RAPIDO@HiPEAC 2016, Prague, Czech
Republic, January 18, 2016},
pages = {6:1--6:6},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2852339.2852345},
doi = {10.1145/2852339.2852345},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/OnnebrinkSWLACH16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/Parkinson16,
author = {Paul J. Parkinson},
editor = {Sergey Tverdyshev},
title = {Applying {MILS} to multicore avionics systems},
booktitle = {International Workshop on {MILS:} Architecture and Assurance for Secure
Systems, MILS@HiPEAC 2016, Prague, Czech Republic, January 19, 2016},
publisher = {Zenodo},
year = {2016},
url = {https://doi.org/10.5281/zenodo.47978},
doi = {10.5281/ZENODO.47978},
timestamp = {Thu, 02 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/Parkinson16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/PickartzBCLM16,
author = {Simon Pickartz and
Jens Breitbart and
Carsten Clauss and
Stefan Lankes and
Antonello Monti},
editor = {Carsten Trinitis and
Josef Weidendorfer},
title = {Virtualization in {HPC} - An Enabler for Adaptive Co-Scheduling?},
booktitle = {Co-Scheduling of {HPC} Applications [extended versions of all papers
from COSH@HiPEAC 2016, Prague, Czech Republic, January 19, 2016]},
series = {Advances in Parallel Computing},
volume = {28},
pages = {114--141},
publisher = {{IOS} Press},
year = {2016},
url = {https://doi.org/10.3233/978-1-61499-730-6-114},
doi = {10.3233/978-1-61499-730-6-114},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/PickartzBCLM16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/PickartzBL16,
author = {Simon Pickartz and
Jens Breitbart and
Stefan Lankes},
editor = {Carsten Trinitis and
Josef Weidendorfer},
title = {Implications of Process-Migration in Virtualized Environments},
booktitle = {Proceedings of the 1st {COSH} Workshop on Co-Scheduling of {HPC} Applications,
COSH@HiPEAC 2016, Prague, Czech Republic, January 19, 2016},
pages = {31--36},
publisher = {{TUM} Library},
year = {2016},
url = {https://doi.org/10.14459/2016md1286953},
doi = {10.14459/2016MD1286953},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/PickartzBL16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/RauterHKK16,
author = {Tobias Rauter and
Andrea H{\"{o}}ller and
Nermin Kajtazovic and
Christian Kreiner},
editor = {Sergey Tverdyshev},
title = {Asset-Centric Security Risk Assessment of Software Components},
booktitle = {International Workshop on {MILS:} Architecture and Assurance for Secure
Systems, MILS@HiPEAC 2016, Prague, Czech Republic, January 19, 2016},
publisher = {Zenodo},
year = {2016},
url = {https://doi.org/10.5281/zenodo.47992},
doi = {10.5281/ZENODO.47992},
timestamp = {Thu, 02 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/RauterHKK16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/RumleyBWNB16,
author = {S{\'{e}}bastien Rumley and
Meisam Bahadori and
Ke Wen and
Dessislava Nikolova and
Keren Bergman},
editor = {S{\"{o}}ren Sonntag and
Sandro Bartolini and
Giorgos Dimitrakopoulos and
Jos{\'{e}} M. Garc{\'{\i}}a},
title = {PhoenixSim: Crosslayer Design and Modeling of Silicon Photonic Interconnects},
booktitle = {Proceedings of the 1st International Workshop on Advanced Interconnect
Solutions and Technologies for Emerging Computing Systems, AISTECS@HiPEAC
2016, Prague, Czech Republic, January 18, 2016},
pages = {7:1--7:6},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2857058.2857061},
doi = {10.1145/2857058.2857061},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/RumleyBWNB16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/RungeK16,
author = {Armin Runge and
Reiner Kolla},
editor = {S{\"{o}}ren Sonntag and
Sandro Bartolini and
Giorgos Dimitrakopoulos and
Jos{\'{e}} M. Garc{\'{\i}}a},
title = {Consideration of the Flit Size for Deflection Routing based Network-on-Chips},
booktitle = {Proceedings of the 1st International Workshop on Advanced Interconnect
Solutions and Technologies for Emerging Computing Systems, AISTECS@HiPEAC
2016, Prague, Czech Republic, January 18, 2016},
pages = {5:1--5:6},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2857058.2857060},
doi = {10.1145/2857058.2857060},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/RungeK16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/SaeedAJ16,
author = {Ahmed Saeed and
Ali Ahmadinia and
Mike Just},
editor = {Martin Palkovic and
Giovanni Agosta and
Alessandro Barenghi and
Israel Koren and
Gerardo Pelosi},
title = {Tag-Protector: An Effective and Dynamic Detection of Out-of-bound
Memory Accesses},
booktitle = {Proceedings of the Third Workshop on Cryptography and Security in
Computing Systems, CS2@HiPEAC, Prague, Czech Republic, January 20,
2016},
pages = {31--36},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2858930.2858936},
doi = {10.1145/2858930.2858936},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/SaeedAJ16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/SalamaS16,
author = {Najwa Salama and
Azeddien M. Sllame},
editor = {S{\"{o}}ren Sonntag and
Sandro Bartolini and
Giorgos Dimitrakopoulos and
Jos{\'{e}} M. Garc{\'{\i}}a},
title = {Designing an Efficient MPLS-Based Switch for {FAT} Tree Network-on-Chip
Systems},
booktitle = {Proceedings of the 1st International Workshop on Advanced Interconnect
Solutions and Technologies for Emerging Computing Systems, AISTECS@HiPEAC
2016, Prague, Czech Republic, January 18, 2016},
pages = {4:1--4:6},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2857058.2857059},
doi = {10.1145/2857058.2857059},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/SalamaS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/SarrazinBP16,
author = {Guillaume Sarrazin and
Nicolas Brunie and
Fr{\'{e}}d{\'{e}}ric P{\'{e}}trot},
title = {Virtual prototyping of floating point units},
booktitle = {Proceedings of the 2016 Workshop on Rapid Simulation and Performance
Evaluation - Methods and Tools, RAPIDO@HiPEAC 2016, Prague, Czech
Republic, January 18, 2016},
pages = {1:1--1:6},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2852339.2852340},
doi = {10.1145/2852339.2852340},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/SarrazinBP16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/SeuschekHS16,
author = {Hermann Seuschek and
Johann Heyszl and
Fabrizio De Santis},
editor = {Martin Palkovic and
Giovanni Agosta and
Alessandro Barenghi and
Israel Koren and
Gerardo Pelosi},
title = {A Cautionary Note: Side-Channel Leakage Implications of Deterministic
Signature Schemes},
booktitle = {Proceedings of the Third Workshop on Cryptography and Security in
Computing Systems, CS2@HiPEAC, Prague, Czech Republic, January 20,
2016},
pages = {7--12},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2858930.2858932},
doi = {10.1145/2858930.2858932},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/SeuschekHS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/SieglBB16,
author = {Patrick Siegl and
Rainer Buchty and
Mladen Berekovic},
title = {Towards bridging the gap between academic and industrial heterogeneous
system architecture design space exploration},
booktitle = {Proceedings of the 2016 Workshop on Rapid Simulation and Performance
Evaluation - Methods and Tools, RAPIDO@HiPEAC 2016, Prague, Czech
Republic, January 18, 2016},
pages = {4:1--4:6},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2852339.2852343},
doi = {10.1145/2852339.2852343},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/SieglBB16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/SussDGNBFSS16,
author = {Tim S{\"{u}}{\ss} and
Nils D{\"{o}}ring and
Ramy Gad and
Lars Nagel and
Andr{\'{e}} Brinkmann and
Dustin Feld and
Eric Schricker and
Thomas Soddemann},
editor = {Carsten Trinitis and
Josef Weidendorfer},
title = {Impact of the Scheduling Strategy in Heterogeneous Systems That Provide
Co-Scheduling},
booktitle = {Proceedings of the 1st {COSH} Workshop on Co-Scheduling of {HPC} Applications,
COSH@HiPEAC 2016, Prague, Czech Republic, January 19, 2016},
pages = {37--42},
publisher = {{TUM} Library},
year = {2016},
url = {https://doi.org/10.14459/2016md1286954},
doi = {10.14459/2016MD1286954},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/SussDGNBFSS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/SussDGNBFSS16a,
author = {Tim S{\"{u}}{\ss} and
Nils D{\"{o}}ring and
Ramy Gad and
Lars Nagel and
Andr{\'{e}} Brinkmann and
Dustin Feld and
Eric Schricker and
Thomas Soddemann},
editor = {Carsten Trinitis and
Josef Weidendorfer},
title = {Impact of the Scheduling Strategy in Heterogeneous Systems That Provide
Co-Scheduling},
booktitle = {Co-Scheduling of {HPC} Applications [extended versions of all papers
from COSH@HiPEAC 2016, Prague, Czech Republic, January 19, 2016]},
series = {Advances in Parallel Computing},
volume = {28},
pages = {142--162},
publisher = {{IOS} Press},
year = {2016},
url = {https://doi.org/10.3233/978-1-61499-730-6-142},
doi = {10.3233/978-1-61499-730-6-142},
timestamp = {Mon, 16 Sep 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/SussDGNBFSS16a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/TerzenidisMP16,
author = {Nikos Terzenidis and
Pavlos Maniotis and
Nikos Pleros},
editor = {S{\"{o}}ren Sonntag and
Sandro Bartolini and
Giorgos Dimitrakopoulos and
Jos{\'{e}} M. Garc{\'{\i}}a},
title = {Bringing OptoBoards to HPC-scale environments: An OptoHPC simulation
engine},
booktitle = {Proceedings of the 1st International Workshop on Advanced Interconnect
Solutions and Technologies for Emerging Computing Systems, AISTECS@HiPEAC
2016, Prague, Czech Republic, January 18, 2016},
pages = {6:1--6:6},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2857058.2857062},
doi = {10.1145/2857058.2857062},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/TerzenidisMP16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/TrinitisW16,
author = {Carsten Trinitis and
Josef Weidendorfer},
editor = {Carsten Trinitis and
Josef Weidendorfer},
title = {Foreword / Workshop Description},
booktitle = {Proceedings of the 1st {COSH} Workshop on Co-Scheduling of {HPC} Applications,
COSH@HiPEAC 2016, Prague, Czech Republic, January 19, 2016},
pages = {5--6},
publisher = {{TUM} Library},
year = {2016},
url = {https://doi.org/10.14459/2016md1286947},
doi = {10.14459/2016MD1286947},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/TrinitisW16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/TrinitisWB16,
author = {Carsten Trinitis and
Josef Weidendorfer and
Andr{\'{e}} Brinkmann},
editor = {Carsten Trinitis and
Josef Weidendorfer},
title = {Co-Scheduling: Prospects and Challenges},
booktitle = {Co-Scheduling of {HPC} Applications [extended versions of all papers
from COSH@HiPEAC 2016, Prague, Czech Republic, January 19, 2016]},
series = {Advances in Parallel Computing},
volume = {28},
pages = {1--11},
publisher = {{IOS} Press},
year = {2016},
url = {https://doi.org/10.3233/978-1-61499-730-6-1},
doi = {10.3233/978-1-61499-730-6-1},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/TrinitisWB16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/Tverdyshev16,
author = {Sergey Tverdyshev},
editor = {Sergey Tverdyshev},
title = {{EURO-MILS:} Building and certifying modular secure systems},
booktitle = {International Workshop on {MILS:} Architecture and Assurance for Secure
Systems, MILS@HiPEAC 2016, Prague, Czech Republic, January 19, 2016},
publisher = {Zenodo},
year = {2016},
url = {https://doi.org/10.5281/zenodo.47975},
doi = {10.5281/ZENODO.47975},
timestamp = {Thu, 02 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/Tverdyshev16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/WeidendorferB16,
author = {Josef Weidendorfer and
Jens Breitbart},
editor = {Carsten Trinitis and
Josef Weidendorfer},
title = {Detailed Characterization of {HPC} Applications for Co-Scheduling},
booktitle = {Proceedings of the 1st {COSH} Workshop on Co-Scheduling of {HPC} Applications,
COSH@HiPEAC 2016, Prague, Czech Republic, January 19, 2016},
pages = {19--24},
publisher = {{TUM} Library},
year = {2016},
url = {https://doi.org/10.14459/2016md1286951},
doi = {10.14459/2016MD1286951},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/WeidendorferB16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/hipeac/2016aistecs,
editor = {S{\"{o}}ren Sonntag and
Sandro Bartolini and
Giorgos Dimitrakopoulos and
Jos{\'{e}} M. Garc{\'{\i}}a},
title = {Proceedings of the 1st International Workshop on Advanced Interconnect
Solutions and Technologies for Emerging Computing Systems, AISTECS@HiPEAC
2016, Prague, Czech Republic, January 18, 2016},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2857058},
doi = {10.1145/2857058},
isbn = {978-1-4503-4084-7},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/2016aistecs.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/hipeac/2016cosh,
editor = {Carsten Trinitis and
Josef Weidendorfer},
title = {Proceedings of the 1st {COSH} Workshop on Co-Scheduling of {HPC} Applications,
COSH@HiPEAC 2016, Prague, Czech Republic, January 19, 2016},
publisher = {{TUM} Library},
year = {2016},
url = {http://wwwi10.lrr.in.tum.de/\&\#126;trinitic/COSH2016/cosh.html},
timestamp = {Mon, 09 May 2016 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/2016cosh.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/hipeac/2016cs,
editor = {Martin Palkovic and
Giovanni Agosta and
Alessandro Barenghi and
Israel Koren and
Gerardo Pelosi},
title = {Proceedings of the Third Workshop on Cryptography and Security in
Computing Systems, CS2@HiPEAC, Prague, Czech Republic, January 20,
2016},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2858930},
doi = {10.1145/2858930},
isbn = {978-1-4503-4065-6},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/2016cs.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/hipeac/2016mils,
editor = {Sergey Tverdyshev},
title = {International Workshop on {MILS:} Architecture and Assurance for Secure
Systems, MILS@HiPEAC 2016, Prague, Czech Republic, January 19, 2016},
publisher = {Zenodo},
year = {2016},
url = {http://mils-workshop-2016.mils.community/},
timestamp = {Thu, 02 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/2016mils.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/hipeac/2016parma,
editor = {Cristina Silvano and
Jo{\~{a}}o M. P. Cardoso and
Giovanni Agosta and
Michael H{\"{u}}bner},
title = {Proceedings of the 7th Workshop on Parallel Programming and Run-Time
Management Techniques for Many-core Architectures and the 5th Workshop
on Design Tools and Architectures For Multicore Embedded Computing
Platforms, {PARMA-DITAM} 2016, Prague, Czech Republic, January 18,
2016},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2872421},
doi = {10.1145/2872421},
isbn = {978-1-4503-4052-6},
timestamp = {Wed, 28 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/2016parma.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/hipeac/2016rapido,
title = {Proceedings of the 2016 Workshop on Rapid Simulation and Performance
Evaluation - Methods and Tools, RAPIDO@HiPEAC 2016, Prague, Czech
Republic, January 18, 2016},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2852339},
doi = {10.1145/2852339},
isbn = {978-1-4503-4072-4},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/2016rapido.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/AdamTRS15,
author = {Daniel Adam and
Sergey Tverdyshev and
Carsten Rolfes and
Timo Sandmann},
editor = {Sergey Tverdyshev},
title = {Two Architecture Approaches for {MILS} Systems in Mobility Domains
(Automobile, Railway and Avionik)},
booktitle = {International Workshop on {MILS:} Architecture and Assurance for Secure
Systems, MILS@HiPEAC 2015, Amsterdam, The Netherlands, January 20,
2015},
publisher = {Zenodo},
year = {2015},
url = {https://doi.org/10.5281/zenodo.47991},
doi = {10.5281/ZENODO.47991},
timestamp = {Thu, 02 Aug 2018 14:39:18 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/AdamTRS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/Blasum15,
author = {Holger Blasum},
editor = {Sergey Tverdyshev},
title = {Partitioning in Safety and Security: Mapping to {MILS} Core Partitioning
Mechanisms},
booktitle = {International Workshop on {MILS:} Architecture and Assurance for Secure
Systems, MILS@HiPEAC 2015, Amsterdam, The Netherlands, January 20,
2015},
publisher = {Zenodo},
year = {2015},
url = {https://doi.org/10.5281/zenodo.47974},
doi = {10.5281/ZENODO.47974},
timestamp = {Thu, 02 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/Blasum15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/BoudguigaKW15,
author = {Aymen Boudguiga and
Witold Klaudel and
Jimmy Durand Wesolowski},
editor = {Gianluca Palermo and
Daniel Gracia P{\'{e}}rez and
Morteza Biglari{-}Abhari and
Daniel Chillet and
Sma{\"{\i}}l Niar and
Adam Morawiec},
title = {On the performance of freescale i.MX6 cryptographic acceleration and
assurance module},
booktitle = {Proceedings of the 2015 Workshop on Rapid Simulation and Performance
Evaluation: Methods and Tools, RAPIDO@HiPEAC 2015, 21 January, 2015,
Amsterdam, The Netherlands},
pages = {8:1--8:8},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2693433.2693441},
doi = {10.1145/2693433.2693441},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/BoudguigaKW15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/CarboneTMD15,
author = {Mathieu Carbone and
Yannick Teglia and
Philippe Maurine and
Gilles R. Ducharme},
editor = {Andy D. Pimentel and
Stephan Wong and
Gerardo Pelosi and
Israel Koren and
Giovanni Agosta and
Alessandro Barenghi},
title = {Interest of {MIA} in frequency domain?},
booktitle = {Proceedings of the Second Workshop on Cryptography and Security in
Computing Systems, CS2@HiPEAC 2015, Amsterdam, Netherlands, January
19-21, 2015},
pages = {35--38},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2694805.2694812},
doi = {10.1145/2694805.2694812},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/CarboneTMD15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/CeballosHB15,
author = {Germ{\'{a}}n Ceballos and
Erik Hagersten and
David Black{-}Schaffer},
editor = {Gianluca Palermo and
Daniel Gracia P{\'{e}}rez and
Morteza Biglari{-}Abhari and
Daniel Chillet and
Sma{\"{\i}}l Niar and
Adam Morawiec},
title = {StatTask: reuse distance analysis for task-based applications},
booktitle = {Proceedings of the 2015 Workshop on Rapid Simulation and Performance
Evaluation: Methods and Tools, RAPIDO@HiPEAC 2015, 21 January, 2015,
Amsterdam, The Netherlands},
pages = {1:1--1:7},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2693433.2693434},
doi = {10.1145/2693433.2693434},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/CeballosHB15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/CunhaFP15,
author = {Marcos Aur{\'{e}}lio Pinto Cunha and
Nicolas Fournel and
Fr{\'{e}}d{\'{e}}ric P{\'{e}}trot},
editor = {Gianluca Palermo and
Daniel Gracia P{\'{e}}rez and
Morteza Biglari{-}Abhari and
Daniel Chillet and
Sma{\"{\i}}l Niar and
Adam Morawiec},
title = {Collecting traces in dynamic binary translation based virtual prototyping
platforms},
booktitle = {Proceedings of the 2015 Workshop on Rapid Simulation and Performance
Evaluation: Methods and Tools, RAPIDO@HiPEAC 2015, 21 January, 2015,
Amsterdam, The Netherlands},
pages = {4:1--4:6},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2693433.2693437},
doi = {10.1145/2693433.2693437},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/CunhaFP15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/DayA15,
author = {Khaled Day and
Mohammad H. Al{-}Towaiq},
title = {A Parallel Gauss-Seidel Algorithm on a 3D Torus Network-on-Chip Architecture},
booktitle = {Ninth International Workshop on Interconnection Network Architectures:
On-Chip, Multi-Chip, INA-OCMC@HiPEAC 2015, Amsterdam, Netherlands,
January 19, 2015},
pages = {13--16},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/INA-OCMC.2015.8},
doi = {10.1109/INA-OCMC.2015.8},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/DayA15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/DeLong15,
author = {Rance J. DeLong},
editor = {Sergey Tverdyshev},
title = {{MILS} Initiatives Within The Open Group},
booktitle = {International Workshop on {MILS:} Architecture and Assurance for Secure
Systems, MILS@HiPEAC 2015, Amsterdam, The Netherlands, January 20,
2015},
publisher = {Zenodo},
year = {2015},
url = {https://doi.org/10.5281/zenodo.47988},
doi = {10.5281/ZENODO.47988},
timestamp = {Thu, 02 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/DeLong15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/ElangovanBA15,
author = {Vinoth Krishnan Elangovan and
Rosa M. Badia and
Eduard Ayguad{\'{e}}},
editor = {Giovanni Agosta and
Cristina Silvano and
Jo{\~{a}}o M. P. Cardoso and
Michael H{\"{u}}bner},
title = {Auto-Tuning OmpSs-OpenCL Kernels Across {GPU} Machines},
booktitle = {Proceedings of the 6th Workshop on Parallel Programming and Run-Time
Management Techniques for Many-core Architectures and the 4th Workshop
on Design Tools and Architectures for Multicore Embedded Computing
Platforms, {PARMA-DITAM} 2015, Amsterdam, Netherlands, January 21,
2015},
pages = {31--36},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2701310.2701316},
doi = {10.1145/2701310.2701316},
timestamp = {Wed, 28 Apr 2021 16:06:57 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/ElangovanBA15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/EndoCC15,
author = {Fernando Akira Endo and
Damien Courouss{\'{e}} and
Henri{-}Pierre Charles},
editor = {Gianluca Palermo and
Daniel Gracia P{\'{e}}rez and
Morteza Biglari{-}Abhari and
Daniel Chillet and
Sma{\"{\i}}l Niar and
Adam Morawiec},
title = {Micro-architectural simulation of embedded core heterogeneity with
gem5 and McPAT},
booktitle = {Proceedings of the 2015 Workshop on Rapid Simulation and Performance
Evaluation: Methods and Tools, RAPIDO@HiPEAC 2015, 21 January, 2015,
Amsterdam, The Netherlands},
pages = {7:1--7:6},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2693433.2693440},
doi = {10.1145/2693433.2693440},
timestamp = {Sat, 02 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/EndoCC15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/FournarisKSK15,
author = {Apostolos P. Fournaris and
Nicolaos Klaoudatos and
Nicolas Sklavos and
Christos Koulamas},
editor = {Andy D. Pimentel and
Stephan Wong and
Gerardo Pelosi and
Israel Koren and
Giovanni Agosta and
Alessandro Barenghi},
title = {Fault and Power Analysis Attack Resistant {RNS} based Edwards Curve
Point Multiplication},
booktitle = {Proceedings of the Second Workshop on Cryptography and Security in
Computing Systems, CS2@HiPEAC 2015, Amsterdam, Netherlands, January
19-21, 2015},
pages = {43--46},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2694805.2694814},
doi = {10.1145/2694805.2694814},
timestamp = {Fri, 15 Jan 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/FournarisKSK15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/FusellaFCM15,
author = {Edoardo Fusella and
Jos{\'{e}} Flich and
Alessandro Cilardo and
Antonino Mazzeo},
title = {On the Design of a Path-Setup Architecture for Exploiting Hybrid Photonic-Electronic
NoCs},
booktitle = {2015 Workshop on Exploiting Silicon Photonics for Energy-Efficient
High Performance Computing, SiPhotonics@HiPEAC 2015, Amsterdam, Netherlands,
January 19, 2015},
pages = {9--16},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/SiPhotonics.2015.14},
doi = {10.1109/SIPHOTONICS.2015.14},
timestamp = {Mon, 18 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/FusellaFCM15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/HawkinsKH15,
author = {Richard Hawkins and
Tim Kelly and
Ibrahim Habli},
editor = {Sergey Tverdyshev},
title = {Developing Assurance Cases for {D-MILS} Systems},
booktitle = {International Workshop on {MILS:} Architecture and Assurance for Secure
Systems, MILS@HiPEAC 2015, Amsterdam, The Netherlands, January 20,
2015},
publisher = {Zenodo},
year = {2015},
url = {https://doi.org/10.5281/zenodo.47984},
doi = {10.5281/ZENODO.47984},
timestamp = {Thu, 02 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/HawkinsKH15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/HeH15,
author = {Wei He and
Alexander Herrmann},
editor = {Andy D. Pimentel and
Stephan Wong and
Gerardo Pelosi and
Israel Koren and
Giovanni Agosta and
Alessandro Barenghi},
title = {Placement Security Analysis for Side-Channel Resistant Dual-Rail Scheme
in {FPGA}},
booktitle = {Proceedings of the Second Workshop on Cryptography and Security in
Computing Systems, CS2@HiPEAC 2015, Amsterdam, Netherlands, January
19-21, 2015},
pages = {39--42},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2694805.2694813},
doi = {10.1145/2694805.2694813},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/HeH15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/HerreraSRPP15,
author = {Fernando Herrera and
Ingo Sander and
Kathrin Rosvall and
Edoardo Paone and
Gianluca Palermo},
editor = {Gianluca Palermo and
Daniel Gracia P{\'{e}}rez and
Morteza Biglari{-}Abhari and
Daniel Chillet and
Sma{\"{\i}}l Niar and
Adam Morawiec},
title = {An efficient joint analytical and simulation-based design space exploration
flow for predictable multi-core systems},
booktitle = {Proceedings of the 2015 Workshop on Rapid Simulation and Performance
Evaluation: Methods and Tools, RAPIDO@HiPEAC 2015, 21 January, 2015,
Amsterdam, The Netherlands},
pages = {2:1--2:8},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2693433.2693435},
doi = {10.1145/2693433.2693435},
timestamp = {Wed, 25 Sep 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/HerreraSRPP15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/HerrmannS15,
author = {Alexander Herrmann and
Marc St{\"{o}}ttinger},
editor = {Andy D. Pimentel and
Stephan Wong and
Gerardo Pelosi and
Israel Koren and
Giovanni Agosta and
Alessandro Barenghi},
title = {Evaluation Tools for Multivariate Side-Channel Analysis},
booktitle = {Proceedings of the Second Workshop on Cryptography and Security in
Computing Systems, CS2@HiPEAC 2015, Amsterdam, Netherlands, January
19-21, 2015},
pages = {1--6},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2694805.2694806},
doi = {10.1145/2694805.2694806},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/HerrmannS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/HuMSGS15,
author = {Yong Hu and
Daniel M{\"{u}}ller{-}Gritschneder and
Martha Johanna Sep{\'{u}}lveda and
Guy Gogniat and
Ulf Schlichtmann},
title = {Automatic ILP-based Firewall Insertion for Secure Application-Specific
Networks-on-Chip},
booktitle = {Ninth International Workshop on Interconnection Network Architectures:
On-Chip, Multi-Chip, INA-OCMC@HiPEAC 2015, Amsterdam, Netherlands,
January 19, 2015},
pages = {9--12},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/INA-OCMC.2015.9},
doi = {10.1109/INA-OCMC.2015.9},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/HuMSGS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/IttershagenHGN15,
author = {Philipp Ittershagen and
Philipp A. Hartmann and
Kim Gr{\"{u}}ttner and
Wolfgang Nebel},
editor = {Gianluca Palermo and
Daniel Gracia P{\'{e}}rez and
Morteza Biglari{-}Abhari and
Daniel Chillet and
Sma{\"{\i}}l Niar and
Adam Morawiec},
title = {A workload extraction framework for software performance model generation},
booktitle = {Proceedings of the 2015 Workshop on Rapid Simulation and Performance
Evaluation: Methods and Tools, RAPIDO@HiPEAC 2015, 21 January, 2015,
Amsterdam, The Netherlands},
pages = {3:1--3:6},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2693433.2693436},
doi = {10.1145/2693433.2693436},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/IttershagenHGN15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/KakoulliSKK15,
author = {Elena Kakoulli and
Vassos Soteriou and
Charalambos Koutsides and
Kyriacos Kalli},
title = {Towards High-Performance and Power-Efficient Optical NoCs Using Silicon-in-Silica
Photonic Components},
booktitle = {Ninth International Workshop on Interconnection Network Architectures:
On-Chip, Multi-Chip, INA-OCMC@HiPEAC 2015, Amsterdam, Netherlands,
January 19, 2015},
pages = {1--4},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/INA-OCMC.2015.12},
doi = {10.1109/INA-OCMC.2015.12},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/KakoulliSKK15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/KoolenS15,
author = {Ruud Koolen and
Julien Schmaltz},
editor = {Sergey Tverdyshev},
title = {Formal Methods for {MILS:} Formalisations of the {GWV} Firewall},
booktitle = {International Workshop on {MILS:} Architecture and Assurance for Secure
Systems, MILS@HiPEAC 2015, Amsterdam, The Netherlands, January 20,
2015},
publisher = {Zenodo},
year = {2015},
url = {https://doi.org/10.5281/zenodo.47983},
doi = {10.5281/ZENODO.47983},
timestamp = {Thu, 02 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/KoolenS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/Lescuyer15,
author = {St{\'{e}}phane Lescuyer},
editor = {Sergey Tverdyshev},
title = {ProvenCore: Towards a Verified Isolation Micro-Kernel},
booktitle = {International Workshop on {MILS:} Architecture and Assurance for Secure
Systems, MILS@HiPEAC 2015, Amsterdam, The Netherlands, January 20,
2015},
publisher = {Zenodo},
year = {2015},
url = {https://doi.org/10.5281/zenodo.47990},
doi = {10.5281/ZENODO.47990},
timestamp = {Thu, 02 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/Lescuyer15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/LuoKBCLOS15,
author = {Jiating Luo and
C{\'{e}}dric Killian and
S{\'{e}}bastien Le Beux and
Daniel Chillet and
Hui Li and
Ian O'Connor and
Olivier Sentieys},
title = {Channel Allocation Protocol for Reconfigurable Optical Network-on-Chip},
booktitle = {2015 Workshop on Exploiting Silicon Photonics for Energy-Efficient
High Performance Computing, SiPhotonics@HiPEAC 2015, Amsterdam, Netherlands,
January 19, 2015},
pages = {33--39},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/SiPhotonics.2015.12},
doi = {10.1109/SIPHOTONICS.2015.12},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/LuoKBCLOS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/ManiotisGTP15,
author = {Pavlos Maniotis and
Savvas Gitzenis and
Leandros Tassiulas and
Nikos Pleros},
title = {High-Speed Optical Cache Memory as Single-Level Shared Cache in Chip-Multiprocessor
Architectures},
booktitle = {2015 Workshop on Exploiting Silicon Photonics for Energy-Efficient
High Performance Computing, SiPhotonics@HiPEAC 2015, Amsterdam, Netherlands,
January 19, 2015},
pages = {1--8},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/SiPhotonics.2015.10},
doi = {10.1109/SIPHOTONICS.2015.10},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/ManiotisGTP15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/MartinsS15,
author = {Paulo Martins and
Leonel Sousa},
editor = {Andy D. Pimentel and
Stephan Wong and
Gerardo Pelosi and
Israel Koren and
Giovanni Agosta and
Alessandro Barenghi},
title = {Stretching the limits of Programmable Embedded Devices for Public-key
Cryptography},
booktitle = {Proceedings of the Second Workshop on Cryptography and Security in
Computing Systems, CS2@HiPEAC 2015, Amsterdam, Netherlands, January
19-21, 2015},
pages = {19--24},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2694805.2694809},
doi = {10.1145/2694805.2694809},
timestamp = {Wed, 16 Jan 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/MartinsS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/MichailIV15,
author = {Harris E. Michail and
Lenos Ioannou and
Artemios G. Voyiatzis},
editor = {Andy D. Pimentel and
Stephan Wong and
Gerardo Pelosi and
Israel Koren and
Giovanni Agosta and
Alessandro Barenghi},
title = {Pipelined {SHA-3} Implementations on {FPGA:} Architecture and Performance
Analysis},
booktitle = {Proceedings of the Second Workshop on Cryptography and Security in
Computing Systems, CS2@HiPEAC 2015, Amsterdam, Netherlands, January
19-21, 2015},
pages = {13--18},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2694805.2694808},
doi = {10.1145/2694805.2694808},
timestamp = {Sat, 05 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/MichailIV15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/NarayananS15,
author = {Surya Narayanan and
Andr{\'{e}} Seznec},
editor = {Giovanni Agosta and
Cristina Silvano and
Jo{\~{a}}o M. P. Cardoso and
Michael H{\"{u}}bner},
title = {Sequential and Parallel Code Sections are Different: they may require
different Processors},
booktitle = {Proceedings of the 6th Workshop on Parallel Programming and Run-Time
Management Techniques for Many-core Architectures and the 4th Workshop
on Design Tools and Architectures for Multicore Embedded Computing
Platforms, {PARMA-DITAM} 2015, Amsterdam, Netherlands, January 21,
2015},
pages = {13--18},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2701310.2701314},
doi = {10.1145/2701310.2701314},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/NarayananS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/NetkachovaMPB15,
author = {Kateryna Netkachova and
Kevin Mueller and
Michael Paulitsch and
Robin Bloomfield},
editor = {Sergey Tverdyshev},
title = {Security-Informed Safety Case Approach to Analysing {MILS} Systems},
booktitle = {International Workshop on {MILS:} Architecture and Assurance for Secure
Systems, MILS@HiPEAC 2015, Amsterdam, The Netherlands, January 20,
2015},
publisher = {Zenodo},
year = {2015},
url = {https://doi.org/10.5281/zenodo.47987},
doi = {10.5281/ZENODO.47987},
timestamp = {Thu, 02 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/NetkachovaMPB15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/OrtinRBZNVB15,
author = {Marta Ort{\'{\i}}n and
Luca Ramini and
Marco Balboni and
Lorenzo Zuolo and
Maddalena Nonato and
V{\'{\i}}ctor Vi{\~{n}}als and
Davide Bertozzi},
title = {Partitioning Strategies of Wavelength-Routed Optical Networks-on-Chip
for Laser Power Minimization},
booktitle = {2015 Workshop on Exploiting Silicon Photonics for Energy-Efficient
High Performance Computing, SiPhotonics@HiPEAC 2015, Amsterdam, Netherlands,
January 19, 2015},
pages = {17--24},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/SiPhotonics.2015.13},
doi = {10.1109/SIPHOTONICS.2015.13},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/OrtinRBZNVB15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/OtoomTAA15,
author = {Mwaffaq Otoom and
Pedro Trancoso and
Hisham M. Almasaeid and
Mohammad A. Alzubaidi},
editor = {Giovanni Agosta and
Cristina Silvano and
Jo{\~{a}}o M. P. Cardoso and
Michael H{\"{u}}bner},
title = {Scalable and Dynamic Global Power Management for Multicore Chips},
booktitle = {Proceedings of the 6th Workshop on Parallel Programming and Run-Time
Management Techniques for Many-core Architectures and the 4th Workshop
on Design Tools and Architectures for Multicore Embedded Computing
Platforms, {PARMA-DITAM} 2015, Amsterdam, Netherlands, January 21,
2015},
pages = {25--30},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2701310.2701312},
doi = {10.1145/2701310.2701312},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/OtoomTAA15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/PeterS15,
author = {Eldhose Peter and
Smruti R. Sarangi},
title = {Optimal Power Efficient Photonic {SWMR} Buses},
booktitle = {2015 Workshop on Exploiting Silicon Photonics for Energy-Efficient
High Performance Computing, SiPhotonics@HiPEAC 2015, Amsterdam, Netherlands,
January 19, 2015},
pages = {25--32},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/SiPhotonics.2015.11},
doi = {10.1109/SIPHOTONICS.2015.11},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/PeterS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/PlagaM15,
author = {Rainer Plaga and
Dominik Merli},
editor = {Andy D. Pimentel and
Stephan Wong and
Gerardo Pelosi and
Israel Koren and
Giovanni Agosta and
Alessandro Barenghi},
title = {A new Definition and Classification of Physical Unclonable Functions},
booktitle = {Proceedings of the Second Workshop on Cryptography and Security in
Computing Systems, CS2@HiPEAC 2015, Amsterdam, Netherlands, January
19-21, 2015},
pages = {7--12},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2694805.2694807},
doi = {10.1145/2694805.2694807},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/PlagaM15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/PolN15,
author = {Kevin van der Pol and
Thomas Noll},
editor = {Sergey Tverdyshev},
title = {Security Type Checking for {MILS-AADL} Specifications},
booktitle = {International Workshop on {MILS:} Architecture and Assurance for Secure
Systems, MILS@HiPEAC 2015, Amsterdam, The Netherlands, January 20,
2015},
publisher = {Zenodo},
year = {2015},
url = {https://doi.org/10.5281/zenodo.47989},
doi = {10.5281/ZENODO.47989},
timestamp = {Wed, 08 Jan 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/PolN15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/RakotovaoPMRNL15,
author = {Tiana A. Rakotovao and
Diego Puschini and
Julien Mottin and
Lukas Rummelhard and
Amaury N{\`{e}}gre and
Christian Laugier},
editor = {Giovanni Agosta and
Cristina Silvano and
Jo{\~{a}}o M. P. Cardoso and
Michael H{\"{u}}bner},
title = {Intelligent Vehicle Perception: Toward the Integration on Embedded
Many-core},
booktitle = {Proceedings of the 6th Workshop on Parallel Programming and Run-Time
Management Techniques for Many-core Architectures and the 4th Workshop
on Design Tools and Architectures for Multicore Embedded Computing
Platforms, {PARMA-DITAM} 2015, Amsterdam, Netherlands, January 21,
2015},
pages = {7--12},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2701310.2701313},
doi = {10.1145/2701310.2701313},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/RakotovaoPMRNL15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/RaminiTB15,
author = {Luca Ramini and
Mahdi Tala and
Davide Bertozzi},
title = {Contrasting Power Efficiency of Contention Resolution vs. Avoidance
Strategies in Optical Ring Interconnects for Photonically-Integrated
Embedded Systems},
booktitle = {Ninth International Workshop on Interconnection Network Architectures:
On-Chip, Multi-Chip, INA-OCMC@HiPEAC 2015, Amsterdam, Netherlands,
January 19, 2015},
pages = {5--8},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/INA-OCMC.2015.10},
doi = {10.1109/INA-OCMC.2015.10},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/RaminiTB15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/RosK15,
author = {Alberto Ros and
Stefanos Kaxiras},
editor = {Giovanni Agosta and
Cristina Silvano and
Jo{\~{a}}o M. P. Cardoso and
Michael H{\"{u}}bner},
title = {Fast{\&}Furious: {A} Tool for Detecting Covert Racing},
booktitle = {Proceedings of the 6th Workshop on Parallel Programming and Run-Time
Management Techniques for Many-core Architectures and the 4th Workshop
on Design Tools and Architectures for Multicore Embedded Computing
Platforms, {PARMA-DITAM} 2015, Amsterdam, Netherlands, January 21,
2015},
pages = {1--6},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2701310.2701315},
doi = {10.1145/2701310.2701315},
timestamp = {Wed, 31 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/RosK15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/RosaLC15,
author = {Thiago Raupp da Rosa and
Romain Lemaire and
Fabien Clermidy},
title = {A Co-design Approach for Hardware Optimizations in Multicore Architectures
Using {MCAPI}},
booktitle = {Ninth International Workshop on Interconnection Network Architectures:
On-Chip, Multi-Chip, INA-OCMC@HiPEAC 2015, Amsterdam, Netherlands,
January 19, 2015},
pages = {17--20},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/INA-OCMC.2015.11},
doi = {10.1109/INA-OCMC.2015.11},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/RosaLC15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/RuessT15,
author = {Harald Rue{\ss} and
Stefano Tonetta},
editor = {Sergey Tverdyshev},
title = {Distributed {MILS} {(D-MILS)} Specification, Analysis, Deployment,
and Assurance of Distributed Critical Systems},
booktitle = {International Workshop on {MILS:} Architecture and Assurance for Secure
Systems, MILS@HiPEAC 2015, Amsterdam, The Netherlands, January 20,
2015},
publisher = {Zenodo},
year = {2015},
url = {https://doi.org/10.5281/zenodo.47985},
doi = {10.5281/ZENODO.47985},
timestamp = {Thu, 02 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/RuessT15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/SaidiCCM15,
author = {Salah Eddine Saidi and
Sylvain Cotard and
Khaled Chaaban and
Kevin Marteil},
editor = {Gianluca Palermo and
Daniel Gracia P{\'{e}}rez and
Morteza Biglari{-}Abhari and
Daniel Chillet and
Sma{\"{\i}}l Niar and
Adam Morawiec},
title = {An {ILP} approach for mapping {AUTOSAR} runnables on multi-core architectures},
booktitle = {Proceedings of the 2015 Workshop on Rapid Simulation and Performance
Evaluation: Methods and Tools, RAPIDO@HiPEAC 2015, 21 January, 2015,
Amsterdam, The Netherlands},
pages = {6:1--6:8},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2693433.2693439},
doi = {10.1145/2693433.2693439},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/SaidiCCM15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/ShafikDYMA15,
author = {Rishad A. Shafik and
Anup Das and
Sheng Yang and
Geoff V. Merrett and
Bashir M. Al{-}Hashimi},
editor = {Giovanni Agosta and
Cristina Silvano and
Jo{\~{a}}o M. P. Cardoso and
Michael H{\"{u}}bner},
title = {Adaptive Energy Minimization of OpenMP Parallel Applications on Many-Core
Systems},
booktitle = {Proceedings of the 6th Workshop on Parallel Programming and Run-Time
Management Techniques for Many-core Architectures and the 4th Workshop
on Design Tools and Architectures for Multicore Embedded Computing
Platforms, {PARMA-DITAM} 2015, Amsterdam, Netherlands, January 21,
2015},
pages = {19--24},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2701310.2701311},
doi = {10.1145/2701310.2701311},
timestamp = {Mon, 15 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/ShafikDYMA15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/SinnhoferRSK15,
author = {Andreas Daniel Sinnhofer and
Wolfgang Raschke and
Christian Steger and
Christian Kreiner},
editor = {Sergey Tverdyshev},
title = {Evaluation paradigm selection according to Common Criteria for an
incremental product development},
booktitle = {International Workshop on {MILS:} Architecture and Assurance for Secure
Systems, MILS@HiPEAC 2015, Amsterdam, The Netherlands, January 20,
2015},
publisher = {Zenodo},
year = {2015},
url = {https://doi.org/10.5281/zenodo.47986},
doi = {10.5281/ZENODO.47986},
timestamp = {Thu, 02 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/SinnhoferRSK15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/TerraneoZF15,
author = {Federico Terraneo and
Davide Zoni and
William Fornaciari},
editor = {Gianluca Palermo and
Daniel Gracia P{\'{e}}rez and
Morteza Biglari{-}Abhari and
Daniel Chillet and
Sma{\"{\i}}l Niar and
Adam Morawiec},
title = {An accurate simulation framework for thermal explorations and optimizations},
booktitle = {Proceedings of the 2015 Workshop on Rapid Simulation and Performance
Evaluation: Methods and Tools, RAPIDO@HiPEAC 2015, 21 January, 2015,
Amsterdam, The Netherlands},
pages = {5:1--5:6},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2693433.2693438},
doi = {10.1145/2693433.2693438},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/TerraneoZF15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/Toorani15,
author = {Mohsen Toorani},
editor = {Andy D. Pimentel and
Stephan Wong and
Gerardo Pelosi and
Israel Koren and
Giovanni Agosta and
Alessandro Barenghi},
title = {On Continuous After-the-Fact Leakage-Resilient Key Exchange},
booktitle = {Proceedings of the Second Workshop on Cryptography and Security in
Computing Systems, CS2@HiPEAC 2015, Amsterdam, Netherlands, January
19-21, 2015},
pages = {31--34},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2694805.2694811},
doi = {10.1145/2694805.2694811},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/Toorani15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/Tverdyshev15,
author = {Sergey Tverdyshev},
editor = {Sergey Tverdyshev},
title = {{EURO-MILS:} Building and certifying modular secure systems},
booktitle = {International Workshop on {MILS:} Architecture and Assurance for Secure
Systems, MILS@HiPEAC 2015, Amsterdam, The Netherlands, January 20,
2015},
publisher = {Zenodo},
year = {2015},
url = {https://doi.org/10.5281/zenodo.47972},
doi = {10.5281/ZENODO.47972},
timestamp = {Thu, 02 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/Tverdyshev15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/ZussaEDRRTC15,
author = {Lo{\"{\i}}c Zussa and
Ingrid Exurville and
Jean{-}Max Dutertre and
Jean{-}Baptiste Rigaud and
Bruno Robisson and
Assia Tria and
Jessy Cl{\'{e}}di{\`{e}}re},
editor = {Andy D. Pimentel and
Stephan Wong and
Gerardo Pelosi and
Israel Koren and
Giovanni Agosta and
Alessandro Barenghi},
title = {Evidence of an information leakage between logically independent blocks},
booktitle = {Proceedings of the Second Workshop on Cryptography and Security in
Computing Systems, CS2@HiPEAC 2015, Amsterdam, Netherlands, January
19-21, 2015},
pages = {25--30},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2694805.2694810},
doi = {10.1145/2694805.2694810},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/ZussaEDRRTC15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/hipeac/2015cs,
editor = {Andy D. Pimentel and
Stephan Wong and
Gerardo Pelosi and
Israel Koren and
Giovanni Agosta and
Alessandro Barenghi},
title = {Proceedings of the Second Workshop on Cryptography and Security in
Computing Systems, CS2@HiPEAC 2015, Amsterdam, Netherlands, January
19-21, 2015},
publisher = {{ACM}},
year = {2015},
url = {http://dl.acm.org/citation.cfm?id=2694805},
isbn = {978-1-4503-3187-6},
timestamp = {Sun, 25 Jan 2015 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/2015cs.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/hipeac/2015ina-ocmc,
title = {Ninth International Workshop on Interconnection Network Architectures:
On-Chip, Multi-Chip, INA-OCMC@HiPEAC 2015, Amsterdam, Netherlands,
January 19, 2015},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://ieeexplore.ieee.org/xpl/conhome/7051733/proceeding},
isbn = {978-1-4799-1870-6},
timestamp = {Wed, 16 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/2015ina-ocmc.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/hipeac/2015mils,
editor = {Sergey Tverdyshev},
title = {International Workshop on {MILS:} Architecture and Assurance for Secure
Systems, MILS@HiPEAC 2015, Amsterdam, The Netherlands, January 20,
2015},
publisher = {Zenodo},
year = {2015},
url = {http://mils-workshop-2015.mils.community/},
timestamp = {Thu, 02 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/2015mils.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/hipeac/2015parma,
editor = {Giovanni Agosta and
Cristina Silvano and
Jo{\~{a}}o M. P. Cardoso and
Michael H{\"{u}}bner},
title = {Proceedings of the 6th Workshop on Parallel Programming and Run-Time
Management Techniques for Many-core Architectures and the 4th Workshop
on Design Tools and Architectures for Multicore Embedded Computing
Platforms, {PARMA-DITAM} 2015, Amsterdam, Netherlands, January 21,
2015},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2701310},
doi = {10.1145/2701310},
isbn = {978-1-4503-3343-6},
timestamp = {Wed, 28 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/2015parma.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/hipeac/2015rapido,
editor = {Gianluca Palermo and
Daniel Gracia P{\'{e}}rez and
Morteza Biglari{-}Abhari and
Daniel Chillet and
Sma{\"{\i}}l Niar and
Adam Morawiec},
title = {Proceedings of the 2015 Workshop on Rapid Simulation and Performance
Evaluation: Methods and Tools, RAPIDO@HiPEAC 2015, 21 January, 2015,
Amsterdam, The Netherlands},
publisher = {{ACM}},
year = {2015},
url = {http://dl.acm.org/citation.cfm?id=2693433},
isbn = {978-1-60558-699-1},
timestamp = {Thu, 29 Jan 2015 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/2015rapido.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/hipeac/2015siphotonics,
title = {2015 Workshop on Exploiting Silicon Photonics for Energy-Efficient
High Performance Computing, SiPhotonics@HiPEAC 2015, Amsterdam, Netherlands,
January 19, 2015},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://ieeexplore.ieee.org/xpl/conhome/7051631/proceeding},
isbn = {978-1-4799-8093-2},
timestamp = {Wed, 16 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/2015siphotonics.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/AndujarVA0D14,
author = {Francisco J. And{\'{u}}jar and
Juan A. Villar and
Francisco J. Alfaro and
Jos{\'{e}} L. S{\'{a}}nchez and
Jos{\'{e}} Duato},
editor = {Giorgos Dimitrakopoulos and
S{\"{o}}ren Sonntag and
Jos{\'{e}} Flich and
Pascal Vivet},
title = {Deadlock-free routing mechanism for 3D twin torus networks},
booktitle = {Proceedings of the 8th International Workshop on Interconnection Network
Architecture - On-Chip, Multi-Chip, {INA-OCMC} 2014, Vienna, Austria,
January 22, 2014},
pages = {3:1--3:4},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2556857.2556862},
doi = {10.1145/2556857.2556862},
timestamp = {Fri, 17 Dec 2021 12:59:56 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/AndujarVA0D14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/BerlachLSLH14,
author = {Reinhard Berlach and
Michael Lackner and
Christian Steger and
Johannes Loinig and
Ernst Haselsteiner},
editor = {Jens Knoop and
Valentina Salapura and
Israel Koren and
Gerardo Pelosi},
title = {Memory-efficient on-card byte code verification for Java cards},
booktitle = {Proceedings of the First Workshop on Cryptography and Security in
Computing Systems, CS2@HiPEAC 2014, Vienna, Austria, January 20, 2014},
pages = {37--40},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2556315.2556323},
doi = {10.1145/2556315.2556323},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/BerlachLSLH14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/ChrysosNGMDB14,
author = {Nikolaos Chrysos and
Fredy D. Neeser and
Mitch Gusat and
Cyriel Minkenberg and
Wolfgang E. Denzel and
Claude Basso},
editor = {Giorgos Dimitrakopoulos and
S{\"{o}}ren Sonntag and
Jos{\'{e}} Flich and
Pascal Vivet},
title = {All routes to efficient datacenter fabrics},
booktitle = {Proceedings of the 8th International Workshop on Interconnection Network
Architecture - On-Chip, Multi-Chip, {INA-OCMC} 2014, Vienna, Austria,
January 22, 2014},
pages = {4:1--4:4},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2556857.2556861},
doi = {10.1145/2556857.2556861},
timestamp = {Fri, 17 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/ChrysosNGMDB14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/DangerDGS14,
author = {Jean{-}Luc Danger and
Nicolas Debande and
Sylvain Guilley and
Youssef Souissi},
editor = {Jens Knoop and
Valentina Salapura and
Israel Koren and
Gerardo Pelosi},
title = {High-order timing attacks},
booktitle = {Proceedings of the First Workshop on Cryptography and Security in
Computing Systems, CS2@HiPEAC 2014, Vienna, Austria, January 20, 2014},
pages = {7--12},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2556315.2556316},
doi = {10.1145/2556315.2556316},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/DangerDGS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/GohringerT14,
author = {Diana G{\"{o}}hringer and
Jan Tepelmann},
editor = {Cristina Silvano and
Jo{\~{a}}o M. P. Cardoso and
Michael H{\"{u}}bner},
title = {An Interactive Tool based on Polly for Detection and Parallelization
of Loops},
booktitle = {Proceedings of the 5th Workshop on Parallel Programming and Run-Time
Management Techniques for Many-core Architectures and the 3rd Workshop
on Design Tools and Architectures for Multicore Embedded Computing
Platforms, {PARMA-DITAM} 2014, Vienna, Austria, January 20, 2014},
pages = {1--6},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2556863.2556869},
doi = {10.1145/2556863.2556869},
timestamp = {Wed, 28 Apr 2021 16:06:57 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/GohringerT14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/GominaGCRT14,
author = {Kamil Gomina and
Philippe Gendrier and
Philippe Candelier and
Jean{-}Baptiste Rigaud and
Assia Tria},
editor = {Jens Knoop and
Valentina Salapura and
Israel Koren and
Gerardo Pelosi},
title = {Detecting positive voltage attacks on {CMOS} circuits},
booktitle = {Proceedings of the First Workshop on Cryptography and Security in
Computing Systems, CS2@HiPEAC 2014, Vienna, Austria, January 20, 2014},
pages = {1--6},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2556315.2556320},
doi = {10.1145/2556315.2556320},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/GominaGCRT14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/HarbinI14,
author = {James Harbin and
Leandro Soares Indrusiak},
editor = {Cristina Silvano and
Jo{\~{a}}o M. P. Cardoso and
Michael H{\"{u}}bner},
title = {Fine-Grained Link Locking Within Power and Latency Transaction Level
Modelling in Wormhole Switching Non-Preemptive Networks On Chip},
booktitle = {Proceedings of the 5th Workshop on Parallel Programming and Run-Time
Management Techniques for Many-core Architectures and the 3rd Workshop
on Design Tools and Architectures for Multicore Embedded Computing
Platforms, {PARMA-DITAM} 2014, Vienna, Austria, January 20, 2014},
pages = {33--38},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2556863.2556865},
doi = {10.1145/2556863.2556865},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/HarbinI14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/LacknerBWS14,
author = {Michael Lackner and
Reinhard Berlach and
Reinhold Weiss and
Christian Steger},
editor = {Jens Knoop and
Valentina Salapura and
Israel Koren and
Gerardo Pelosi},
title = {Countering type confusion and buffer overflow attacks on Java smart
cards by data type sensitive obfuscation},
booktitle = {Proceedings of the First Workshop on Cryptography and Security in
Computing Systems, CS2@HiPEAC 2014, Vienna, Austria, January 20, 2014},
pages = {19--24},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2556315.2556317},
doi = {10.1145/2556315.2556317},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/LacknerBWS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/LibuttiMBF14,
author = {Simone Libutti and
Giuseppe Massari and
Patrick Bellasi and
William Fornaciari},
editor = {Cristina Silvano and
Jo{\~{a}}o M. P. Cardoso and
Michael H{\"{u}}bner},
title = {Exploiting Performance Counters for Energy Efficient Co-Scheduling
of Mixed Workloads on Multi-Core Platforms},
booktitle = {Proceedings of the 5th Workshop on Parallel Programming and Run-Time
Management Techniques for Many-core Architectures and the 3rd Workshop
on Design Tools and Architectures for Multicore Embedded Computing
Platforms, {PARMA-DITAM} 2014, Vienna, Austria, January 20, 2014},
pages = {27--32},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2556863.2556866},
doi = {10.1145/2556863.2556866},
timestamp = {Wed, 25 Sep 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/LibuttiMBF14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/MassariCBF14,
author = {Giuseppe Massari and
Chiara Caffarri and
Patrick Bellasi and
William Fornaciari},
editor = {Cristina Silvano and
Jo{\~{a}}o M. P. Cardoso and
Michael H{\"{u}}bner},
title = {Extending a Run-time Resource Management framework to support OpenCL
and Heterogeneous Systems},
booktitle = {Proceedings of the 5th Workshop on Parallel Programming and Run-Time
Management Techniques for Many-core Architectures and the 3rd Workshop
on Design Tools and Architectures for Multicore Embedded Computing
Platforms, {PARMA-DITAM} 2014, Vienna, Austria, January 20, 2014},
pages = {21--26},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2556863.2556868},
doi = {10.1145/2556863.2556868},
timestamp = {Wed, 25 Sep 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/MassariCBF14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/NobrePCCD14,
author = {Ricardo Nobre and
Pedro Pinto and
Tiago Carvalho and
Jo{\~{a}}o M. P. Cardoso and
Pedro C. Diniz},
editor = {Cristina Silvano and
Jo{\~{a}}o M. P. Cardoso and
Michael H{\"{u}}bner},
title = {On Expressing Strategies for Directive-Driven Multicore Programing
Models},
booktitle = {Proceedings of the 5th Workshop on Parallel Programming and Run-Time
Management Techniques for Many-core Architectures and the 3rd Workshop
on Design Tools and Architectures for Multicore Embedded Computing
Platforms, {PARMA-DITAM} 2014, Vienna, Austria, January 20, 2014},
pages = {7--12},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2556863.2556870},
doi = {10.1145/2556863.2556870},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/NobrePCCD14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/PicekEBJCG14,
author = {Stjepan Picek and
Baris Ege and
Lejla Batina and
Domagoj Jakobovic and
Lukasz Chmielewski and
Marin Golub},
editor = {Jens Knoop and
Valentina Salapura and
Israel Koren and
Gerardo Pelosi},
title = {On using genetic algorithms for intrinsic side-channel resistance:
the case of {AES} S-box},
booktitle = {Proceedings of the First Workshop on Cryptography and Security in
Computing Systems, CS2@HiPEAC 2014, Vienna, Austria, January 20, 2014},
pages = {13--18},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2556315.2556319},
doi = {10.1145/2556315.2556319},
timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/PicekEBJCG14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/PrisacariRG0BM14,
author = {Bogdan Prisacari and
Germ{\'{a}}n Rodr{\'{\i}}guez and
Marina Garc{\'{\i}}a and
Enrique Vallejo and
Ram{\'{o}}n Beivide and
Cyriel Minkenberg},
editor = {Giorgos Dimitrakopoulos and
S{\"{o}}ren Sonntag and
Jos{\'{e}} Flich and
Pascal Vivet},
title = {Performance implications of remote-only load balancing under adversarial
traffic in Dragonflies},
booktitle = {Proceedings of the 8th International Workshop on Interconnection Network
Architecture - On-Chip, Multi-Chip, {INA-OCMC} 2014, Vienna, Austria,
January 22, 2014},
pages = {5:1--5:4},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2556857.2556860},
doi = {10.1145/2556857.2556860},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/PrisacariRG0BM14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/RathodBG14,
author = {Nihar Rathod and
Shankar Balachandran and
Neel Gala},
editor = {Giorgos Dimitrakopoulos and
S{\"{o}}ren Sonntag and
Jos{\'{e}} Flich and
Pascal Vivet},
title = {{CAERUS:} an effective arbitration and ejection policy for routing
in an unidirectional torus},
booktitle = {Proceedings of the 8th International Workshop on Interconnection Network
Architecture - On-Chip, Multi-Chip, {INA-OCMC} 2014, Vienna, Austria,
January 22, 2014},
pages = {1:1--1:4},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2556857.2556858},
doi = {10.1145/2556857.2556858},
timestamp = {Fri, 17 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/RathodBG14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/SaraswatFKD14,
author = {Vishal Saraswat and
Daniel Feldman and
Denis Foo Kune and
Satyajit Das},
editor = {Jens Knoop and
Valentina Salapura and
Israel Koren and
Gerardo Pelosi},
title = {Remote cache-timing attacks against {AES}},
booktitle = {Proceedings of the First Workshop on Cryptography and Security in
Computing Systems, CS2@HiPEAC 2014, Vienna, Austria, January 20, 2014},
pages = {45--48},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2556315.2556322},
doi = {10.1145/2556315.2556322},
timestamp = {Mon, 16 Sep 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/SaraswatFKD14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/SchnarzWS14,
author = {Pierre Schnarz and
Joachim Wietzke and
Ingo Stengel},
editor = {Jens Knoop and
Valentina Salapura and
Israel Koren and
Gerardo Pelosi},
title = {Towards attacks on restricted memory areas through co-processors in
embedded multi-OS environments via malicious firmware injection},
booktitle = {Proceedings of the First Workshop on Cryptography and Security in
Computing Systems, CS2@HiPEAC 2014, Vienna, Austria, January 20, 2014},
pages = {25--30},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2556315.2556318},
doi = {10.1145/2556315.2556318},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/SchnarzWS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/SeepersSSZ14,
author = {Robert M. Seepers and
Christos Strydis and
Ioannis Sourdis and
Chris I. De Zeeuw},
editor = {Jens Knoop and
Valentina Salapura and
Israel Koren and
Gerardo Pelosi},
title = {Adaptive entity-identifier generation for {IMD} emergency access},
booktitle = {Proceedings of the First Workshop on Cryptography and Security in
Computing Systems, CS2@HiPEAC 2014, Vienna, Austria, January 20, 2014},
pages = {41--44},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2556315.2556324},
doi = {10.1145/2556315.2556324},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/SeepersSSZ14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/SideropoulosP14,
author = {Thomas Sideropoulos and
Nikos P. Pitsianis},
editor = {Cristina Silvano and
Jo{\~{a}}o M. P. Cardoso and
Michael H{\"{u}}bner},
title = {A cycle-accurate synthesizable {MIPS} simulator in Simulink},
booktitle = {Proceedings of the 5th Workshop on Parallel Programming and Run-Time
Management Techniques for Many-core Architectures and the 3rd Workshop
on Design Tools and Architectures for Multicore Embedded Computing
Platforms, {PARMA-DITAM} 2014, Vienna, Austria, January 20, 2014},
pages = {17--20},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2556863.2556867},
doi = {10.1145/2556863.2556867},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/SideropoulosP14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/Sotiriou-Xanthopoulos14,
author = {Efstathios Sotiriou{-}Xanthopoulos and
Sotirios Xydis and
Kostas Siozios and
George Economakos and
Dimitrios Soudris},
editor = {Cristina Silvano and
Jo{\~{a}}o M. P. Cardoso and
Michael H{\"{u}}bner},
title = {Effective Platform-Level Exploration for Heterogeneous Multicores
Exploiting Simulation-Induced Slacks},
booktitle = {Proceedings of the 5th Workshop on Parallel Programming and Run-Time
Management Techniques for Many-core Architectures and the 3rd Workshop
on Design Tools and Architectures for Multicore Embedded Computing
Platforms, {PARMA-DITAM} 2014, Vienna, Austria, January 20, 2014},
pages = {13--16},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2556863.2556864},
doi = {10.1145/2556863.2556864},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/Sotiriou-Xanthopoulos14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/SpreitzerS14,
author = {Raphael Spreitzer and
J{\"{o}}rn{-}Marc Schmidt},
editor = {Jens Knoop and
Valentina Salapura and
Israel Koren and
Gerardo Pelosi},
title = {Group-signature schemes on constrained devices: the gap between theory
and practice},
booktitle = {Proceedings of the First Workshop on Cryptography and Security in
Computing Systems, CS2@HiPEAC 2014, Vienna, Austria, January 20, 2014},
pages = {31--36},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2556315.2556321},
doi = {10.1145/2556315.2556321},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/SpreitzerS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/StranoGFB14,
author = {Alessandro Strano and
Alberto Ghiribaldi and
Herv{\'{e}} Tatenguem Fankem and
Davide Bertozzi},
editor = {Giorgos Dimitrakopoulos and
S{\"{o}}ren Sonntag and
Jos{\'{e}} Flich and
Pascal Vivet},
title = {A feature-rich NoC switch with cross-feature optimizations for the
next generation of reliable and reconfigurable embedded systems},
booktitle = {Proceedings of the 8th International Workshop on Interconnection Network
Architecture - On-Chip, Multi-Chip, {INA-OCMC} 2014, Vienna, Austria,
January 22, 2014},
pages = {2:1--2:4},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2556857.2556859},
doi = {10.1145/2556857.2556859},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/StranoGFB14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/hipeac/2014cs,
editor = {Jens Knoop and
Valentina Salapura and
Israel Koren and
Gerardo Pelosi},
title = {Proceedings of the First Workshop on Cryptography and Security in
Computing Systems, CS2@HiPEAC 2014, Vienna, Austria, January 20, 2014},
publisher = {{ACM}},
year = {2014},
url = {http://dl.acm.org/citation.cfm?id=2556315},
isbn = {978-1-4503-2484-7},
timestamp = {Wed, 06 May 2015 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/2014cs.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/hipeac/2014ina-ocmc,
editor = {Giorgos Dimitrakopoulos and
S{\"{o}}ren Sonntag and
Jos{\'{e}} Flich and
Pascal Vivet},
title = {Proceedings of the 8th International Workshop on Interconnection Network
Architecture - On-Chip, Multi-Chip, {INA-OCMC} 2014, Vienna, Austria,
January 22, 2014},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2556857},
doi = {10.1145/2556857},
isbn = {978-1-4503-2639-1},
timestamp = {Fri, 17 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/2014ina-ocmc.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/hipeac/2014parma,
editor = {Cristina Silvano and
Jo{\~{a}}o M. P. Cardoso and
Michael H{\"{u}}bner},
title = {Proceedings of the 5th Workshop on Parallel Programming and Run-Time
Management Techniques for Many-core Architectures and the 3rd Workshop
on Design Tools and Architectures for Multicore Embedded Computing
Platforms, {PARMA-DITAM} 2014, Vienna, Austria, January 20, 2014},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2556863},
doi = {10.1145/2556863},
isbn = {978-1-4503-2607-0},
timestamp = {Wed, 28 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/2014parma.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/AbadPG13,
author = {Pablo Abad Fidalgo and
Valentin Puente and
Jos{\'{e}}{-}{\'{A}}ngel Gregorio},
title = {{LIGERO:} {A} light but efficient router conceived for cache-coherent
chip multiprocessors},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {9},
number = {4},
pages = {37:1--37:21},
year = {2013},
url = {https://doi.org/10.1145/2400682.2400696},
doi = {10.1145/2400682.2400696},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/AbadPG13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/AlbericioIVL13,
author = {Jorge Albericio and
Pablo Ib{\'{a}}{\~{n}}ez and
V{\'{\i}}ctor Vi{\~{n}}als and
Jos{\'{e}} Mar{\'{\i}}a Llaber{\'{\i}}a},
title = {Exploiting reuse locality on inclusive shared last-level caches},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {9},
number = {4},
pages = {38:1--38:19},
year = {2013},
url = {https://doi.org/10.1145/2400682.2400697},
doi = {10.1145/2400682.2400697},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/AlbericioIVL13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/AntaoS13,
author = {Samuel Antao and
Leonel Sousa},
title = {The {CRNS} framework and its application to programmable and reconfigurable
cryptography},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {9},
number = {4},
pages = {33:1--33:25},
year = {2013},
url = {https://doi.org/10.1145/2400682.2400692},
doi = {10.1145/2400682.2400692},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/AntaoS13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/BaghdadiCVT13,
author = {Riyadh Baghdadi and
Albert Cohen and
Sven Verdoolaege and
Konrad Trifunovic},
title = {Improved loop tiling based on the removal of spurious false dependences},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {9},
number = {4},
pages = {52:1--52:26},
year = {2013},
url = {https://doi.org/10.1145/2400682.2400711},
doi = {10.1145/2400682.2400711},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/BaghdadiCVT13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/BelviranliBG13,
author = {Mehmet E. Belviranli and
Laxmi N. Bhuyan and
Rajiv Gupta},
title = {A dynamic self-scheduling scheme for heterogeneous multiprocessor
architectures},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {9},
number = {4},
pages = {57:1--57:20},
year = {2013},
url = {https://doi.org/10.1145/2400682.2400716},
doi = {10.1145/2400682.2400716},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/BelviranliBG13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/BoisEE13,
author = {Kristof Du Bois and
Stijn Eyerman and
Lieven Eeckhout},
title = {Per-thread cycle accounting in multicore processors},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {9},
number = {4},
pages = {29:1--29:22},
year = {2013},
url = {https://doi.org/10.1145/2400682.2400688},
doi = {10.1145/2400682.2400688},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/BoisEE13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/ChenS13,
author = {Doris Chen and
Deshanand P. Singh},
title = {Profile-guided floating- to fixed-point conversion for hybrid FPGA-processor
applications},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {9},
number = {4},
pages = {43:1--43:25},
year = {2013},
url = {https://doi.org/10.1145/2400682.2400702},
doi = {10.1145/2400682.2400702},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/ChenS13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/ChrysosDPD13,
author = {Grigorios Chrysos and
Panagiotis Dagritzikos and
Ioannis Papaefstathiou and
Apostolos Dollas},
title = {{HC-CART:} {A} parallel system implementation of data mining classification
and regression tree {(CART)} algorithm on a multi-FPGA system},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {9},
number = {4},
pages = {47:1--47:25},
year = {2013},
url = {https://doi.org/10.1145/2400682.2400706},
doi = {10.1145/2400682.2400706},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/ChrysosDPD13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/ClearyCPG13,
author = {Jimmy Cleary and
Owen Callanan and
Mark Purcell and
David Gregg},
title = {Fast asymmetric thread synchronization},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {9},
number = {4},
pages = {27:1--27:22},
year = {2013},
url = {https://doi.org/10.1145/2400682.2400686},
doi = {10.1145/2400682.2400686},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/ClearyCPG13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/CoelhoI13,
author = {Fabien Coelho and
Fran{\c{c}}ois Irigoin},
title = {{API} compilation for image hardware accelerators},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {9},
number = {4},
pages = {49:1--49:25},
year = {2013},
url = {https://doi.org/10.1145/2400682.2400708},
doi = {10.1145/2400682.2400708},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/CoelhoI13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/CoppensSM13,
author = {Bart Coppens and
Bjorn De Sutter and
Jonas Maebe},
title = {Feedback-driven binary code diversification},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {9},
number = {4},
pages = {24:1--24:26},
year = {2013},
url = {https://doi.org/10.1145/2400682.2400683},
doi = {10.1145/2400682.2400683},
timestamp = {Mon, 07 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/CoppensSM13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/CraeynestE13,
author = {Kenzo Van Craeynest and
Lieven Eeckhout},
title = {Understanding fundamental design choices in single-ISA heterogeneous
multicore architectures},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {9},
number = {4},
pages = {32:1--32:23},
year = {2013},
url = {https://doi.org/10.1145/2400682.2400691},
doi = {10.1145/2400682.2400691},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/CraeynestE13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/CuiWCS13,
author = {Yan Cui and
Yingxin Wang and
Yu Chen and
Yuanchun Shi},
title = {Lock-contention-aware scheduler: {A} scalable and energy-efficient
method for addressing scalability collapse on multicore systems},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {9},
number = {4},
pages = {44:1--44:25},
year = {2013},
url = {https://doi.org/10.1145/2400682.2400703},
doi = {10.1145/2400682.2400703},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/CuiWCS13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/CuiYXF13,
author = {Huimin Cui and
Qing Yi and
Jingling Xue and
Xiaobing Feng},
title = {Layout-oblivious compiler optimization for matrix computations},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {9},
number = {4},
pages = {35:1--35:20},
year = {2013},
url = {https://doi.org/10.1145/2400682.2400694},
doi = {10.1145/2400682.2400694},
timestamp = {Sun, 22 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/taco/CuiYXF13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/DioufHCOP13,
author = {Boubacar Diouf and
Can Hantas and
Albert Cohen and
{\"{O}}zcan {\"{O}}zturk and
Jens Palsberg},
title = {A decoupled local memory allocator},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {9},
number = {4},
pages = {34:1--34:22},
year = {2013},
url = {https://doi.org/10.1145/2400682.2400693},
doi = {10.1145/2400682.2400693},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/DioufHCOP13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/DolanMG13,
author = {Stephen Dolan and
Servesh Muralidharan and
David Gregg},
title = {Compiler support for lightweight context switching},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {9},
number = {4},
pages = {36:1--36:25},
year = {2013},
url = {https://doi.org/10.1145/2400682.2400695},
doi = {10.1145/2400682.2400695},
timestamp = {Sun, 22 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/taco/DolanMG13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/DuZCMM13,
author = {Yu Du and
Miao Zhou and
Bruce R. Childers and
Rami G. Melhem and
Daniel Moss{\'{e}}},
title = {Delta-compressed caching for overcoming the write bandwidth limitation
of hybrid main memory},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {9},
number = {4},
pages = {55:1--55:20},
year = {2013},
url = {https://doi.org/10.1145/2400682.2400714},
doi = {10.1145/2400682.2400714},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/DuZCMM13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/FowersBWS13,
author = {Jeremy Fowers and
Greg Brown and
John Robert Wernsing and
Greg Stitt},
title = {A performance and energy comparison of convolution on GPUs, FPGAs,
and multicore processors},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {9},
number = {4},
pages = {25:1--25:21},
year = {2013},
url = {https://doi.org/10.1145/2400682.2400684},
doi = {10.1145/2400682.2400684},
timestamp = {Thu, 25 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/taco/FowersBWS13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/GerardsK13,
author = {Marco Gerards and
Jan Kuper},
title = {Optimal {DPM} and {DVFS} for frame-based real-time systems},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {9},
number = {4},
pages = {41:1--41:23},
year = {2013},
url = {https://doi.org/10.1145/2400682.2400700},
doi = {10.1145/2400682.2400700},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/GerardsK13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/KhanBRHCC13,
author = {Malik Murtaza Khan and
Protonu Basu and
Gabe Rudy and
Mary W. Hall and
Chun Chen and
Jacqueline Chame},
title = {A script-based autotuning compiler system to generate high-performance
{CUDA} code},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {9},
number = {4},
pages = {31:1--31:25},
year = {2013},
url = {https://doi.org/10.1145/2400682.2400690},
doi = {10.1145/2400682.2400690},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/taco/KhanBRHCC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/LeeKLYP13,
author = {Jongwon Lee and
Yohan Ko and
Kyoungwoo Lee and
Jonghee M. Youn and
Yunheung Paek},
title = {Dynamic code duplication with vulnerability awareness for soft error
detection on {VLIW} architectures},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {9},
number = {4},
pages = {48:1--48:24},
year = {2013},
url = {https://doi.org/10.1145/2400682.2400707},
doi = {10.1145/2400682.2400707},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/LeeKLYP13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/LiMJ13,
author = {Yong Li and
Rami G. Melhem and
Alex K. Jones},
title = {{PS-TLB:} Leveraging page classification information for fast, scalable
and efficient translation for future CMPs},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {9},
number = {4},
pages = {28:1--28:21},
year = {2013},
url = {https://doi.org/10.1145/2400682.2400687},
doi = {10.1145/2400682.2400687},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/LiMJ13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/LuqueMCV13,
author = {Carlos Luque and
Miquel Moret{\'{o}} and
Francisco J. Cazorla and
Mateo Valero},
title = {Fair {CPU} time accounting in {CMP+SMT} processors},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {9},
number = {4},
pages = {50:1--50:25},
year = {2013},
url = {https://doi.org/10.1145/2400682.2400709},
doi = {10.1145/2400682.2400709},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/taco/LuqueMCV13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/LutzFC13,
author = {Thibaut Lutz and
Christian Fensch and
Murray Cole},
title = {{PARTANS:} An autotuning framework for stencil computation on multi-GPU
systems},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {9},
number = {4},
pages = {59:1--59:24},
year = {2013},
url = {https://doi.org/10.1145/2400682.2400718},
doi = {10.1145/2400682.2400718},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/LutzFC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/MattheakisP13,
author = {Pavlos M. Mattheakis and
Ioannis Papaefstathiou},
title = {Significantly reducing {MPI} intercommunication latency and power
overhead in both embedded and {HPC} systems},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {9},
number = {4},
pages = {51:1--51:25},
year = {2013},
url = {https://doi.org/10.1145/2400682.2400710},
doi = {10.1145/2400682.2400710},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/MattheakisP13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/NegiG13,
author = {Anurag Negi and
J. Rub{\'{e}}n Titos Gil},
title = {SCIN-cache: Fast speculative versioning in multithreaded cores},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {9},
number = {4},
pages = {58:1--58:26},
year = {2013},
url = {https://doi.org/10.1145/2400682.2400717},
doi = {10.1145/2400682.2400717},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/NegiG13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/NugterenCC13,
author = {Cedric Nugteren and
Pieter Custers and
Henk Corporaal},
title = {Algorithmic species: {A} classification of affine loop nests for parallel
programming},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {9},
number = {4},
pages = {40:1--40:25},
year = {2013},
url = {https://doi.org/10.1145/2400682.2400699},
doi = {10.1145/2400682.2400699},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/NugterenCC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/PopC13,
author = {Antoniu Pop and
Albert Cohen},
title = {OpenStream: Expressiveness and data-flow compilation of OpenMP streaming
programs},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {9},
number = {4},
pages = {53:1--53:25},
year = {2013},
url = {https://doi.org/10.1145/2400682.2400712},
doi = {10.1145/2400682.2400712},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/PopC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/PuriniJ13,
author = {Suresh Purini and
Lakshya Jain},
title = {Finding good optimization sequences covering program space},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {9},
number = {4},
pages = {56:1--56:23},
year = {2013},
url = {https://doi.org/10.1145/2400682.2400715},
doi = {10.1145/2400682.2400715},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/PuriniJ13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/PusukuriGB13,
author = {Kishore Kumar Pusukuri and
Rajiv Gupta and
Laxmi N. Bhuyan},
title = {{ADAPT:} {A} framework for coscheduling multithreaded programs},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {9},
number = {4},
pages = {45:1--45:24},
year = {2013},
url = {https://doi.org/10.1145/2400682.2400704},
doi = {10.1145/2400682.2400704},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/PusukuriGB13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/RohouWY13,
author = {Erven Rohou and
Kevin Williams and
David Yuste},
title = {Vectorization technology to improve interpreter performance},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {9},
number = {4},
pages = {26:1--26:22},
year = {2013},
url = {https://doi.org/10.1145/2400682.2400685},
doi = {10.1145/2400682.2400685},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/taco/RohouWY13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/TartaraC13,
author = {Michele Tartara and
Stefano Crespi{-}Reghizzi},
title = {Continuous learning of compiler heuristics},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {9},
number = {4},
pages = {46:1--46:25},
year = {2013},
url = {https://doi.org/10.1145/2400682.2400705},
doi = {10.1145/2400682.2400705},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/taco/TartaraC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/VerdoolaegeJCGTC13,
author = {Sven Verdoolaege and
Juan Carlos Juega and
Albert Cohen and
Jos{\'{e}} Ignacio G{\'{o}}mez and
Christian Tenllado and
Francky Catthoor},
title = {Polyhedral parallel code generation for {CUDA}},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {9},
number = {4},
pages = {54:1--54:23},
year = {2013},
url = {https://doi.org/10.1145/2400682.2400713},
doi = {10.1145/2400682.2400713},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/VerdoolaegeJCGTC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/WimmerHVJDS13,
author = {Christian Wimmer and
Michael Haupt and
Michael L. Van de Vanter and
Mick J. Jordan and
Laurent Dayn{\`{e}}s and
Doug Simon},
title = {Maxine: An approachable virtual machine for, and in, java},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {9},
number = {4},
pages = {30:1--30:24},
year = {2013},
url = {https://doi.org/10.1145/2400682.2400689},
doi = {10.1145/2400682.2400689},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/WimmerHVJDS13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/XiaoCCGHLRW13,
author = {Chunhua Xiao and
M.{-}C. Frank Chang and
Jason Cong and
Michael Gill and
Zhangqin Huang and
Chunyue Liu and
Glenn Reinman and
Hao Wu},
title = {Stream arbitration: Towards efficient bandwidth utilization for emerging
on-chip interconnects},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {9},
number = {4},
pages = {60:1--60:27},
year = {2013},
url = {https://doi.org/10.1145/2400682.2400719},
doi = {10.1145/2400682.2400719},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/XiaoCCGHLRW13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/YanJTF13,
author = {Zhichao Yan and
Hong Jiang and
Yujuan Tan and
Dan Feng},
title = {An integrated pseudo-associativity and relaxed-order approach to hardware
transactional memory},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {9},
number = {4},
pages = {42:1--42:26},
year = {2013},
url = {https://doi.org/10.1145/2400682.2400701},
doi = {10.1145/2400682.2400701},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/YanJTF13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/YiapanisRBL13,
author = {Paraskevas Yiapanis and
Demian Rosas{-}Ham and
Gavin Brown and
Mikel Luj{\'{a}}n},
title = {Optimizing software runtime systems for speculative parallelization},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {9},
number = {4},
pages = {39:1--39:27},
year = {2013},
url = {https://doi.org/10.1145/2400682.2400698},
doi = {10.1145/2400682.2400698},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/YiapanisRBL13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/ChrysosNGCMBV13,
author = {Nikolaos Chrysos and
Fredy D. Neeser and
Mitch Gusat and
Rolf Clauberg and
Cyriel Minkenberg and
Claude Basso and
Kenneth M. Valk},
title = {Arbitration of many thousand flows at 100G and beyond},
booktitle = {Proceedings of the 2013 Interconnection Network Architecture: On-Chip,
Multi-Chip, IMA-OCMC@HiPEAC 2013, Berlin, Germany, January 23, 2013},
pages = {5--8},
publisher = {{ACM}},
year = {2013},
url = {https://doi.org/10.1145/2482759.2482761},
doi = {10.1145/2482759.2482761},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/ChrysosNGCMBV13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/CrisanBCG13,
author = {Daniel Crisan and
Robert Birke and
Nikolaos Chrysos and
Mitch Gusat},
title = {How elastic is your virtualized datacenter fabric?},
booktitle = {Proceedings of the 2013 Interconnection Network Architecture: On-Chip,
Multi-Chip, IMA-OCMC@HiPEAC 2013, Berlin, Germany, January 23, 2013},
pages = {17--20},
publisher = {{ACM}},
year = {2013},
url = {https://doi.org/10.1145/2482759.2482764},
doi = {10.1145/2482759.2482764},
timestamp = {Mon, 08 Jul 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/CrisanBCG13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/GarciaVBOCVLR13,
author = {Marina Garc{\'{\i}}a and
Enrique Vallejo and
Ram{\'{o}}n Beivide and
Miguel Odriozola and
Cristobal Camarero and
Mateo Valero and
Jes{\'{u}}s Labarta and
Germ{\'{a}}n Rodr{\'{\i}}guez},
title = {Global misrouting policies in two-level hierarchical networks},
booktitle = {Proceedings of the 2013 Interconnection Network Architecture: On-Chip,
Multi-Chip, IMA-OCMC@HiPEAC 2013, Berlin, Germany, January 23, 2013},
pages = {13--16},
publisher = {{ACM}},
year = {2013},
url = {https://doi.org/10.1145/2482759.2482763},
doi = {10.1145/2482759.2482763},
timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/GarciaVBOCVLR13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/JokanovicPRM13,
author = {Ana Jokanovic and
Bogdan Prisacari and
Germ{\'{a}}n Rodr{\'{\i}}guez and
Cyriel Minkenberg},
title = {Randomizing task placement does not randomize traffic (enough)},
booktitle = {Proceedings of the 2013 Interconnection Network Architecture: On-Chip,
Multi-Chip, IMA-OCMC@HiPEAC 2013, Berlin, Germany, January 23, 2013},
pages = {9--12},
publisher = {{ACM}},
year = {2013},
url = {https://doi.org/10.1145/2482759.2482762},
doi = {10.1145/2482759.2482762},
timestamp = {Mon, 16 Sep 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/JokanovicPRM13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/OrtinFAGVIV13,
author = {Marta Ort{\'{\i}}n and
Alexandra Ferreron and
Jorge Albericio and
Dar{\'{\i}}o Su{\'{a}}rez Gracia and
Mar{\'{\i}}a Villarroya{-}Gaud{\'{o}} and
Cruz Izu and
V{\'{\i}}ctor Vi{\~{n}}als},
title = {Characterization and cost-efficient selection of NoC topologies for
general purpose CMPs},
booktitle = {Proceedings of the 2013 Interconnection Network Architecture: On-Chip,
Multi-Chip, IMA-OCMC@HiPEAC 2013, Berlin, Germany, January 23, 2013},
pages = {21--24},
publisher = {{ACM}},
year = {2013},
url = {https://doi.org/10.1145/2482759.2482765},
doi = {10.1145/2482759.2482765},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/OrtinFAGVIV13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/TrivinoBF13,
author = {Francisco Trivi{\~{n}}o and
Davide Bertozzi and
Jos{\'{e}} Flich},
title = {A fast algorithm for runtime reconfiguration to maximize the lifetime
of nanoscale NoCs},
booktitle = {Proceedings of the 2013 Interconnection Network Architecture: On-Chip,
Multi-Chip, IMA-OCMC@HiPEAC 2013, Berlin, Germany, January 23, 2013},
pages = {1--4},
publisher = {{ACM}},
year = {2013},
url = {https://doi.org/10.1145/2482759.2482760},
doi = {10.1145/2482759.2482760},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/TrivinoBF13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/ZoniF13,
author = {Davide Zoni and
William Fornaciari},
title = {NBTI-aware design of NoC buffers},
booktitle = {Proceedings of the 2013 Interconnection Network Architecture: On-Chip,
Multi-Chip, IMA-OCMC@HiPEAC 2013, Berlin, Germany, January 23, 2013},
pages = {25--28},
publisher = {{ACM}},
year = {2013},
url = {https://doi.org/10.1145/2482759.2482766},
doi = {10.1145/2482759.2482766},
timestamp = {Mon, 16 Sep 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/ZoniF13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/hipeac/2013ina-ocmc,
title = {Proceedings of the 2013 Interconnection Network Architecture: On-Chip,
Multi-Chip, IMA-OCMC@HiPEAC 2013, Berlin, Germany, January 23, 2013},
publisher = {{ACM}},
year = {2013},
url = {https://doi.org/10.1145/2482759},
doi = {10.1145/2482759},
isbn = {978-1-4503-1784-9},
timestamp = {Mon, 08 Jul 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/2013ina-ocmc.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/AlbericioTIVL12,
author = {Jorge Albericio and
Ruben Gran Tejero and
Pablo Ib{\'{a}}{\~{n}}ez and
V{\'{\i}}ctor Vi{\~{n}}als and
Jos{\'{e}} Mar{\'{\i}}a Llaber{\'{\i}}a},
title = {{ABS:} {A} low-cost adaptive controller for prefetching in a banked
shared last-level cache},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {8},
number = {4},
pages = {19:1--19:20},
year = {2012},
url = {https://doi.org/10.1145/2086696.2086698},
doi = {10.1145/2086696.2086698},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/AlbericioTIVL12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/BayrakVIB12,
author = {Ali Galip Bayrak and
Nikola Velickovic and
Paolo Ienne and
Wayne P. Burleson},
title = {An architecture-independent instruction shuffler to protect against
side-channel attacks},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {8},
number = {4},
pages = {20:1--20:19},
year = {2012},
url = {https://doi.org/10.1145/2086696.2086699},
doi = {10.1145/2086696.2086699},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/BayrakVIB12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/BogdanskiRSG12,
author = {Bartosz Bogdanski and
Sven{-}Arne Reinemo and
Frank Olaf Sem{-}Jacobsen and
Ernst Gunnar Gran},
title = {sFtree: {A} fully connected and deadlock-free switch-to-switch routing
algorithm for fat-trees},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {8},
number = {4},
pages = {55:1--55:20},
year = {2012},
url = {https://doi.org/10.1145/2086696.2086734},
doi = {10.1145/2086696.2086734},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/taco/BogdanskiRSG12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/BruintjesWGMS12,
author = {Tom M. Bruintjes and
Karel H. G. Walters and
Sabih H. Gerez and
Bert Molenkamp and
Gerard J. M. Smit},
title = {Sabrewing: {A} lightweight architecture for combined floating-point
and integer arithmetic},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {8},
number = {4},
pages = {41:1--41:22},
year = {2012},
url = {https://doi.org/10.1145/2086696.2086720},
doi = {10.1145/2086696.2086720},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/BruintjesWGMS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/CleemputCS12,
author = {Jeroen Van Cleemput and
Bart Coppens and
Bjorn De Sutter},
title = {Compiler mitigations for time attacks on modern x86 processors},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {8},
number = {4},
pages = {23:1--23:20},
year = {2012},
url = {https://doi.org/10.1145/2086696.2086702},
doi = {10.1145/2086696.2086702},
timestamp = {Sun, 22 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/taco/CleemputCS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/DasDU12,
author = {Dibyendu Das and
Beno{\^{\i}}t Dupont de Dinechin and
Ramakrishna Upadrasta},
title = {Efficient liveness computation using merge sets and DJ-graphs},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {8},
number = {4},
pages = {27:1--27:18},
year = {2012},
url = {https://doi.org/10.1145/2086696.2086706},
doi = {10.1145/2086696.2086706},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/DasDU12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/DemmeS12,
author = {John Demme and
Simha Sethumadhavan},
title = {Approximate graph clustering for program characterization},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {8},
number = {4},
pages = {21:1--21:21},
year = {2012},
url = {https://doi.org/10.1145/2086696.2086700},
doi = {10.1145/2086696.2086700},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/DemmeS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/DomnitserJLAP12,
author = {Leonid Domnitser and
Aamer Jaleel and
Jason Loew and
Nael B. Abu{-}Ghazaleh and
Dmitry Ponomarev},
title = {Non-monopolizable caches: Low-complexity mitigation of cache side
channel attacks},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {8},
number = {4},
pages = {35:1--35:21},
year = {2012},
url = {https://doi.org/10.1145/2086696.2086714},
doi = {10.1145/2086696.2086714},
timestamp = {Thu, 25 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/taco/DomnitserJLAP12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/DongCPDJ12,
author = {Yaozu Dong and
Yu Chen and
Zhenhao Pan and
Jinquan Dai and
Yunhong Jiang},
title = {ReNIC: Architectural extension to {SR-IOV} {I/O} virtualization for
efficient replication},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {8},
number = {4},
pages = {40:1--40:22},
year = {2012},
url = {https://doi.org/10.1145/2086696.2086719},
doi = {10.1145/2086696.2086719},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/DongCPDJ12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/FengLG12,
author = {Min Feng and
Changhui Lin and
Rajiv Gupta},
title = {{PLDS:} Partitioning linked data structures for parallelism},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {8},
number = {4},
pages = {38:1--38:21},
year = {2012},
url = {https://doi.org/10.1145/2086696.2086717},
doi = {10.1145/2086696.2086717},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/FengLG12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/Garcia-GuiradoPRG12,
author = {Antonio Garc{\'{\i}}a{-}Guirado and
Ricardo Fern{\'{a}}ndez Pascual and
Alberto Ros and
Jos{\'{e}} M. Garc{\'{\i}}a},
title = {{DAPSCO:} Distance-aware partially shared cache organization},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {8},
number = {4},
pages = {25:1--25:19},
year = {2012},
url = {https://doi.org/10.1145/2086696.2086704},
doi = {10.1145/2086696.2086704},
timestamp = {Wed, 31 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/Garcia-GuiradoPRG12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/GilAGHCUHV12,
author = {J. Rub{\'{e}}n Titos Gil and
Manuel E. Acacio and
Jos{\'{e}} M. Garc{\'{\i}}a and
Tim Harris and
Adri{\'{a}}n Cristal and
Osman S. Unsal and
Ibrahim Hur and
Mateo Valero},
title = {Hardware transactional memory with software-defined conflicts},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {8},
number = {4},
pages = {31:1--31:20},
year = {2012},
url = {https://doi.org/10.1145/2086696.2086710},
doi = {10.1145/2086696.2086710},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/GilAGHCUHV12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/HasenplaughAJSE12,
author = {William Hasenplaugh and
Pritpal S. Ahuja and
Aamer Jaleel and
Simon C. Steely Jr. and
Joel S. Emer},
title = {The gradient-based cache partitioning algorithm},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {8},
number = {4},
pages = {44:1--44:21},
year = {2012},
url = {https://doi.org/10.1145/2086696.2086723},
doi = {10.1145/2086696.2086723},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/HasenplaughAJSE12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/KichererNBK12,
author = {Mario Kicherer and
Fabian Nowak and
Rainer Buchty and
Wolfgang Karl},
title = {Seamlessly portable applications: Managing the diversity of modern
heterogeneous systems},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {8},
number = {4},
pages = {42:1--42:20},
year = {2012},
url = {https://doi.org/10.1145/2086696.2086721},
doi = {10.1145/2086696.2086721},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/KichererNBK12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/KimLMP12,
author = {Yongjoo Kim and
Jongeun Lee and
Toan X. Mai and
Yunheung Paek},
title = {Improving performance of nested loops on reconfigurable array processors},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {8},
number = {4},
pages = {32:1--32:23},
year = {2012},
url = {https://doi.org/10.1145/2086696.2086711},
doi = {10.1145/2086696.2086711},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/KimLMP12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/LiraJMG12,
author = {Javier Lira and
Timothy M. Jones and
Carlos Molina and
Antonio Gonz{\'{a}}lez},
title = {The migration prefetcher: Anticipating data promotion in dynamic {NUCA}
caches},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {8},
number = {4},
pages = {45:1--45:20},
year = {2012},
url = {https://doi.org/10.1145/2086696.2086724},
doi = {10.1145/2086696.2086724},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/LiraJMG12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/LyonsHWB12,
author = {Michael J. Lyons and
Mark Hempstead and
Gu{-}Yeon Wei and
David M. Brooks},
title = {The accelerator store: {A} shared memory framework for accelerator-based
systems},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {8},
number = {4},
pages = {48:1--48:22},
year = {2012},
url = {https://doi.org/10.1145/2086696.2086727},
doi = {10.1145/2086696.2086727},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/LyonsHWB12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/MalitsBKM12,
author = {Roman Malits and
Evgeny Bolotin and
Avinoam Kolodny and
Avi Mendelson},
title = {Exploring the limits of {GPGPU} scheduling in control flow bound applications},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {8},
number = {4},
pages = {29:1--29:22},
year = {2012},
url = {https://doi.org/10.1145/2086696.2086708},
doi = {10.1145/2086696.2086708},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/taco/MalitsBKM12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/McCandlessG12,
author = {Jason McCandless and
David Gregg},
title = {Compiler techniques to improve dynamic branch prediction for indirect
jump and call instructions},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {8},
number = {4},
pages = {24:1--24:20},
year = {2012},
url = {https://doi.org/10.1145/2086696.2086703},
doi = {10.1145/2086696.2086703},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/McCandlessG12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/OrosaAB12,
author = {Lois Orosa and
Elisardo Antelo and
Javier D. Bruguera},
title = {FlexSig: Implementing flexible hardware signatures},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {8},
number = {4},
pages = {30:1--30:20},
year = {2012},
url = {https://doi.org/10.1145/2086696.2086709},
doi = {10.1145/2086696.2086709},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/OrosaAB12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/OrozcoGKLG12,
author = {Daniel A. Orozco and
Elkin Garcia and
Rishi Khan and
Kelly Livingston and
Guang R. Gao},
title = {Toward high-throughput algorithms on many-core architectures},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {8},
number = {4},
pages = {49:1--49:21},
year = {2012},
url = {https://doi.org/10.1145/2086696.2086728},
doi = {10.1145/2086696.2086728},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/OrozcoGKLG12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/PatsilarasCT12,
author = {George Patsilaras and
Niket K. Choudhary and
James Tuck},
title = {Efficiently exploiting memory level parallelism on asymmetric coupled
cores in the dark silicon era},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {8},
number = {4},
pages = {28:1--28:21},
year = {2012},
url = {https://doi.org/10.1145/2086696.2086707},
doi = {10.1145/2086696.2086707},
timestamp = {Tue, 23 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/PatsilarasCT12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/PradelleKC12,
author = {Beno{\^{\i}}t Pradelle and
Alain Ketterlin and
Philippe Clauss},
title = {Polyhedral parallelization of binary code},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {8},
number = {4},
pages = {39:1--39:21},
year = {2012},
url = {https://doi.org/10.1145/2086696.2086718},
doi = {10.1145/2086696.2086718},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/taco/PradelleKC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/PremillieuS12,
author = {Nathana{\"{e}}l Pr{\'{e}}millieu and
Andr{\'{e}} Seznec},
title = {{SYRANT:} SYmmetric resource allocation on not-taken and taken paths},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {8},
number = {4},
pages = {43:1--43:20},
year = {2012},
url = {https://doi.org/10.1145/2086696.2086722},
doi = {10.1145/2086696.2086722},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/taco/PremillieuS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/PricopiM12,
author = {Mihai Pricopi and
Tulika Mitra},
title = {Bahurupi: {A} polymorphic heterogeneous multi-core architecture},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {8},
number = {4},
pages = {22:1--22:21},
year = {2012},
url = {https://doi.org/10.1145/2086696.2086701},
doi = {10.1145/2086696.2086701},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/PricopiM12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/PurnaprajnaI12,
author = {Madhura Purnaprajna and
Paolo Ienne},
title = {Making wide-issue {VLIW} processors viable on FPGAs},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {8},
number = {4},
pages = {33:1--33:16},
year = {2012},
url = {https://doi.org/10.1145/2086696.2086712},
doi = {10.1145/2086696.2086712},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/PurnaprajnaI12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/PusukuriGB12,
author = {Kishore Kumar Pusukuri and
Rajiv Gupta and
Laxmi N. Bhuyan},
title = {Thread Tranquilizer: Dynamically reducing performance variation},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {8},
number = {4},
pages = {46:1--46:21},
year = {2012},
url = {https://doi.org/10.1145/2086696.2086725},
doi = {10.1145/2086696.2086725},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/PusukuriGB12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/RadojkovicGGQYC12,
author = {Petar Radojkovic and
Sylvain Girbal and
Arnaud Grasset and
Eduardo Qui{\~{n}}ones and
Sami Yehia and
Francisco J. Cazorla},
title = {On the evaluation of the impact of shared resources in multithreaded
{COTS} processors in time-critical environments},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {8},
number = {4},
pages = {34:1--34:25},
year = {2012},
url = {https://doi.org/10.1145/2086696.2086713},
doi = {10.1145/2086696.2086713},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/RadojkovicGGQYC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/RicoCVPVERV12,
author = {Alejandro Rico and
Felipe Cabarcas and
Carlos Villavieja and
Milan Pavlovic and
Augusto Vega and
Yoav Etsion and
Alex Ram{\'{\i}}rez and
Mateo Valero},
title = {On the simulation of large-scale architectures using multiple application
abstraction levels},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {8},
number = {4},
pages = {36:1--36:20},
year = {2012},
url = {https://doi.org/10.1145/2086696.2086715},
doi = {10.1145/2086696.2086715},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/RicoCVPVERV12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/RyckboschPE12,
author = {Frederick Ryckbosch and
Stijn Polfliet and
Lieven Eeckhout},
title = {VSim: Simulating multi-server setups at near native hardware speed},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {8},
number = {4},
pages = {52:1--52:20},
year = {2012},
url = {https://doi.org/10.1145/2086696.2086731},
doi = {10.1145/2086696.2086731},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/RyckboschPE12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/SaidiTLM12,
author = {Selma Saidi and
Pranav Tendulkar and
Thierry Lepley and
Oded Maler},
title = {Optimizing explicit data transfers for data parallel applications
on the cell architecture},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {8},
number = {4},
pages = {37:1--37:20},
year = {2012},
url = {https://doi.org/10.1145/2086696.2086716},
doi = {10.1145/2086696.2086716},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/SaidiTLM12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/StenstromB12,
author = {Per Stenstr{\"{o}}m and
Koen De Bosschere},
title = {Introduction to the special issue on high-performance and embedded
architectures and compilers},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {8},
number = {4},
pages = {18:1--18:2},
year = {2012},
url = {https://doi.org/10.1145/2086696.2086697},
doi = {10.1145/2086696.2086697},
timestamp = {Sun, 22 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/taco/StenstromB12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/StockPS12,
author = {Kevin Stock and
Louis{-}No{\"{e}}l Pouchet and
P. Sadayappan},
title = {Using machine learning to improve automatic vectorization},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {8},
number = {4},
pages = {50:1--50:23},
year = {2012},
url = {https://doi.org/10.1145/2086696.2086729},
doi = {10.1145/2086696.2086729},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/StockPS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/TherdsteerasukdiBCCR12,
author = {Kanit Therdsteerasukdi and
Gyungsu Byun and
Jason Cong and
M. Frank Chang and
Glenn Reinman},
title = {Utilizing {RF-I} and intelligent scheduling for better throughput/watt
in a mobile {GPU} memory system},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {8},
number = {4},
pages = {51:1--51:19},
year = {2012},
url = {https://doi.org/10.1145/2086696.2086730},
doi = {10.1145/2086696.2086730},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/TherdsteerasukdiBCCR12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/WangKCS12,
author = {Qingping Wang and
Sameer Kulkarni and
John Cavazos and
Michael F. Spear},
title = {A transactional memory with automatic performance tuning},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {8},
number = {4},
pages = {54:1--54:23},
year = {2012},
url = {https://doi.org/10.1145/2086696.2086733},
doi = {10.1145/2086696.2086733},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/WangKCS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/WangWYLX12,
author = {Zhenjiang Wang and
Chenggang Wu and
Pen{-}Chung Yew and
Jianjun Li and
Di Xu},
title = {On-the-fly structure splitting for heap objects},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {8},
number = {4},
pages = {26:1--26:20},
year = {2012},
url = {https://doi.org/10.1145/2086696.2086705},
doi = {10.1145/2086696.2086705},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/taco/WangWYLX12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/ZhangGCWWCJ12,
author = {Dongsong Zhang and
Deke Guo and
Fang{-}Yuan Chen and
Fei Wu and
Tong Wu and
Ting Cao and
Shiyao Jin},
title = {TL-plane-based multi-core energy-efficient real-time scheduling algorithm
for sporadic tasks},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {8},
number = {4},
pages = {47:1--47:20},
year = {2012},
url = {https://doi.org/10.1145/2086696.2086726},
doi = {10.1145/2086696.2086726},
timestamp = {Fri, 12 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/taco/ZhangGCWWCJ12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/ZhouDCMM12,
author = {Miao Zhou and
Yu Du and
Bruce R. Childers and
Rami G. Melhem and
Daniel Moss{\'{e}}},
title = {Writeback-aware partitioning and replacement for last-level caches
in phase change main memory systems},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {8},
number = {4},
pages = {53:1--53:21},
year = {2012},
url = {https://doi.org/10.1145/2086696.2086732},
doi = {10.1145/2086696.2086732},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/ZhouDCMM12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/Dimitrakopoulos12,
author = {Giorgos Dimitrakopoulos and
Emmanouil Kalligeros},
title = {Low-cost fault-tolerant switch allocator for network-on-chip routers},
booktitle = {Proceedings of the 2012 Interconnection Network Architecture - On-Chip,
Multi-Chip Workshop, INA-OCMC@HiPEAC 2012, Paris, France, January
25, 2012},
pages = {25--28},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2107763.2107770},
doi = {10.1145/2107763.2107770},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/Dimitrakopoulos12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/FabreBZBRAF12,
author = {Christian Fabre and
Iuliana Bacivarov and
Eth Z{\"{u}}rich and
Ananda Basu and
Martino Ruggiero and
David Atienza and
Eric Flamand},
title = {{PRO3D:} programming for future 3D manycore architectures},
booktitle = {Proceedings of the 2012 Interconnection Network Architecture - On-Chip,
Multi-Chip Workshop, INA-OCMC@HiPEAC 2012, Paris, France, January
25, 2012},
pages = {47--50},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2107763.2107776},
doi = {10.1145/2107763.2107776},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/FabreBZBRAF12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/JokanovicMSBRL12,
author = {Ana Jokanovic and
Cyriel Minkenberg and
Jos{\'{e}} Carlos Sancho and
Ram{\'{o}}n Beivide and
Germ{\'{a}}n Rodr{\'{\i}}guez and
Jes{\'{u}}s Labarta},
title = {Contention-aware node allocation policy for high-performance capacity
systems},
booktitle = {Proceedings of the 2012 Interconnection Network Architecture - On-Chip,
Multi-Chip Workshop, INA-OCMC@HiPEAC 2012, Paris, France, January
25, 2012},
pages = {5--8},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2107763.2107765},
doi = {10.1145/2107763.2107765},
timestamp = {Wed, 16 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/JokanovicMSBRL12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/LemonnierM12,
author = {Fabrice Lemonnier and
Philippe Millet},
title = {FlexTiles: self adaptive heterogeneous manycore based on flexible
tiles {(FP7} project)},
booktitle = {Proceedings of the 2012 Interconnection Network Architecture - On-Chip,
Multi-Chip Workshop, INA-OCMC@HiPEAC 2012, Paris, France, January
25, 2012},
pages = {37--38},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2107763.2107773},
doi = {10.1145/2107763.2107773},
timestamp = {Fri, 17 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/LemonnierM12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/LoddeRF12,
author = {Mario Lodde and
Toni Roca and
Jos{\'{e}} Flich},
title = {Heterogeneous network design for effective support of invalidation-based
coherency protocols},
booktitle = {Proceedings of the 2012 Interconnection Network Architecture - On-Chip,
Multi-Chip Workshop, INA-OCMC@HiPEAC 2012, Paris, France, January
25, 2012},
pages = {1--4},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2107763.2107764},
doi = {10.1145/2107763.2107764},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/LoddeRF12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/NakhjavaniSSN12,
author = {Reza Nakhjavani and
Ali Shahabi and
Saeed Safari and
Zainalabedin Navabi},
title = {A novel graceful degradable routing algorithm for 3D on-chip networks},
booktitle = {Proceedings of the 2012 Interconnection Network Architecture - On-Chip,
Multi-Chip Workshop, INA-OCMC@HiPEAC 2012, Paris, France, January
25, 2012},
pages = {17--20},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2107763.2107768},
doi = {10.1145/2107763.2107768},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/NakhjavaniSSN12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/OConnorTS12,
author = {Ian O'Connor and
Dries Van Thourhout and
Alberto Scandurra},
title = {Wavelength division multiplexed photonic layer on {CMOS}},
booktitle = {Proceedings of the 2012 Interconnection Network Architecture - On-Chip,
Multi-Chip Workshop, INA-OCMC@HiPEAC 2012, Paris, France, January
25, 2012},
pages = {33--36},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2107763.2107772},
doi = {10.1145/2107763.2107772},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/OConnorTS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/OxmanWB12,
author = {Gadi Oxman and
Shlomo Weiss and
Yitzhak (Tsahi) Birk},
title = {Buffered deflection routing for networks-on-chip},
booktitle = {Proceedings of the 2012 Interconnection Network Architecture - On-Chip,
Multi-Chip Workshop, INA-OCMC@HiPEAC 2012, Paris, France, January
25, 2012},
pages = {9--12},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2107763.2107766},
doi = {10.1145/2107763.2107766},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/OxmanWB12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/SilvanoFCAPZBCC12,
author = {Cristina Silvano and
William Fornaciari and
Stefano Crespi{-}Reghizzi and
Giovanni Agosta and
Gianluca Palermo and
Vittorio Zaccaria and
Patrick Bellasi and
Fabrizio Castro and
Simone Corbetta and
Ettore Speziale and
Diego Melpignano and
J. M. Zins and
David Siorpaes and
Heiko H{\"{u}}bert and
Benno Stabernack and
Jens Brandenburg and
Martin Palkovic and
Praveen Raghavan and
Chantal Ykman{-}Couvreur and
Alexandros Bartzas and
Dimitrios Soudris and
Torsten Kempf and
Gerd Ascheid and
Heinrich Meyr and
Junaid Ansari and
Petri M{\"{a}}h{\"{o}}nen and
Bart Vanthournout},
title = {Parallel paradigms and run-time management techniques for many-core
architectures: the 2PARMA approach},
booktitle = {Proceedings of the 2012 Interconnection Network Architecture - On-Chip,
Multi-Chip Workshop, INA-OCMC@HiPEAC 2012, Paris, France, January
25, 2012},
pages = {39--42},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2107763.2107774},
doi = {10.1145/2107763.2107774},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/SilvanoFCAPZBCC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/StefanNG12,
author = {Radu Andrei Stefan and
Ashkan Beyranvand Nejad and
Kees Goossens},
title = {Online allocation for contention-free-routing NoCs},
booktitle = {Proceedings of the 2012 Interconnection Network Architecture - On-Chip,
Multi-Chip Workshop, INA-OCMC@HiPEAC 2012, Paris, France, January
25, 2012},
pages = {13--16},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2107763.2107767},
doi = {10.1145/2107763.2107767},
timestamp = {Fri, 17 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/StefanNG12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/StranoBAGSTFSB12,
author = {Alessandro Strano and
Davide Bertozzi and
Federico Angiolini and
Leonardo Di G. Gregorio and
Frank Olaf Sem{-}Jacobsen and
Vladimir Todorov and
Jos{\'{e}} Flich and
Jos{\'{e}} Silla and
Tobias Bjerregaard},
title = {Quest for the ultimate network-on-chip: the NaNoC project},
booktitle = {Proceedings of the 2012 Interconnection Network Architecture - On-Chip,
Multi-Chip Workshop, INA-OCMC@HiPEAC 2012, Paris, France, January
25, 2012},
pages = {43--46},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2107763.2107775},
doi = {10.1145/2107763.2107775},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/StranoBAGSTFSB12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/TerenziSB12,
author = {Simone Terenzi and
Alessandro Strano and
Davide Bertozzi},
title = {Optimizing built-in pseudo-random self-testing for network-on-chip
switches},
booktitle = {Proceedings of the 2012 Interconnection Network Architecture - On-Chip,
Multi-Chip Workshop, INA-OCMC@HiPEAC 2012, Paris, France, January
25, 2012},
pages = {21--24},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2107763.2107769},
doi = {10.1145/2107763.2107769},
timestamp = {Fri, 17 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/TerenziSB12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/VitkovskiySN12,
author = {Arseniy Vitkovskiy and
Vassos Soteriou and
Chrysostomos Nicopoulos},
title = {A highly robust distributed fault-tolerant routing algorithm for NoCs
with localized rerouting},
booktitle = {Proceedings of the 2012 Interconnection Network Architecture - On-Chip,
Multi-Chip Workshop, INA-OCMC@HiPEAC 2012, Paris, France, January
25, 2012},
pages = {29--32},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2107763.2107771},
doi = {10.1145/2107763.2107771},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/VitkovskiySN12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/hipeac/2012ina-ocmc,
title = {Proceedings of the 2012 Interconnection Network Architecture - On-Chip,
Multi-Chip Workshop, INA-OCMC@HiPEAC 2012, Paris, France, January
25, 2012},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2107763},
doi = {10.1145/2107763},
isbn = {978-1-4503-1010-9},
timestamp = {Fri, 17 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/2012ina-ocmc.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/AbellaQCSV11,
author = {Jaume Abella and
Eduardo Qui{\~{n}}ones and
Francisco J. Cazorla and
Yanos Sazeides and
Mateo Valero},
editor = {Manolis Katevenis and
Margaret Martonosi and
Christos Kozyrakis and
Olivier Temam},
title = {{RVC:} a mechanism for time-analyzable real-time processors with faulty
caches},
booktitle = {High Performance Embedded Architectures and Compilers, 6th International
Conference, HiPEAC 2011, Heraklion, Crete, Greece, January 24-26,
2011. Proceedings},
pages = {97--106},
publisher = {{ACM}},
year = {2011},
url = {https://doi.org/10.1145/1944862.1944878},
doi = {10.1145/1944862.1944878},
timestamp = {Tue, 18 May 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/AbellaQCSV11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/AbousamraJM11,
author = {Ahmed Abousamra and
Alex K. Jones and
Rami G. Melhem},
editor = {Manolis Katevenis and
Margaret Martonosi and
Christos Kozyrakis and
Olivier Temam},
title = {NoC-aware cache design for multithreaded execution on tiled chip multiprocessors},
booktitle = {High Performance Embedded Architectures and Compilers, 6th International
Conference, HiPEAC 2011, Heraklion, Crete, Greece, January 24-26,
2011. Proceedings},
pages = {197--205},
publisher = {{ACM}},
year = {2011},
url = {https://doi.org/10.1145/1944862.1944891},
doi = {10.1145/1944862.1944891},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/AbousamraJM11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/Amarasinghe11,
author = {Saman P. Amarasinghe},
editor = {Manolis Katevenis and
Margaret Martonosi and
Christos Kozyrakis and
Olivier Temam},
title = {PetaBricks: a language and compiler based on autotuning},
booktitle = {High Performance Embedded Architectures and Compilers, 6th International
Conference, HiPEAC 2011, Heraklion, Crete, Greece, January 24-26,
2011. Proceedings},
pages = {3},
publisher = {{ACM}},
year = {2011},
url = {https://doi.org/10.1145/1944862.1944865},
doi = {10.1145/1944862.1944865},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/Amarasinghe11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/ArandiE11,
author = {Samer Arandi and
Paraskevas Evripidou},
editor = {Manolis Katevenis and
Margaret Martonosi and
Christos Kozyrakis and
Olivier Temam},
title = {DDM-VM\({}_{\mbox{c}}\): the data-driven multithreading virtual machine
for the cell processor},
booktitle = {High Performance Embedded Architectures and Compilers, 6th International
Conference, HiPEAC 2011, Heraklion, Crete, Greece, January 24-26,
2011. Proceedings},
pages = {25--34},
publisher = {{ACM}},
year = {2011},
url = {https://doi.org/10.1145/1944862.1944869},
doi = {10.1145/1944862.1944869},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/ArandiE11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/BhattacherjeeNG11,
author = {Souvik Bhattacherjee and
Ankur Narang and
Vikas K. Garg},
editor = {Manolis Katevenis and
Margaret Martonosi and
Christos Kozyrakis and
Olivier Temam},
title = {High throughput data redundancy removal algorithm with scalable performance},
booktitle = {High Performance Embedded Architectures and Compilers, 6th International
Conference, HiPEAC 2011, Heraklion, Crete, Greece, January 24-26,
2011. Proceedings},
pages = {87--96},
publisher = {{ACM}},
year = {2011},
url = {https://doi.org/10.1145/1944862.1944877},
doi = {10.1145/1944862.1944877},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/BhattacherjeeNG11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/BoisSPRE11,
author = {Kristof Du Bois and
Tim Schaeps and
Stijn Polfliet and
Frederick Ryckbosch and
Lieven Eeckhout},
editor = {Manolis Katevenis and
Margaret Martonosi and
Christos Kozyrakis and
Olivier Temam},
title = {{SWEEP:} evaluating computer system energy efficiency using synthetic
workloads},
booktitle = {High Performance Embedded Architectures and Compilers, 6th International
Conference, HiPEAC 2011, Heraklion, Crete, Greece, January 24-26,
2011. Proceedings},
pages = {159--166},
publisher = {{ACM}},
year = {2011},
url = {https://doi.org/10.1145/1944862.1944886},
doi = {10.1145/1944862.1944886},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/BoisSPRE11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/CamachoFDEO11,
author = {J. Camacho and
Jos{\'{e}} Flich and
Jos{\'{e}} Duato and
Hans Eberle and
Wladek Olesinski},
editor = {Jos{\'{e}} Flich and
Davide Bertozzi and
Tor Skeie and
Daniele Ludovici},
title = {A power-efficient network on-chip topology},
booktitle = {Proceedings of the Fifth International Workshop on Interconnection
Network Architecture - On-Chip, Multi-Chip, {INA-OCMC} '11, Heraklion,
Greece, January 23, 2011},
pages = {23--26},
publisher = {{ACM}},
year = {2011},
url = {https://doi.org/10.1145/1930037.1930044},
doi = {10.1145/1930037.1930044},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/CamachoFDEO11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/Carloni11,
author = {Luca P. Carloni},
editor = {Jos{\'{e}} Flich and
Davide Bertozzi and
Tor Skeie and
Daniele Ludovici},
title = {Emerging silicon photonics technologies for multi-core platform architectures},
booktitle = {Proceedings of the Fifth International Workshop on Interconnection
Network Architecture - On-Chip, Multi-Chip, {INA-OCMC} '11, Heraklion,
Greece, January 23, 2011},
pages = {1},
publisher = {{ACM}},
year = {2011},
url = {https://doi.org/10.1145/1930037.1930038},
doi = {10.1145/1930037.1930038},
timestamp = {Fri, 17 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/Carloni11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/DaloukasAB11,
author = {Konstantis Daloukas and
Christos D. Antonopoulos and
Nikolaos Bellas},
editor = {Manolis Katevenis and
Margaret Martonosi and
Christos Kozyrakis and
Olivier Temam},
title = {GLOpenCL: OpenCL support on hardware- and software-managed cache multicores},
booktitle = {High Performance Embedded Architectures and Compilers, 6th International
Conference, HiPEAC 2011, Heraklion, Crete, Greece, January 24-26,
2011. Proceedings},
pages = {15--24},
publisher = {{ACM}},
year = {2011},
url = {https://doi.org/10.1145/1944862.1944868},
doi = {10.1145/1944862.1944868},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/DaloukasAB11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/DeVuystTK11,
author = {Matthew DeVuyst and
Dean M. Tullsen and
Seon Wook Kim},
editor = {Manolis Katevenis and
Margaret Martonosi and
Christos Kozyrakis and
Olivier Temam},
title = {Runtime parallelization of legacy code on a transactional memory system},
booktitle = {High Performance Embedded Architectures and Compilers, 6th International
Conference, HiPEAC 2011, Heraklion, Crete, Greece, January 24-26,
2011. Proceedings},
pages = {127--136},
publisher = {{ACM}},
year = {2011},
url = {https://doi.org/10.1145/1944862.1944882},
doi = {10.1145/1944862.1944882},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/DeVuystTK11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/Dimitrakopoulos11,
author = {Giorgos Dimitrakopoulos and
Kostas Galanopoulos},
editor = {Jos{\'{e}} Flich and
Davide Bertozzi and
Tor Skeie and
Daniele Ludovici},
title = {Switch allocator for bufferless network-on-chip routers},
booktitle = {Proceedings of the Fifth International Workshop on Interconnection
Network Architecture - On-Chip, Multi-Chip, {INA-OCMC} '11, Heraklion,
Greece, January 23, 2011},
pages = {19--22},
publisher = {{ACM}},
year = {2011},
url = {https://doi.org/10.1145/1930037.1930043},
doi = {10.1145/1930037.1930043},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/Dimitrakopoulos11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/DusserS11,
author = {Julien Dusser and
Andr{\'{e}} Seznec},
editor = {Manolis Katevenis and
Margaret Martonosi and
Christos Kozyrakis and
Olivier Temam},
title = {Decoupled zero-compressed memory},
booktitle = {High Performance Embedded Architectures and Compilers, 6th International
Conference, HiPEAC 2011, Heraklion, Crete, Greece, January 24-26,
2011. Proceedings},
pages = {77--86},
publisher = {{ACM}},
year = {2011},
url = {https://doi.org/10.1145/1944862.1944876},
doi = {10.1145/1944862.1944876},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/DusserS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/EdvinssonLL11,
author = {Marcus Edvinsson and
Jonas Lundberg and
Welf L{\"{o}}we},
editor = {Manolis Katevenis and
Margaret Martonosi and
Christos Kozyrakis and
Olivier Temam},
title = {Parallel points-to analysis for multi-core machines},
booktitle = {High Performance Embedded Architectures and Compilers, 6th International
Conference, HiPEAC 2011, Heraklion, Crete, Greece, January 24-26,
2011. Proceedings},
pages = {45--54},
publisher = {{ACM}},
year = {2011},
url = {https://doi.org/10.1145/1944862.1944872},
doi = {10.1145/1944862.1944872},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/EdvinssonLL11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/EklovBH11,
author = {David Eklov and
David Black{-}Schaffer and
Erik Hagersten},
editor = {Manolis Katevenis and
Margaret Martonosi and
Christos Kozyrakis and
Olivier Temam},
title = {Fast modeling of shared caches in multicore systems},
booktitle = {High Performance Embedded Architectures and Compilers, 6th International
Conference, HiPEAC 2011, Heraklion, Crete, Greece, January 24-26,
2011. Proceedings},
pages = {147--157},
publisher = {{ACM}},
year = {2011},
url = {https://doi.org/10.1145/1944862.1944885},
doi = {10.1145/1944862.1944885},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/EklovBH11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/Gonzalez11,
author = {Antonio Gonz{\'{a}}lez},
editor = {Manolis Katevenis and
Margaret Martonosi and
Christos Kozyrakis and
Olivier Temam},
title = {Moore's law implications on energy reduction},
booktitle = {High Performance Embedded Architectures and Compilers, 6th International
Conference, HiPEAC 2011, Heraklion, Crete, Greece, January 24-26,
2011. Proceedings},
pages = {1--2},
publisher = {{ACM}},
year = {2011},
url = {https://doi.org/10.1145/1944862.1944864},
doi = {10.1145/1944862.1944864},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/Gonzalez11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/GreweWO11,
author = {Dominik Grewe and
Zheng Wang and
Michael F. P. O'Boyle},
editor = {Manolis Katevenis and
Margaret Martonosi and
Christos Kozyrakis and
Olivier Temam},
title = {A workload-aware mapping approach for data-parallel programs},
booktitle = {High Performance Embedded Architectures and Compilers, 6th International
Conference, HiPEAC 2011, Heraklion, Crete, Greece, January 24-26,
2011. Proceedings},
pages = {117--126},
publisher = {{ACM}},
year = {2011},
url = {https://doi.org/10.1145/1944862.1944881},
doi = {10.1145/1944862.1944881},
timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/GreweWO11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/HammoudCM11,
author = {Mohammad Hammoud and
Sangyeun Cho and
Rami G. Melhem},
editor = {Manolis Katevenis and
Margaret Martonosi and
Christos Kozyrakis and
Olivier Temam},
title = {Cache equalizer: a placement mechanism for chip multiprocessor distributed
shared caches},
booktitle = {High Performance Embedded Architectures and Compilers, 6th International
Conference, HiPEAC 2011, Heraklion, Crete, Greece, January 24-26,
2011. Proceedings},
pages = {177--186},
publisher = {{ACM}},
year = {2011},
url = {https://doi.org/10.1145/1944862.1944889},
doi = {10.1145/1944862.1944889},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/HammoudCM11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/HassanPLC11,
author = {Khaldon Hassan and
Fr{\'{e}}d{\'{e}}ric P{\'{e}}trot and
Riccardo Locatelli and
Marcello Coppola},
editor = {Jos{\'{e}} Flich and
Davide Bertozzi and
Tor Skeie and
Daniele Ludovici},
title = {{EEEP:} an \emph{extreme end} to \emph{end} flow control \emph{protocol}
for {SDRAM} access through networks on chip},
booktitle = {Proceedings of the Fifth International Workshop on Interconnection
Network Architecture - On-Chip, Multi-Chip, {INA-OCMC} '11, Heraklion,
Greece, January 23, 2011},
pages = {3--6},
publisher = {{ACM}},
year = {2011},
url = {https://doi.org/10.1145/1930037.1930039},
doi = {10.1145/1930037.1930039},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/HassanPLC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/KichererBK11,
author = {Mario Kicherer and
Rainer Buchty and
Wolfgang Karl},
editor = {Manolis Katevenis and
Margaret Martonosi and
Christos Kozyrakis and
Olivier Temam},
title = {Cost-aware function migration in heterogeneous systems},
booktitle = {High Performance Embedded Architectures and Compilers, 6th International
Conference, HiPEAC 2011, Heraklion, Crete, Greece, January 24-26,
2011. Proceedings},
pages = {137--145},
publisher = {{ACM}},
year = {2011},
url = {https://doi.org/10.1145/1944862.1944883},
doi = {10.1145/1944862.1944883},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/KichererBK11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/LiCL11,
author = {Shisheng Li and
Buqi Cheng and
Xiao{-}Feng Li},
editor = {Manolis Katevenis and
Margaret Martonosi and
Christos Kozyrakis and
Olivier Temam},
title = {TypeCastor: demystify dynamic typing of JavaScript applications},
booktitle = {High Performance Embedded Architectures and Compilers, 6th International
Conference, HiPEAC 2011, Heraklion, Crete, Greece, January 24-26,
2011. Proceedings},
pages = {55--65},
publisher = {{ACM}},
year = {2011},
url = {https://doi.org/10.1145/1944862.1944873},
doi = {10.1145/1944862.1944873},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/LiCL11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/LudoviciSGB11,
author = {Daniele Ludovici and
Alessandro Strano and
Georgi Nedeltchev Gaydadjiev and
Davide Bertozzi},
editor = {Jos{\'{e}} Flich and
Davide Bertozzi and
Tor Skeie and
Daniele Ludovici},
title = {Mesochronous NoC technology for power-efficient {GALS} MPSoCs},
booktitle = {Proceedings of the Fifth International Workshop on Interconnection
Network Architecture - On-Chip, Multi-Chip, {INA-OCMC} '11, Heraklion,
Greece, January 23, 2011},
pages = {27--30},
publisher = {{ACM}},
year = {2011},
url = {https://doi.org/10.1145/1930037.1930045},
doi = {10.1145/1930037.1930045},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/LudoviciSGB11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/ManikantanGR11,
author = {R. Manikantan and
R. Govindarajan and
Kaushik Rajan},
editor = {Manolis Katevenis and
Margaret Martonosi and
Christos Kozyrakis and
Olivier Temam},
title = {Extended histories: improving regularity and performance in correlation
prefetchers},
booktitle = {High Performance Embedded Architectures and Compilers, 6th International
Conference, HiPEAC 2011, Heraklion, Crete, Greece, January 24-26,
2011. Proceedings},
pages = {67--76},
publisher = {{ACM}},
year = {2011},
url = {https://doi.org/10.1145/1944862.1944875},
doi = {10.1145/1944862.1944875},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/ManikantanGR11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/MarsTS11,
author = {Jason Mars and
Lingjia Tang and
Mary Lou Soffa},
editor = {Manolis Katevenis and
Margaret Martonosi and
Christos Kozyrakis and
Olivier Temam},
title = {Directly characterizing cross core interference through contention
synthesis},
booktitle = {High Performance Embedded Architectures and Compilers, 6th International
Conference, HiPEAC 2011, Heraklion, Crete, Greece, January 24-26,
2011. Proceedings},
pages = {167--176},
publisher = {{ACM}},
year = {2011},
url = {https://doi.org/10.1145/1944862.1944887},
doi = {10.1145/1944862.1944887},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/MarsTS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/Michaud11,
author = {Pierre Michaud},
editor = {Manolis Katevenis and
Margaret Martonosi and
Christos Kozyrakis and
Olivier Temam},
title = {Replacement policies for shared caches on symmetric multicores: a
programmer-centric point of view},
booktitle = {High Performance Embedded Architectures and Compilers, 6th International
Conference, HiPEAC 2011, Heraklion, Crete, Greece, January 24-26,
2011. Proceedings},
pages = {187--196},
publisher = {{ACM}},
year = {2011},
url = {https://doi.org/10.1145/1944862.1944890},
doi = {10.1145/1944862.1944890},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/Michaud11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/PariniRBB11,
author = {Alberto Parini and
Luca Ramini and
Gaetano Bellanca and
Davide Bertozzi},
editor = {Jos{\'{e}} Flich and
Davide Bertozzi and
Tor Skeie and
Daniele Ludovici},
title = {Abstract modelling of switching elements for optical networks-on-chip
with technology platform awareness},
booktitle = {Proceedings of the Fifth International Workshop on Interconnection
Network Architecture - On-Chip, Multi-Chip, {INA-OCMC} '11, Heraklion,
Greece, January 23, 2011},
pages = {31--34},
publisher = {{ACM}},
year = {2011},
url = {https://doi.org/10.1145/1930037.1930046},
doi = {10.1145/1930037.1930046},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/PariniRBB11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/PopC11,
author = {Antoniu Pop and
Albert Cohen},
editor = {Manolis Katevenis and
Margaret Martonosi and
Christos Kozyrakis and
Olivier Temam},
title = {A stream-computing extension to OpenMP},
booktitle = {High Performance Embedded Architectures and Compilers, 6th International
Conference, HiPEAC 2011, Heraklion, Crete, Greece, January 24-26,
2011. Proceedings},
pages = {5--14},
publisher = {{ACM}},
year = {2011},
url = {https://doi.org/10.1145/1944862.1944867},
doi = {10.1145/1944862.1944867},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/PopC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/RahmanGY11,
author = {Faizur Rahman and
Jichi Guo and
Qing Yi},
editor = {Manolis Katevenis and
Margaret Martonosi and
Christos Kozyrakis and
Olivier Temam},
title = {Automated empirical tuning of scientific codes for performance and
power consumption},
booktitle = {High Performance Embedded Architectures and Compilers, 6th International
Conference, HiPEAC 2011, Heraklion, Crete, Greece, January 24-26,
2011. Proceedings},
pages = {107--116},
publisher = {{ACM}},
year = {2011},
url = {https://doi.org/10.1145/1944862.1944880},
doi = {10.1145/1944862.1944880},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/RahmanGY11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/RohouDNRWCZ11,
author = {Erven Rohou and
Sergei Dyshel and
Dorit Nuzman and
Ira Rosen and
Kevin Williams and
Albert Cohen and
Ayal Zaks},
editor = {Manolis Katevenis and
Margaret Martonosi and
Christos Kozyrakis and
Olivier Temam},
title = {Speculatively vectorized bytecode},
booktitle = {High Performance Embedded Architectures and Compilers, 6th International
Conference, HiPEAC 2011, Heraklion, Crete, Greece, January 24-26,
2011. Proceedings},
pages = {35--44},
publisher = {{ACM}},
year = {2011},
url = {https://doi.org/10.1145/1944862.1944871},
doi = {10.1145/1944862.1944871},
timestamp = {Tue, 09 Jul 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/RohouDNRWCZ11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/Sem-JacobsenRS11,
author = {Frank Olaf Sem{-}Jacobsen and
Samuel Rodrigo and
Tor Skeie},
editor = {Jos{\'{e}} Flich and
Davide Bertozzi and
Tor Skeie and
Daniele Ludovici},
title = {iFDOR: dynamic rerouting on-chip},
booktitle = {Proceedings of the Fifth International Workshop on Interconnection
Network Architecture - On-Chip, Multi-Chip, {INA-OCMC} '11, Heraklion,
Greece, January 23, 2011},
pages = {11--14},
publisher = {{ACM}},
year = {2011},
url = {https://doi.org/10.1145/1930037.1930041},
doi = {10.1145/1930037.1930041},
timestamp = {Fri, 17 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/Sem-JacobsenRS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/StefanG11,
author = {Radu Andrei Stefan and
Kees Goossens},
editor = {Jos{\'{e}} Flich and
Davide Bertozzi and
Tor Skeie and
Daniele Ludovici},
title = {An improved algorithm for slot selection in the {\AE}thereal network-on-chip},
booktitle = {Proceedings of the Fifth International Workshop on Interconnection
Network Architecture - On-Chip, Multi-Chip, {INA-OCMC} '11, Heraklion,
Greece, January 23, 2011},
pages = {7--10},
publisher = {{ACM}},
year = {2011},
url = {https://doi.org/10.1145/1930037.1930040},
doi = {10.1145/1930037.1930040},
timestamp = {Fri, 17 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/StefanG11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/XuLT11,
author = {Thomas Canhao Xu and
Pasi Liljeberg and
Hannu Tenhunen},
editor = {Jos{\'{e}} Flich and
Davide Bertozzi and
Tor Skeie and
Daniele Ludovici},
title = {Process scheduling for future multicore processors},
booktitle = {Proceedings of the Fifth International Workshop on Interconnection
Network Architecture - On-Chip, Multi-Chip, {INA-OCMC} '11, Heraklion,
Greece, January 23, 2011},
pages = {15--18},
publisher = {{ACM}},
year = {2011},
url = {https://doi.org/10.1145/1930037.1930042},
doi = {10.1145/1930037.1930042},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/XuLT11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/hipeac/2011,
editor = {Manolis Katevenis and
Margaret Martonosi and
Christos Kozyrakis and
Olivier Temam},
title = {High Performance Embedded Architectures and Compilers, 6th International
Conference, HiPEAC 2011, Heraklion, Crete, Greece, January 24-26,
2011. Proceedings},
publisher = {{ACM}},
year = {2011},
isbn = {978-1-4503-0241-8},
timestamp = {Tue, 09 Aug 2011 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/2011.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/hipeac/2011ina-ocmc,
editor = {Jos{\'{e}} Flich and
Davide Bertozzi and
Tor Skeie and
Daniele Ludovici},
title = {Proceedings of the Fifth International Workshop on Interconnection
Network Architecture - On-Chip, Multi-Chip, {INA-OCMC} '11, Heraklion,
Greece, January 23, 2011},
publisher = {{ACM}},
year = {2011},
url = {https://doi.org/10.1145/1930037},
doi = {10.1145/1930037},
isbn = {978-1-4503-0272-2},
timestamp = {Fri, 17 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/2011ina-ocmc.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/AnsariKLKKW10,
author = {Mohammad Ansari and
Behram Khan and
Mikel Luj{\'{a}}n and
Christos Kotselidis and
Chris C. Kirkham and
Ian Watson},
editor = {Yale N. Patt and
Pierfrancesco Foglia and
Evelyn Duesterwald and
Paolo Faraboschi and
Xavier Martorell},
title = {Improving Performance by Reducing Aborts in Hardware Transactional
Memory},
booktitle = {High Performance Embedded Architectures and Compilers, 5th International
Conference, HiPEAC 2010, Pisa, Italy, January 25-27, 2010. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {5952},
pages = {35--49},
publisher = {Springer},
year = {2010},
url = {https://doi.org/10.1007/978-3-642-11515-8\_5},
doi = {10.1007/978-3-642-11515-8\_5},
timestamp = {Tue, 14 May 2019 10:00:51 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/AnsariKLKKW10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/Ben-ItzhakCK10,
author = {Yaniv Ben{-}Itzhak and
Israel Cidon and
Avinoam Kolodny},
editor = {Yale N. Patt and
Pierfrancesco Foglia and
Evelyn Duesterwald and
Paolo Faraboschi and
Xavier Martorell},
title = {Performance and Power Aware {CMP} Thread Allocation Modeling},
booktitle = {High Performance Embedded Architectures and Compilers, 5th International
Conference, HiPEAC 2010, Pisa, Italy, January 25-27, 2010. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {5952},
pages = {232--246},
publisher = {Springer},
year = {2010},
url = {https://doi.org/10.1007/978-3-642-11515-8\_18},
doi = {10.1007/978-3-642-11515-8\_18},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/Ben-ItzhakCK10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/CarpenterRA10,
author = {Paul M. Carpenter and
Alex Ram{\'{\i}}rez and
Eduard Ayguad{\'{e}}},
editor = {Yale N. Patt and
Pierfrancesco Foglia and
Evelyn Duesterwald and
Paolo Faraboschi and
Xavier Martorell},
title = {Buffer Sizing for Self-timed Stream Programs on Heterogeneous Distributed
Memory Multiprocessors},
booktitle = {High Performance Embedded Architectures and Compilers, 5th International
Conference, HiPEAC 2010, Pisa, Italy, January 25-27, 2010. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {5952},
pages = {96--110},
publisher = {Springer},
year = {2010},
url = {https://doi.org/10.1007/978-3-642-11515-8\_9},
doi = {10.1007/978-3-642-11515-8\_9},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/CarpenterRA10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/CooperDDRRR10,
author = {Pete Cooper and
Uwe Dolinsky and
Alastair F. Donaldson and
Andrew Richards and
Colin Riley and
George Russell},
editor = {Yale N. Patt and
Pierfrancesco Foglia and
Evelyn Duesterwald and
Paolo Faraboschi and
Xavier Martorell},
title = {Offload - Automating Code Migration to Heterogeneous Multicore Systems},
booktitle = {High Performance Embedded Architectures and Compilers, 5th International
Conference, HiPEAC 2010, Pisa, Italy, January 25-27, 2010. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {5952},
pages = {337--352},
publisher = {Springer},
year = {2010},
url = {https://doi.org/10.1007/978-3-642-11515-8\_25},
doi = {10.1007/978-3-642-11515-8\_25},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/CooperDDRRR10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/DioufCRC10,
author = {Boubacar Diouf and
Albert Cohen and
Fabrice Rastello and
John Cavazos},
editor = {Yale N. Patt and
Pierfrancesco Foglia and
Evelyn Duesterwald and
Paolo Faraboschi and
Xavier Martorell},
title = {Split Register Allocation: Linear Complexity Without the Performance
Penalty},
booktitle = {High Performance Embedded Architectures and Compilers, 5th International
Conference, HiPEAC 2010, Pisa, Italy, January 25-27, 2010. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {5952},
pages = {66--80},
publisher = {Springer},
year = {2010},
url = {https://doi.org/10.1007/978-3-642-11515-8\_7},
doi = {10.1007/978-3-642-11515-8\_7},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/DioufCRC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/Espasa10,
author = {Roger Espasa},
editor = {Yale N. Patt and
Pierfrancesco Foglia and
Evelyn Duesterwald and
Paolo Faraboschi and
Xavier Martorell},
title = {Larrabee: {A} Many-Core Intel Architecture for Visual Computing},
booktitle = {High Performance Embedded Architectures and Compilers, 5th International
Conference, HiPEAC 2010, Pisa, Italy, January 25-27, 2010. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {5952},
pages = {2},
publisher = {Springer},
year = {2010},
url = {https://doi.org/10.1007/978-3-642-11515-8\_2},
doi = {10.1007/978-3-642-11515-8\_2},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/Espasa10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/FengGAM10,
author = {Shuguang Feng and
Shantanu Gupta and
Amin Ansari and
Scott A. Mahlke},
editor = {Yale N. Patt and
Pierfrancesco Foglia and
Evelyn Duesterwald and
Paolo Faraboschi and
Xavier Martorell},
title = {Maestro: Orchestrating Lifetime Reliability in Chip Multiprocessors},
booktitle = {High Performance Embedded Architectures and Compilers, 5th International
Conference, HiPEAC 2010, Pisa, Italy, January 25-27, 2010. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {5952},
pages = {186--200},
publisher = {Springer},
year = {2010},
url = {https://doi.org/10.1007/978-3-642-11515-8\_15},
doi = {10.1007/978-3-642-11515-8\_15},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/FengGAM10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/FerrerBGMA10,
author = {Roger Ferrer and
Vicen{\c{c}} Beltran and
Marc Gonz{\'{a}}lez and
Xavier Martorell and
Eduard Ayguad{\'{e}}},
editor = {Yale N. Patt and
Pierfrancesco Foglia and
Evelyn Duesterwald and
Paolo Faraboschi and
Xavier Martorell},
title = {Analysis of Task Offloading for Accelerators},
booktitle = {High Performance Embedded Architectures and Compilers, 5th International
Conference, HiPEAC 2010, Pisa, Italy, January 25-27, 2010. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {5952},
pages = {322--336},
publisher = {Springer},
year = {2010},
url = {https://doi.org/10.1007/978-3-642-11515-8\_24},
doi = {10.1007/978-3-642-11515-8\_24},
timestamp = {Wed, 08 Feb 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/FerrerBGMA10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/FerriWMBH10,
author = {Cesare Ferri and
Samantha Wood and
Tali Moreshet and
R. Iris Bahar and
Maurice Herlihy},
editor = {Yale N. Patt and
Pierfrancesco Foglia and
Evelyn Duesterwald and
Paolo Faraboschi and
Xavier Martorell},
title = {Energy and Throughput Efficient Transactional Memory for Embedded
Multicore Systems},
booktitle = {High Performance Embedded Architectures and Compilers, 5th International
Conference, HiPEAC 2010, Pisa, Italy, January 25-27, 2010. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {5952},
pages = {50--65},
publisher = {Springer},
year = {2010},
url = {https://doi.org/10.1007/978-3-642-11515-8\_6},
doi = {10.1007/978-3-642-11515-8\_6},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/FerriWMBH10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/GolovanevskyDZE10,
author = {Olga Golovanevsky and
Alon Dayan and
Ayal Zaks and
David Edelsohn},
editor = {Yale N. Patt and
Pierfrancesco Foglia and
Evelyn Duesterwald and
Paolo Faraboschi and
Xavier Martorell},
title = {Trace-Based Data Layout Optimizations for Multi-core Processors},
booktitle = {High Performance Embedded Architectures and Compilers, 5th International
Conference, HiPEAC 2010, Pisa, Italy, January 25-27, 2010. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {5952},
pages = {81--95},
publisher = {Springer},
year = {2010},
url = {https://doi.org/10.1007/978-3-642-11515-8\_8},
doi = {10.1007/978-3-642-11515-8\_8},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/GolovanevskyDZE10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/GrannaesJN10,
author = {Marius Grann{\ae}s and
Magnus Jahre and
Lasse Natvig},
editor = {Yale N. Patt and
Pierfrancesco Foglia and
Evelyn Duesterwald and
Paolo Faraboschi and
Xavier Martorell},
title = {Multi-level Hardware Prefetching Using Low Complexity Delta Correlating
Prediction Tables with Partial Matching},
booktitle = {High Performance Embedded Architectures and Compilers, 5th International
Conference, HiPEAC 2010, Pisa, Italy, January 25-27, 2010. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {5952},
pages = {247--261},
publisher = {Springer},
year = {2010},
url = {https://doi.org/10.1007/978-3-642-11515-8\_19},
doi = {10.1007/978-3-642-11515-8\_19},
timestamp = {Sat, 16 Sep 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/GrannaesJN10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/HoffmannWA10,
author = {Henry Hoffmann and
David Wentzlaff and
Anant Agarwal},
editor = {Yale N. Patt and
Pierfrancesco Foglia and
Evelyn Duesterwald and
Paolo Faraboschi and
Xavier Martorell},
title = {Remote Store Programming},
booktitle = {High Performance Embedded Architectures and Compilers, 5th International
Conference, HiPEAC 2010, Pisa, Italy, January 25-27, 2010. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {5952},
pages = {3--17},
publisher = {Springer},
year = {2010},
url = {https://doi.org/10.1007/978-3-642-11515-8\_3},
doi = {10.1007/978-3-642-11515-8\_3},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/HoffmannWA10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/HomayounGVSKD10,
author = {Houman Homayoun and
Aseem Gupta and
Alexander V. Veidenbaum and
Avesta Sasan and
Fadi J. Kurdahi and
Nikil D. Dutt},
editor = {Yale N. Patt and
Pierfrancesco Foglia and
Evelyn Duesterwald and
Paolo Faraboschi and
Xavier Martorell},
title = {{RELOCATE:} Register File Local Access Pattern Redistribution Mechanism
for Power and Thermal Management in Out-of-Order Embedded Processor},
booktitle = {High Performance Embedded Architectures and Compilers, 5th International
Conference, HiPEAC 2010, Pisa, Italy, January 25-27, 2010. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {5952},
pages = {216--231},
publisher = {Springer},
year = {2010},
url = {https://doi.org/10.1007/978-3-642-11515-8\_17},
doi = {10.1007/978-3-642-11515-8\_17},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/HomayounGVSKD10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/Iannucci10,
author = {Bob Iannucci},
editor = {Yale N. Patt and
Pierfrancesco Foglia and
Evelyn Duesterwald and
Paolo Faraboschi and
Xavier Martorell},
title = {Embedded Systems as Datacenters},
booktitle = {High Performance Embedded Architectures and Compilers, 5th International
Conference, HiPEAC 2010, Pisa, Italy, January 25-27, 2010. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {5952},
pages = {1},
publisher = {Springer},
year = {2010},
url = {https://doi.org/10.1007/978-3-642-11515-8\_1},
doi = {10.1007/978-3-642-11515-8\_1},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/Iannucci10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/JahreGN10,
author = {Magnus Jahre and
Marius Grann{\ae}s and
Lasse Natvig},
editor = {Yale N. Patt and
Pierfrancesco Foglia and
Evelyn Duesterwald and
Paolo Faraboschi and
Xavier Martorell},
title = {{DIEF:} An Accurate Interference Feedback Mechanism for Chip Multiprocessor
Memory Systems},
booktitle = {High Performance Embedded Architectures and Compilers, 5th International
Conference, HiPEAC 2010, Pisa, Italy, January 25-27, 2010. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {5952},
pages = {292--306},
publisher = {Springer},
year = {2010},
url = {https://doi.org/10.1007/978-3-642-11515-8\_22},
doi = {10.1007/978-3-642-11515-8\_22},
timestamp = {Sat, 16 Sep 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/JahreGN10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/JiangTS10,
author = {Yunlian Jiang and
Kai Tian and
Xipeng Shen},
editor = {Yale N. Patt and
Pierfrancesco Foglia and
Evelyn Duesterwald and
Paolo Faraboschi and
Xavier Martorell},
title = {Combining Locality Analysis with Online Proactive Job Co-scheduling
in Chip Multiprocessors},
booktitle = {High Performance Embedded Architectures and Compilers, 5th International
Conference, HiPEAC 2010, Pisa, Italy, January 25-27, 2010. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {5952},
pages = {201--215},
publisher = {Springer},
year = {2010},
url = {https://doi.org/10.1007/978-3-642-11515-8\_16},
doi = {10.1007/978-3-642-11515-8\_16},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/JiangTS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/KimLSYP10,
author = {Yongjoo Kim and
Jongeun Lee and
Aviral Shrivastava and
Jonghee W. Yoon and
Yunheung Paek},
editor = {Yale N. Patt and
Pierfrancesco Foglia and
Evelyn Duesterwald and
Paolo Faraboschi and
Xavier Martorell},
title = {Memory-Aware Application Mapping on Coarse-Grained Reconfigurable
Arrays},
booktitle = {High Performance Embedded Architectures and Compilers, 5th International
Conference, HiPEAC 2010, Pisa, Italy, January 25-27, 2010. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {5952},
pages = {171--185},
publisher = {Springer},
year = {2010},
url = {https://doi.org/10.1007/978-3-642-11515-8\_14},
doi = {10.1007/978-3-642-11515-8\_14},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/KimLSYP10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/KluterBBCI10,
author = {Theo Kluter and
Samuel Burri and
Philip Brisk and
Edoardo Charbon and
Paolo Ienne},
editor = {Yale N. Patt and
Pierfrancesco Foglia and
Evelyn Duesterwald and
Paolo Faraboschi and
Xavier Martorell},
title = {Virtual Ways: Efficient Coherence for Architecturally Visible Storage
in Automatic Instruction Set Extensions},
booktitle = {High Performance Embedded Architectures and Compilers, 5th International
Conference, HiPEAC 2010, Pisa, Italy, January 25-27, 2010. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {5952},
pages = {126--140},
publisher = {Springer},
year = {2010},
url = {https://doi.org/10.1007/978-3-642-11515-8\_11},
doi = {10.1007/978-3-642-11515-8\_11},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/KluterBBCI10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/MesmayCFP10,
author = {Fr{\'{e}}d{\'{e}}ric de Mesmay and
Srinivas Chellappa and
Franz Franchetti and
Markus P{\"{u}}schel},
editor = {Yale N. Patt and
Pierfrancesco Foglia and
Evelyn Duesterwald and
Paolo Faraboschi and
Xavier Martorell},
title = {Computer Generation of Efficient Software Viterbi Decoders},
booktitle = {High Performance Embedded Architectures and Compilers, 5th International
Conference, HiPEAC 2010, Pisa, Italy, January 25-27, 2010. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {5952},
pages = {353--368},
publisher = {Springer},
year = {2010},
url = {https://doi.org/10.1007/978-3-642-11515-8\_26},
doi = {10.1007/978-3-642-11515-8\_26},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/MesmayCFP10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/MonakovLA10,
author = {Alexander Monakov and
Anton Lokhmotov and
Arutyun Avetisyan},
editor = {Yale N. Patt and
Pierfrancesco Foglia and
Evelyn Duesterwald and
Paolo Faraboschi and
Xavier Martorell},
title = {Automatically Tuning Sparse Matrix-Vector Multiplication for {GPU}
Architectures},
booktitle = {High Performance Embedded Architectures and Compilers, 5th International
Conference, HiPEAC 2010, Pisa, Italy, January 25-27, 2010. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {5952},
pages = {111--125},
publisher = {Springer},
year = {2010},
url = {https://doi.org/10.1007/978-3-642-11515-8\_10},
doi = {10.1007/978-3-642-11515-8\_10},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/MonakovLA10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/MoussalliSNT10,
author = {Roger Moussalli and
Mariam Salloum and
Walid A. Najjar and
Vassilis J. Tsotras},
editor = {Yale N. Patt and
Pierfrancesco Foglia and
Evelyn Duesterwald and
Paolo Faraboschi and
Xavier Martorell},
title = {Accelerating {XML} Query Matching through Custom Stack Generation
on FPGAs},
booktitle = {High Performance Embedded Architectures and Compilers, 5th International
Conference, HiPEAC 2010, Pisa, Italy, January 25-27, 2010. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {5952},
pages = {141--155},
publisher = {Springer},
year = {2010},
url = {https://doi.org/10.1007/978-3-642-11515-8\_12},
doi = {10.1007/978-3-642-11515-8\_12},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/MoussalliSNT10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/OhlendorfMWH10,
author = {Rainer Ohlendorf and
Michael Meitinger and
Thomas Wild and
Andreas Herkersdorf},
editor = {Yale N. Patt and
Pierfrancesco Foglia and
Evelyn Duesterwald and
Paolo Faraboschi and
Xavier Martorell},
title = {An Application-Aware Load Balancing Strategy for Network Processors},
booktitle = {High Performance Embedded Architectures and Compilers, 5th International
Conference, HiPEAC 2010, Pisa, Italy, January 25-27, 2010. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {5952},
pages = {156--170},
publisher = {Springer},
year = {2010},
url = {https://doi.org/10.1007/978-3-642-11515-8\_13},
doi = {10.1007/978-3-642-11515-8\_13},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/OhlendorfMWH10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/SartoriK10,
author = {John Sartori and
Rakesh Kumar},
editor = {Yale N. Patt and
Pierfrancesco Foglia and
Evelyn Duesterwald and
Paolo Faraboschi and
Xavier Martorell},
title = {Low-Overhead, High-Speed Multi-core Barrier Synchronization},
booktitle = {High Performance Embedded Architectures and Compilers, 5th International
Conference, HiPEAC 2010, Pisa, Italy, January 25-27, 2010. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {5952},
pages = {18--34},
publisher = {Springer},
year = {2010},
url = {https://doi.org/10.1007/978-3-642-11515-8\_4},
doi = {10.1007/978-3-642-11515-8\_4},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/SartoriK10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/SrikantaiahK10,
author = {Shekhar Srikantaiah and
Mahmut T. Kandemir},
editor = {Yale N. Patt and
Pierfrancesco Foglia and
Evelyn Duesterwald and
Paolo Faraboschi and
Xavier Martorell},
title = {{SRP:} Symbiotic Resource Partitioning of the Memory Hierarchy in
CMPs},
booktitle = {High Performance Embedded Architectures and Compilers, 5th International
Conference, HiPEAC 2010, Pisa, Italy, January 25-27, 2010. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {5952},
pages = {277--291},
publisher = {Springer},
year = {2010},
url = {https://doi.org/10.1007/978-3-642-11515-8\_21},
doi = {10.1007/978-3-642-11515-8\_21},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/SrikantaiahK10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/TzenakisKAKNB10,
author = {George Tzenakis and
Konstantinos Kapelonis and
Michail Alvanos and
Konstantinos Koukos and
Dimitrios S. Nikolopoulos and
Angelos Bilas},
editor = {Yale N. Patt and
Pierfrancesco Foglia and
Evelyn Duesterwald and
Paolo Faraboschi and
Xavier Martorell},
title = {\emph{Tagged Procedure Calls} (\emph{TPC}): Efficient Runtime Support
for Task-Based Parallelism on the Cell Processor},
booktitle = {High Performance Embedded Architectures and Compilers, 5th International
Conference, HiPEAC 2010, Pisa, Italy, January 25-27, 2010. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {5952},
pages = {307--321},
publisher = {Springer},
year = {2010},
url = {https://doi.org/10.1007/978-3-642-11515-8\_23},
doi = {10.1007/978-3-642-11515-8\_23},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/TzenakisKAKNB10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/XieL10,
author = {Yuejian Xie and
Gabriel H. Loh},
editor = {Yale N. Patt and
Pierfrancesco Foglia and
Evelyn Duesterwald and
Paolo Faraboschi and
Xavier Martorell},
title = {Scalable Shared-Cache Management by Containing Thrashing Workloads},
booktitle = {High Performance Embedded Architectures and Compilers, 5th International
Conference, HiPEAC 2010, Pisa, Italy, January 25-27, 2010. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {5952},
pages = {262--276},
publisher = {Springer},
year = {2010},
url = {https://doi.org/10.1007/978-3-642-11515-8\_20},
doi = {10.1007/978-3-642-11515-8\_20},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/XieL10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/hipeac/2010,
editor = {Yale N. Patt and
Pierfrancesco Foglia and
Evelyn Duesterwald and
Paolo Faraboschi and
Xavier Martorell},
title = {High Performance Embedded Architectures and Compilers, 5th International
Conference, HiPEAC 2010, Pisa, Italy, January 25-27, 2010. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {5952},
publisher = {Springer},
year = {2010},
url = {https://doi.org/10.1007/978-3-642-11515-8},
doi = {10.1007/978-3-642-11515-8},
isbn = {978-3-642-11514-1},
timestamp = {Tue, 14 May 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/2010.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/Agerwala09,
author = {Tilak Agerwala},
editor = {Andr{\'{e}} Seznec and
Joel S. Emer and
Michael F. P. O'Boyle and
Margaret Martonosi and
Theo Ungerer},
title = {Keynote: Challenges on the Road to Exascale Computing},
booktitle = {High Performance Embedded Architectures and Compilers, Fourth International
Conference, HiPEAC 2009, Paphos, Cyprus, January 25-28, 2009. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {5409},
pages = {1},
publisher = {Springer},
year = {2009},
url = {https://doi.org/10.1007/978-3-540-92990-1\_1},
doi = {10.1007/978-3-540-92990-1\_1},
timestamp = {Tue, 14 May 2019 10:00:51 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/Agerwala09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/Al-KadiT09,
author = {Ghiath Al{-}Kadi and
Andrei Sergeevich Terechko},
editor = {Andr{\'{e}} Seznec and
Joel S. Emer and
Michael F. P. O'Boyle and
Margaret Martonosi and
Theo Ungerer},
title = {A Hardware Task Scheduler for Embedded Video Processing},
booktitle = {High Performance Embedded Architectures and Compilers, Fourth International
Conference, HiPEAC 2009, Paphos, Cyprus, January 25-28, 2009. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {5409},
pages = {140--152},
publisher = {Springer},
year = {2009},
url = {https://doi.org/10.1007/978-3-540-92990-1\_12},
doi = {10.1007/978-3-540-92990-1\_12},
timestamp = {Fri, 02 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/Al-KadiT09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/AnsariLKJKW09,
author = {Mohammad Ansari and
Mikel Luj{\'{a}}n and
Christos Kotselidis and
Kim Jarvis and
Chris C. Kirkham and
Ian Watson},
editor = {Andr{\'{e}} Seznec and
Joel S. Emer and
Michael F. P. O'Boyle and
Margaret Martonosi and
Theo Ungerer},
title = {Steal-on-Abort: Improving Transactional Memory Performance through
Dynamic Transaction Reordering},
booktitle = {High Performance Embedded Architectures and Compilers, Fourth International
Conference, HiPEAC 2009, Paphos, Cyprus, January 25-28, 2009. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {5409},
pages = {4--18},
publisher = {Springer},
year = {2009},
url = {https://doi.org/10.1007/978-3-540-92990-1\_3},
doi = {10.1007/978-3-540-92990-1\_3},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/AnsariLKJKW09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/AzevedoMJTHAR09,
author = {Arnaldo Azevedo and
Cor Meenderinck and
Ben H. H. Juurlink and
Andrei Sergeevich Terechko and
Jan Hoogerbrugge and
Mauricio Alvarez and
Alex Ram{\'{\i}}rez},
editor = {Andr{\'{e}} Seznec and
Joel S. Emer and
Michael F. P. O'Boyle and
Margaret Martonosi and
Theo Ungerer},
title = {Parallel {H.264} Decoding on an Embedded Multicore Processor},
booktitle = {High Performance Embedded Architectures and Compilers, Fourth International
Conference, HiPEAC 2009, Paphos, Cyprus, January 25-28, 2009. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {5409},
pages = {404--418},
publisher = {Springer},
year = {2009},
url = {https://doi.org/10.1007/978-3-540-92990-1\_29},
doi = {10.1007/978-3-540-92990-1\_29},
timestamp = {Fri, 29 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/AzevedoMJTHAR09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/BhadauriaWM09,
author = {Major Bhadauria and
Vincent M. Weaver and
Sally A. McKee},
editor = {Andr{\'{e}} Seznec and
Joel S. Emer and
Michael F. P. O'Boyle and
Margaret Martonosi and
Theo Ungerer},
title = {Accomodating Diversity in CMPs with Heterogeneous Frequencies},
booktitle = {High Performance Embedded Architectures and Compilers, Fourth International
Conference, HiPEAC 2009, Paphos, Cyprus, January 25-28, 2009. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {5409},
pages = {248--262},
publisher = {Springer},
year = {2009},
url = {https://doi.org/10.1007/978-3-540-92990-1\_19},
doi = {10.1007/978-3-540-92990-1\_19},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/BhadauriaWM09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/Bodin09,
author = {Fran{\c{c}}ois Bodin},
editor = {Andr{\'{e}} Seznec and
Joel S. Emer and
Michael F. P. O'Boyle and
Margaret Martonosi and
Theo Ungerer},
title = {Keynote: Compilers in the Manycore Era},
booktitle = {High Performance Embedded Architectures and Compilers, Fourth International
Conference, HiPEAC 2009, Paphos, Cyprus, January 25-28, 2009. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {5409},
pages = {2--3},
publisher = {Springer},
year = {2009},
url = {https://doi.org/10.1007/978-3-540-92990-1\_2},
doi = {10.1007/978-3-540-92990-1\_2},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/Bodin09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/CraeynestEE09,
author = {Kenzo Van Craeynest and
Stijn Eyerman and
Lieven Eeckhout},
editor = {Andr{\'{e}} Seznec and
Joel S. Emer and
Michael F. P. O'Boyle and
Margaret Martonosi and
Theo Ungerer},
title = {MLP-Aware Runahead Threads in a Simultaneous Multithreading Processor},
booktitle = {High Performance Embedded Architectures and Compilers, Fourth International
Conference, HiPEAC 2009, Paphos, Cyprus, January 25-28, 2009. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {5409},
pages = {110--124},
publisher = {Springer},
year = {2009},
url = {https://doi.org/10.1007/978-3-540-92990-1\_10},
doi = {10.1007/978-3-540-92990-1\_10},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/CraeynestEE09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/DingKIR09,
author = {Yang Ding and
Mahmut T. Kandemir and
Mary Jane Irwin and
Padma Raghavan},
editor = {Andr{\'{e}} Seznec and
Joel S. Emer and
Michael F. P. O'Boyle and
Margaret Martonosi and
Theo Ungerer},
title = {Adapting Application Mapping to Systematic Within-Die Process Variations
on Chip Multiprocessors},
booktitle = {High Performance Embedded Architectures and Compilers, Fourth International
Conference, HiPEAC 2009, Paphos, Cyprus, January 25-28, 2009. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {5409},
pages = {231--247},
publisher = {Springer},
year = {2009},
url = {https://doi.org/10.1007/978-3-540-92990-1\_18},
doi = {10.1007/978-3-540-92990-1\_18},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/DingKIR09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/ErikssonK09,
author = {Mattias V. Eriksson and
Christoph W. Kessler},
editor = {Andr{\'{e}} Seznec and
Joel S. Emer and
Michael F. P. O'Boyle and
Margaret Martonosi and
Theo Ungerer},
title = {Integrated Modulo Scheduling for Clustered {VLIW} Architectures},
booktitle = {High Performance Embedded Architectures and Compilers, Fourth International
Conference, HiPEAC 2009, Paphos, Cyprus, January 25-28, 2009. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {5409},
pages = {65--79},
publisher = {Springer},
year = {2009},
url = {https://doi.org/10.1007/978-3-540-92990-1\_7},
doi = {10.1007/978-3-540-92990-1\_7},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/ErikssonK09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/FarooqJJ09,
author = {Muhammad Umar Farooq and
Lizy Kurian John and
Margarida F. Jacome},
editor = {Andr{\'{e}} Seznec and
Joel S. Emer and
Michael F. P. O'Boyle and
Margaret Martonosi and
Theo Ungerer},
title = {Compiler Controlled Speculation for Power Aware {ILP} Extraction in
Dataflow Architectures},
booktitle = {High Performance Embedded Architectures and Compilers, Fourth International
Conference, HiPEAC 2009, Paphos, Cyprus, January 25-28, 2009. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {5409},
pages = {324--338},
publisher = {Springer},
year = {2009},
url = {https://doi.org/10.1007/978-3-540-92990-1\_24},
doi = {10.1007/978-3-540-92990-1\_24},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/FarooqJJ09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/FellahiC09,
author = {Mohammed Fellahi and
Albert Cohen},
editor = {Andr{\'{e}} Seznec and
Joel S. Emer and
Michael F. P. O'Boyle and
Margaret Martonosi and
Theo Ungerer},
title = {Software Pipelining in Nested Loops with Prolog-Epilog Merging},
booktitle = {High Performance Embedded Architectures and Compilers, Fourth International
Conference, HiPEAC 2009, Paphos, Cyprus, January 25-28, 2009. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {5409},
pages = {80--94},
publisher = {Springer},
year = {2009},
url = {https://doi.org/10.1007/978-3-540-92990-1\_8},
doi = {10.1007/978-3-540-92990-1\_8},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/FellahiC09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/FernandesSSM09,
author = {Gabriel Falc{\~{a}}o Paiva Fernandes and
Leonel Sousa and
V{\'{\i}}tor Manuel Mendes da Silva and
Jos{\'{e}} Marinho},
editor = {Andr{\'{e}} Seznec and
Joel S. Emer and
Michael F. P. O'Boyle and
Margaret Martonosi and
Theo Ungerer},
title = {Parallel {LDPC} Decoding on the Cell/B.E. Processor},
booktitle = {High Performance Embedded Architectures and Compilers, Fourth International
Conference, HiPEAC 2009, Paphos, Cyprus, January 25-28, 2009. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {5409},
pages = {389--403},
publisher = {Springer},
year = {2009},
url = {https://doi.org/10.1007/978-3-540-92990-1\_28},
doi = {10.1007/978-3-540-92990-1\_28},
timestamp = {Fri, 02 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/FernandesSSM09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/FursinT09,
author = {Grigori Fursin and
Olivier Temam},
editor = {Andr{\'{e}} Seznec and
Joel S. Emer and
Michael F. P. O'Boyle and
Margaret Martonosi and
Theo Ungerer},
title = {Collective Optimization},
booktitle = {High Performance Embedded Architectures and Compilers, Fourth International
Conference, HiPEAC 2009, Paphos, Cyprus, January 25-28, 2009. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {5409},
pages = {34--49},
publisher = {Springer},
year = {2009},
url = {https://doi.org/10.1007/978-3-540-92990-1\_5},
doi = {10.1007/978-3-540-92990-1\_5},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/FursinT09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/HammoudCM09,
author = {Mohammad Hammoud and
Sangyeun Cho and
Rami G. Melhem},
editor = {Andr{\'{e}} Seznec and
Joel S. Emer and
Michael F. P. O'Boyle and
Margaret Martonosi and
Theo Ungerer},
title = {{ACM:} An Efficient Approach for Managing Shared Caches in Chip Multiprocessors},
booktitle = {High Performance Embedded Architectures and Compilers, Fourth International
Conference, HiPEAC 2009, Paphos, Cyprus, January 25-28, 2009. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {5409},
pages = {355--372},
publisher = {Springer},
year = {2009},
url = {https://doi.org/10.1007/978-3-540-92990-1\_26},
doi = {10.1007/978-3-540-92990-1\_26},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/HammoudCM09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/HenryN09,
author = {Michael B. Henry and
Leyla Nazhandali},
editor = {Andr{\'{e}} Seznec and
Joel S. Emer and
Michael F. P. O'Boyle and
Margaret Martonosi and
Theo Ungerer},
title = {Hybrid Super/Subthreshold Design of a Low Power Scalable-Throughput
{FFT} Architecture},
booktitle = {High Performance Embedded Architectures and Compilers, Fourth International
Conference, HiPEAC 2009, Paphos, Cyprus, January 25-28, 2009. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {5409},
pages = {278--292},
publisher = {Springer},
year = {2009},
url = {https://doi.org/10.1007/978-3-540-92990-1\_21},
doi = {10.1007/978-3-540-92990-1\_21},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/HenryN09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/HowesLDK09,
author = {Lee W. Howes and
Anton Lokhmotov and
Alastair F. Donaldson and
Paul H. J. Kelly},
editor = {Andr{\'{e}} Seznec and
Joel S. Emer and
Michael F. P. O'Boyle and
Margaret Martonosi and
Theo Ungerer},
title = {Deriving Efficient Data Movement from Decoupled Access/Execute Specifications},
booktitle = {High Performance Embedded Architectures and Compilers, Fourth International
Conference, HiPEAC 2009, Paphos, Cyprus, January 25-28, 2009. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {5409},
pages = {168--182},
publisher = {Springer},
year = {2009},
url = {https://doi.org/10.1007/978-3-540-92990-1\_14},
doi = {10.1007/978-3-540-92990-1\_14},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/HowesLDK09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/JimenezVGGFN09,
author = {V{\'{\i}}ctor J. Jim{\'{e}}nez and
Llu{\'{\i}}s Vilanova and
Isaac Gelado and
Marisa Gil and
Grigori Fursin and
Nacho Navarro},
editor = {Andr{\'{e}} Seznec and
Joel S. Emer and
Michael F. P. O'Boyle and
Margaret Martonosi and
Theo Ungerer},
title = {Predictive Runtime Code Scheduling for Heterogeneous Architectures},
booktitle = {High Performance Embedded Architectures and Compilers, Fourth International
Conference, HiPEAC 2009, Paphos, Cyprus, January 25-28, 2009. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {5409},
pages = {19--33},
publisher = {Springer},
year = {2009},
url = {https://doi.org/10.1007/978-3-540-92990-1\_4},
doi = {10.1007/978-3-540-92990-1\_4},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/JimenezVGGFN09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/JonesT09,
author = {Daniel Jones and
Nigel P. Topham},
editor = {Andr{\'{e}} Seznec and
Joel S. Emer and
Michael F. P. O'Boyle and
Margaret Martonosi and
Theo Ungerer},
title = {High Speed {CPU} Simulation Using {LTU} Dynamic Binary Translation},
booktitle = {High Performance Embedded Architectures and Compilers, Fourth International
Conference, HiPEAC 2009, Paphos, Cyprus, January 25-28, 2009. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {5409},
pages = {50--64},
publisher = {Springer},
year = {2009},
url = {https://doi.org/10.1007/978-3-540-92990-1\_6},
doi = {10.1007/978-3-540-92990-1\_6},
timestamp = {Wed, 13 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/JonesT09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/KhanK09,
author = {Omer Khan and
Sandip Kundu},
editor = {Andr{\'{e}} Seznec and
Joel S. Emer and
Michael F. P. O'Boyle and
Margaret Martonosi and
Theo Ungerer},
title = {Predictive Thermal Management for Chip Multiprocessors Using Co-designed
Virtual Machines},
booktitle = {High Performance Embedded Architectures and Compilers, Fourth International
Conference, HiPEAC 2009, Paphos, Cyprus, January 25-28, 2009. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {5409},
pages = {293--307},
publisher = {Springer},
year = {2009},
url = {https://doi.org/10.1007/978-3-540-92990-1\_22},
doi = {10.1007/978-3-540-92990-1\_22},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/KhanK09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/KluterBCI09,
author = {Theo Kluter and
Philip Brisk and
Edoardo Charbon and
Paolo Ienne},
editor = {Andr{\'{e}} Seznec and
Joel S. Emer and
Michael F. P. O'Boyle and
Margaret Martonosi and
Theo Ungerer},
title = {MPSoC Design Using Application-Specific Architecturally Visible Communication},
booktitle = {High Performance Embedded Architectures and Compilers, Fourth International
Conference, HiPEAC 2009, Paphos, Cyprus, January 25-28, 2009. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {5409},
pages = {183--197},
publisher = {Springer},
year = {2009},
url = {https://doi.org/10.1007/978-3-540-92990-1\_15},
doi = {10.1007/978-3-540-92990-1\_15},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/KluterBCI09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/MischeUKU09,
author = {J{\"{o}}rg Mische and
Sascha Uhrig and
Florian Kluge and
Theo Ungerer},
editor = {Andr{\'{e}} Seznec and
Joel S. Emer and
Michael F. P. O'Boyle and
Margaret Martonosi and
Theo Ungerer},
title = {{IPC} Control for Multiple Real-Time Threads on an In-Order {SMT}
Processor},
booktitle = {High Performance Embedded Architectures and Compilers, Fourth International
Conference, HiPEAC 2009, Paphos, Cyprus, January 25-28, 2009. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {5409},
pages = {125--139},
publisher = {Springer},
year = {2009},
url = {https://doi.org/10.1007/978-3-540-92990-1\_11},
doi = {10.1007/978-3-540-92990-1\_11},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/MischeUKU09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/MuralidharaK09,
author = {Sai Prashanth Muralidhara and
Mahmut T. Kandemir},
editor = {Andr{\'{e}} Seznec and
Joel S. Emer and
Michael F. P. O'Boyle and
Margaret Martonosi and
Theo Ungerer},
title = {Communication Based Proactive Link Power Management},
booktitle = {High Performance Embedded Architectures and Compilers, Fourth International
Conference, HiPEAC 2009, Paphos, Cyprus, January 25-28, 2009. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {5409},
pages = {198--215},
publisher = {Springer},
year = {2009},
url = {https://doi.org/10.1007/978-3-540-92990-1\_16},
doi = {10.1007/978-3-540-92990-1\_16},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/MuralidharaK09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/NijhuisBBA09,
author = {Maik Nijhuis and
Herbert Bos and
Henri E. Bal and
C{\'{e}}dric Augonnet},
editor = {Andr{\'{e}} Seznec and
Joel S. Emer and
Michael F. P. O'Boyle and
Margaret Martonosi and
Theo Ungerer},
title = {Mapping and Synchronizing Streaming Applications on Cell Processors},
booktitle = {High Performance Embedded Architectures and Compilers, Fourth International
Conference, HiPEAC 2009, Paphos, Cyprus, January 25-28, 2009. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {5409},
pages = {216--230},
publisher = {Springer},
year = {2009},
url = {https://doi.org/10.1007/978-3-540-92990-1\_17},
doi = {10.1007/978-3-540-92990-1\_17},
timestamp = {Fri, 02 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/NijhuisBBA09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/SalamyR09,
author = {Hassan A. Salamy and
J. Ramanujam},
editor = {Andr{\'{e}} Seznec and
Joel S. Emer and
Michael F. P. O'Boyle and
Margaret Martonosi and
Theo Ungerer},
title = {A Framework for Task Scheduling and Memory Partitioning for Multi-Processor
System-on-Chip},
booktitle = {High Performance Embedded Architectures and Compilers, Fourth International
Conference, HiPEAC 2009, Paphos, Cyprus, January 25-28, 2009. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {5409},
pages = {263--277},
publisher = {Springer},
year = {2009},
url = {https://doi.org/10.1007/978-3-540-92990-1\_20},
doi = {10.1007/978-3-540-92990-1\_20},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/SalamyR09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/SubramanianM09,
author = {Suriya Subramanian and
Kathryn S. McKinley},
editor = {Andr{\'{e}} Seznec and
Joel S. Emer and
Michael F. P. O'Boyle and
Margaret Martonosi and
Theo Ungerer},
title = {HeDGE: Hybrid Dataflow Graph Execution in the Issue Logic},
booktitle = {High Performance Embedded Architectures and Compilers, Fourth International
Conference, HiPEAC 2009, Paphos, Cyprus, January 25-28, 2009. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {5409},
pages = {308--323},
publisher = {Springer},
year = {2009},
url = {https://doi.org/10.1007/978-3-540-92990-1\_23},
doi = {10.1007/978-3-540-92990-1\_23},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/SubramanianM09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/ThuressonSS09,
author = {Martin Thuresson and
Magnus Sj{\"{a}}lander and
Per Stenstr{\"{o}}m},
editor = {Andr{\'{e}} Seznec and
Joel S. Emer and
Michael F. P. O'Boyle and
Margaret Martonosi and
Theo Ungerer},
title = {A Flexible Code Compression Scheme Using Partitioned Look-Up Tables},
booktitle = {High Performance Embedded Architectures and Compilers, Fourth International
Conference, HiPEAC 2009, Paphos, Cyprus, January 25-28, 2009. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {5409},
pages = {95--109},
publisher = {Springer},
year = {2009},
url = {https://doi.org/10.1007/978-3-540-92990-1\_9},
doi = {10.1007/978-3-540-92990-1\_9},
timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/ThuressonSS09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/VandeputteE09,
author = {Frederik Vandeputte and
Lieven Eeckhout},
editor = {Andr{\'{e}} Seznec and
Joel S. Emer and
Michael F. P. O'Boyle and
Margaret Martonosi and
Theo Ungerer},
title = {Finding Stress Patterns in Microprocessor Workloads},
booktitle = {High Performance Embedded Architectures and Compilers, Fourth International
Conference, HiPEAC 2009, Paphos, Cyprus, January 25-28, 2009. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {5409},
pages = {153--167},
publisher = {Springer},
year = {2009},
url = {https://doi.org/10.1007/978-3-540-92990-1\_13},
doi = {10.1007/978-3-540-92990-1\_13},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/VandeputteE09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/WatkinsMS09,
author = {Matthew A. Watkins and
Sally A. McKee and
Lambert Schaelicke},
editor = {Andr{\'{e}} Seznec and
Joel S. Emer and
Michael F. P. O'Boyle and
Margaret Martonosi and
Theo Ungerer},
title = {Revisiting Cache Block Superloading},
booktitle = {High Performance Embedded Architectures and Compilers, Fourth International
Conference, HiPEAC 2009, Paphos, Cyprus, January 25-28, 2009. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {5409},
pages = {339--354},
publisher = {Springer},
year = {2009},
url = {https://doi.org/10.1007/978-3-540-92990-1\_25},
doi = {10.1007/978-3-540-92990-1\_25},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/WatkinsMS09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/YanamandraINKN09,
author = {Aditya Yanamandra and
Mary Jane Irwin and
Vijaykrishnan Narayanan and
Mahmut T. Kandemir and
Sri Hari Krishna Narayanan},
editor = {Andr{\'{e}} Seznec and
Joel S. Emer and
Michael F. P. O'Boyle and
Margaret Martonosi and
Theo Ungerer},
title = {In-Network Caching for Chip Multiprocessors},
booktitle = {High Performance Embedded Architectures and Compilers, Fourth International
Conference, HiPEAC 2009, Paphos, Cyprus, January 25-28, 2009. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {5409},
pages = {373--388},
publisher = {Springer},
year = {2009},
url = {https://doi.org/10.1007/978-3-540-92990-1\_27},
doi = {10.1007/978-3-540-92990-1\_27},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/YanamandraINKN09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/hipeac/2009,
editor = {Andr{\'{e}} Seznec and
Joel S. Emer and
Michael F. P. O'Boyle and
Margaret Martonosi and
Theo Ungerer},
title = {High Performance Embedded Architectures and Compilers, Fourth International
Conference, HiPEAC 2009, Paphos, Cyprus, January 25-28, 2009. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {5409},
publisher = {Springer},
year = {2009},
url = {https://doi.org/10.1007/978-3-540-92990-1},
doi = {10.1007/978-3-540-92990-1},
isbn = {978-3-540-92989-5},
timestamp = {Tue, 14 May 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/2009.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/AbouGhazalehCMM08,
author = {Nevine AbouGhazaleh and
Bruce R. Childers and
Daniel Moss{\'{e}} and
Rami G. Melhem},
editor = {Per Stenstr{\"{o}}m and
Michel Dubois and
Manolis Katevenis and
Rajiv Gupta and
Theo Ungerer},
title = {Integrated {CPU} Cache Power Management in Multiple Clock Domain Processors},
booktitle = {High Performance Embedded Architectures and Compilers, Third International
Conference, HiPEAC 2008, G{\"{o}}teborg, Sweden, January 27-29,
2008, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {4917},
pages = {209--223},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-77560-7\_15},
doi = {10.1007/978-3-540-77560-7\_15},
timestamp = {Mon, 06 Dec 2021 16:37:01 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/AbouGhazalehCMM08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/AklM08,
author = {Patrick Akl and
Andreas Moshovos},
editor = {Per Stenstr{\"{o}}m and
Michel Dubois and
Manolis Katevenis and
Rajiv Gupta and
Theo Ungerer},
title = {Turbo-ROB: {A} Low Cost Checkpoint/Restore Accelerator},
booktitle = {High Performance Embedded Architectures and Compilers, Third International
Conference, HiPEAC 2008, G{\"{o}}teborg, Sweden, January 27-29,
2008, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {4917},
pages = {258--272},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-77560-7\_18},
doi = {10.1007/978-3-540-77560-7\_18},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/AklM08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/Ben-AsherBCHKLS08,
author = {Yosi Ben{-}Asher and
Omer Boehm and
Daniel Citron and
Gadi Haber and
Moshe Klausner and
Roy Levin and
Yousef Shajrawi},
editor = {Per Stenstr{\"{o}}m and
Michel Dubois and
Manolis Katevenis and
Rajiv Gupta and
Theo Ungerer},
title = {Aggressive Function Inlining: Preventing Loop Blockings in the Instruction
Cache},
booktitle = {High Performance Embedded Architectures and Compilers, Third International
Conference, HiPEAC 2008, G{\"{o}}teborg, Sweden, January 27-29,
2008, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {4917},
pages = {384--397},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-77560-7\_26},
doi = {10.1007/978-3-540-77560-7\_26},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/Ben-AsherBCHKLS08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/BlagojevicFCN08,
author = {Filip Blagojevic and
Xizhou Feng and
Kirk W. Cameron and
Dimitrios S. Nikolopoulos},
editor = {Per Stenstr{\"{o}}m and
Michel Dubois and
Manolis Katevenis and
Rajiv Gupta and
Theo Ungerer},
title = {Modeling Multigrain Parallelism on Heterogeneous Multi-core Processors:
{A} Case Study of the Cell {BE}},
booktitle = {High Performance Embedded Architectures and Compilers, Third International
Conference, HiPEAC 2008, G{\"{o}}teborg, Sweden, January 27-29,
2008, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {4917},
pages = {38--52},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-77560-7\_4},
doi = {10.1007/978-3-540-77560-7\_4},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/BlagojevicFCN08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/BouwensBSG08,
author = {Frank Bouwens and
Mladen Berekovic and
Bjorn De Sutter and
Georgi Gaydadjiev},
editor = {Per Stenstr{\"{o}}m and
Michel Dubois and
Manolis Katevenis and
Rajiv Gupta and
Theo Ungerer},
title = {Architecture Enhancements for the {ADRES} Coarse-Grained Reconfigurable
Array},
booktitle = {High Performance Embedded Architectures and Compilers, Third International
Conference, HiPEAC 2008, G{\"{o}}teborg, Sweden, January 27-29,
2008, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {4917},
pages = {66--81},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-77560-7\_6},
doi = {10.1007/978-3-540-77560-7\_6},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/BouwensBSG08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/ChavesDKSV08,
author = {Ricardo Chaves and
Blagomir Donchev and
Georgi Kuzmanov and
Leonel Sousa and
Stamatis Vassiliadis},
editor = {Per Stenstr{\"{o}}m and
Michel Dubois and
Manolis Katevenis and
Rajiv Gupta and
Theo Ungerer},
title = {{BRAM-LUT} Tradeoff on a Polymorphic {DES} Design},
booktitle = {High Performance Embedded Architectures and Compilers, Third International
Conference, HiPEAC 2008, G{\"{o}}teborg, Sweden, January 27-29,
2008, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {4917},
pages = {55--65},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-77560-7\_5},
doi = {10.1007/978-3-540-77560-7\_5},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/ChavesDKSV08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/Chiueh08,
author = {Tzi{-}cker Chiueh},
editor = {Per Stenstr{\"{o}}m and
Michel Dubois and
Manolis Katevenis and
Rajiv Gupta and
Theo Ungerer},
title = {Fast Bounds Checking Using Debug Register},
booktitle = {High Performance Embedded Architectures and Compilers, Third International
Conference, HiPEAC 2008, G{\"{o}}teborg, Sweden, January 27-29,
2008, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {4917},
pages = {99--113},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-77560-7\_8},
doi = {10.1007/978-3-540-77560-7\_8},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/Chiueh08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/CorneroCPOR08,
author = {Marco Cornero and
Roberto Costa and
Ricardo Fern{\'{a}}ndez Pascual and
Andrea C. Ornstein and
Erven Rohou},
editor = {Per Stenstr{\"{o}}m and
Michel Dubois and
Manolis Katevenis and
Rajiv Gupta and
Theo Ungerer},
title = {An Experimental Environment Validating the Suitability of {CLI} as
an Effective Deployment Format for Embedded Systems},
booktitle = {High Performance Embedded Architectures and Compilers, Third International
Conference, HiPEAC 2008, G{\"{o}}teborg, Sweden, January 27-29,
2008, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {4917},
pages = {130--144},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-77560-7\_10},
doi = {10.1007/978-3-540-77560-7\_10},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/CorneroCPOR08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/EyermanES08,
author = {Stijn Eyerman and
Lieven Eeckhout and
James E. Smith},
editor = {Per Stenstr{\"{o}}m and
Michel Dubois and
Manolis Katevenis and
Rajiv Gupta and
Theo Ungerer},
title = {Studying Compiler Optimizations on Superscalar Processors Through
Interval Analysis},
booktitle = {High Performance Embedded Architectures and Compilers, Third International
Conference, HiPEAC 2008, G{\"{o}}teborg, Sweden, January 27-29,
2008, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {4917},
pages = {114--129},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-77560-7\_9},
doi = {10.1007/978-3-540-77560-7\_9},
timestamp = {Mon, 11 Sep 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/EyermanES08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/GarciaSFMV08,
author = {Alejandro Garc{\'{\i}}a and
Oliverio J. Santana and
Enrique Fern{\'{a}}ndez and
Pedro Medina and
Mateo Valero},
editor = {Per Stenstr{\"{o}}m and
Michel Dubois and
Manolis Katevenis and
Rajiv Gupta and
Theo Ungerer},
title = {{LPA:} {A} First Approach to the Loop Processor Architecture},
booktitle = {High Performance Embedded Architectures and Compilers, Third International
Conference, HiPEAC 2008, G{\"{o}}teborg, Sweden, January 27-29,
2008, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {4917},
pages = {273--287},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-77560-7\_19},
doi = {10.1007/978-3-540-77560-7\_19},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/GarciaSFMV08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/GoudarziIN08,
author = {Maziar Goudarzi and
Tohru Ishihara and
Hamid Noori},
editor = {Per Stenstr{\"{o}}m and
Michel Dubois and
Manolis Katevenis and
Rajiv Gupta and
Theo Ungerer},
title = {Variation-Aware Software Techniques for Cache Leakage Reduction Using
Value-Dependence of {SRAM} Leakage Due to Within-Die Process Variation},
booktitle = {High Performance Embedded Architectures and Compilers, Third International
Conference, HiPEAC 2008, G{\"{o}}teborg, Sweden, January 27-29,
2008, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {4917},
pages = {224--239},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-77560-7\_16},
doi = {10.1007/978-3-540-77560-7\_16},
timestamp = {Sat, 16 Sep 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/GoudarziIN08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/GoversHBRBNM08,
author = {Jochem Govers and
Jos Huisken and
Mladen Berekovic and
Olivier Rousseaux and
Frank Bouwens and
Michael De Nil and
Jef L. van Meerbergen},
editor = {Per Stenstr{\"{o}}m and
Michel Dubois and
Manolis Katevenis and
Rajiv Gupta and
Theo Ungerer},
title = {Implementation of an {UWB} Impulse-Radio Acquisition and Despreading
Algorithm on a Low Power {ASIP}},
booktitle = {High Performance Embedded Architectures and Compilers, Third International
Conference, HiPEAC 2008, G{\"{o}}teborg, Sweden, January 27-29,
2008, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {4917},
pages = {82--96},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-77560-7\_7},
doi = {10.1007/978-3-540-77560-7\_7},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/GoversHBRBNM08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/HahnSSA08,
author = {Todd T. Hahn and
Eric Stotzer and
Dineel Sule and
Mike Asal},
editor = {Per Stenstr{\"{o}}m and
Michel Dubois and
Manolis Katevenis and
Rajiv Gupta and
Theo Ungerer},
title = {Compilation Strategies for Reducing Code Size on a {VLIW} Processor
with Variable Length Instructions},
booktitle = {High Performance Embedded Architectures and Compilers, Third International
Conference, HiPEAC 2008, G{\"{o}}teborg, Sweden, January 27-29,
2008, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {4917},
pages = {147--160},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-77560-7\_11},
doi = {10.1007/978-3-540-77560-7\_11},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/HahnSSA08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/Kissell08,
author = {Kevin D. Kissell},
editor = {Per Stenstr{\"{o}}m and
Michel Dubois and
Manolis Katevenis and
Rajiv Gupta and
Theo Ungerer},
title = {{MIPS} {MT:} {A} Multithreaded {RISC} Architecture for Embedded Real-Time
Processing},
booktitle = {High Performance Embedded Architectures and Compilers, Third International
Conference, HiPEAC 2008, G{\"{o}}teborg, Sweden, January 27-29,
2008, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {4917},
pages = {9--21},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-77560-7\_2},
doi = {10.1007/978-3-540-77560-7\_2},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/Kissell08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/LevinNH08,
author = {Roy Levin and
Ilan Newman and
Gadi Haber},
editor = {Per Stenstr{\"{o}}m and
Michel Dubois and
Manolis Katevenis and
Rajiv Gupta and
Theo Ungerer},
title = {Complementing Missing and Inaccurate Profiling Using a Minimum Cost
Circulation Algorithm},
booktitle = {High Performance Embedded Architectures and Compilers, Third International
Conference, HiPEAC 2008, G{\"{o}}teborg, Sweden, January 27-29,
2008, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {4917},
pages = {291--304},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-77560-7\_20},
doi = {10.1007/978-3-540-77560-7\_20},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/LevinNH08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/LinC08,
author = {Chun{-}Chieh Lin and
Chuen{-}Liang Chen},
editor = {Per Stenstr{\"{o}}m and
Michel Dubois and
Manolis Katevenis and
Rajiv Gupta and
Theo Ungerer},
title = {Code Arrangement of Embedded Java Virtual Machine for {NAND} Flash
Memory},
booktitle = {High Performance Embedded Architectures and Compilers, Third International
Conference, HiPEAC 2008, G{\"{o}}teborg, Sweden, January 27-29,
2008, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {4917},
pages = {369--383},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-77560-7\_25},
doi = {10.1007/978-3-540-77560-7\_25},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/LinC08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/MoretoCRV08,
author = {Miquel Moret{\'{o}} and
Francisco J. Cazorla and
Alex Ram{\'{\i}}rez and
Mateo Valero},
editor = {Per Stenstr{\"{o}}m and
Michel Dubois and
Manolis Katevenis and
Rajiv Gupta and
Theo Ungerer},
title = {MLP-Aware Dynamic Cache Partitioning},
booktitle = {High Performance Embedded Architectures and Compilers, Third International
Conference, HiPEAC 2008, G{\"{o}}teborg, Sweden, January 27-29,
2008, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {4917},
pages = {337--352},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-77560-7\_23},
doi = {10.1007/978-3-540-77560-7\_23},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/MoretoCRV08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/PsotaA08,
author = {James Psota and
Anant Agarwal},
editor = {Per Stenstr{\"{o}}m and
Michel Dubois and
Manolis Katevenis and
Rajiv Gupta and
Theo Ungerer},
title = {rMPI: Message Passing on Multicore Processors with On-Chip Interconnect},
booktitle = {High Performance Embedded Architectures and Compilers, Third International
Conference, HiPEAC 2008, G{\"{o}}teborg, Sweden, January 27-29,
2008, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {4917},
pages = {22--37},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-77560-7\_3},
doi = {10.1007/978-3-540-77560-7\_3},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/PsotaA08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/RaghavanLAJCV08,
author = {Praveen Raghavan and
Andy Lambrechts and
Javed Absar and
Murali Jayapala and
Francky Catthoor and
Diederik Verkest},
editor = {Per Stenstr{\"{o}}m and
Michel Dubois and
Manolis Katevenis and
Rajiv Gupta and
Theo Ungerer},
title = {Coffee: COmpiler Framework for Energy-Aware Exploration},
booktitle = {High Performance Embedded Architectures and Compilers, Third International
Conference, HiPEAC 2008, G{\"{o}}teborg, Sweden, January 27-29,
2008, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {4917},
pages = {193--208},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-77560-7\_14},
doi = {10.1007/978-3-540-77560-7\_14},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/RaghavanLAJCV08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/SarkarT08,
author = {Subhradyuti Sarkar and
Dean M. Tullsen},
editor = {Per Stenstr{\"{o}}m and
Michel Dubois and
Manolis Katevenis and
Rajiv Gupta and
Theo Ungerer},
title = {Compiler Techniques for Reducing Data Cache Miss Rate on a Multithreaded
Architecture},
booktitle = {High Performance Embedded Architectures and Compilers, Third International
Conference, HiPEAC 2008, G{\"{o}}teborg, Sweden, January 27-29,
2008, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {4917},
pages = {353--368},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-77560-7\_24},
doi = {10.1007/978-3-540-77560-7\_24},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/SarkarT08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/SazeidesMCK08,
author = {Yiannakis Sazeides and
Andreas Moustakas and
Kypros Constantinides and
Marios Kleanthous},
editor = {Per Stenstr{\"{o}}m and
Michel Dubois and
Manolis Katevenis and
Rajiv Gupta and
Theo Ungerer},
title = {The Significance of Affectors and Affectees Correlations for Branch
Prediction},
booktitle = {High Performance Embedded Architectures and Compilers, Third International
Conference, HiPEAC 2008, G{\"{o}}teborg, Sweden, January 27-29,
2008, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {4917},
pages = {243--257},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-77560-7\_17},
doi = {10.1007/978-3-540-77560-7\_17},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/SazeidesMCK08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/ServatGACJ08,
author = {Harald Servat and
Cecilia Gonz{\'{a}}lez{-}Alvarez and
Xavier Aguilar and
Daniel Cabrera{-}Benitez and
Daniel Jim{\'{e}}nez{-}Gonz{\'{a}}lez},
editor = {Per Stenstr{\"{o}}m and
Michel Dubois and
Manolis Katevenis and
Rajiv Gupta and
Theo Ungerer},
title = {Drug Design Issues on the Cell {BE}},
booktitle = {High Performance Embedded Architectures and Compilers, Third International
Conference, HiPEAC 2008, G{\"{o}}teborg, Sweden, January 27-29,
2008, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {4917},
pages = {176--190},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-77560-7\_13},
doi = {10.1007/978-3-540-77560-7\_13},
timestamp = {Wed, 14 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/ServatGACJ08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/ValeroL08,
author = {Mateo Valero and
Jes{\'{u}}s Labarta},
editor = {Per Stenstr{\"{o}}m and
Michel Dubois and
Manolis Katevenis and
Rajiv Gupta and
Theo Ungerer},
title = {Supercomputing for the Future, Supercomputing from the Past (Keynote)},
booktitle = {High Performance Embedded Architectures and Compilers, Third International
Conference, HiPEAC 2008, G{\"{o}}teborg, Sweden, January 27-29,
2008, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {4917},
pages = {3--5},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-77560-7\_1},
doi = {10.1007/978-3-540-77560-7\_1},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/ValeroL08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/VandeputteE08,
author = {Frederik Vandeputte and
Lieven Eeckhout},
editor = {Per Stenstr{\"{o}}m and
Michel Dubois and
Manolis Katevenis and
Rajiv Gupta and
Theo Ungerer},
title = {Phase Complexity Surfaces: Characterizing Time-Varying Program Behavior},
booktitle = {High Performance Embedded Architectures and Compilers, Third International
Conference, HiPEAC 2008, G{\"{o}}teborg, Sweden, January 27-29,
2008, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {4917},
pages = {320--334},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-77560-7\_22},
doi = {10.1007/978-3-540-77560-7\_22},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/VandeputteE08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/VandierendonckRQB08,
author = {Hans Vandierendonck and
Sean Rul and
Michiel Questier and
Koen De Bosschere},
editor = {Per Stenstr{\"{o}}m and
Michel Dubois and
Manolis Katevenis and
Rajiv Gupta and
Theo Ungerer},
title = {Experiences with Parallelizing a Bio-informatics Program on the Cell
{BE}},
booktitle = {High Performance Embedded Architectures and Compilers, Third International
Conference, HiPEAC 2008, G{\"{o}}teborg, Sweden, January 27-29,
2008, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {4917},
pages = {161--175},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-77560-7\_12},
doi = {10.1007/978-3-540-77560-7\_12},
timestamp = {Fri, 02 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/VandierendonckRQB08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/WeaverM08,
author = {Vincent M. Weaver and
Sally A. McKee},
editor = {Per Stenstr{\"{o}}m and
Michel Dubois and
Manolis Katevenis and
Rajiv Gupta and
Theo Ungerer},
title = {Using Dynamic Binary Instrumentation to Generate Multi-platform SimPoints:
Methodology and Accuracy},
booktitle = {High Performance Embedded Architectures and Compilers, Third International
Conference, HiPEAC 2008, G{\"{o}}teborg, Sweden, January 27-29,
2008, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {4917},
pages = {305--319},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-77560-7\_21},
doi = {10.1007/978-3-540-77560-7\_21},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/WeaverM08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/hipeac/2008,
editor = {Per Stenstr{\"{o}}m and
Michel Dubois and
Manolis Katevenis and
Rajiv Gupta and
Theo Ungerer},
title = {High Performance Embedded Architectures and Compilers, Third International
Conference, HiPEAC 2008, G{\"{o}}teborg, Sweden, January 27-29,
2008, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {4917},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-77560-7},
doi = {10.1007/978-3-540-77560-7},
isbn = {978-3-540-77559-1},
timestamp = {Mon, 06 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/2008.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/BhadauriaMST07,
author = {Major Bhadauria and
Sally A. McKee and
Karan Singh and
Gary S. Tyson},
editor = {Koen De Bosschere and
David R. Kaeli and
Per Stenstr{\"{o}}m and
David B. Whalley and
Theo Ungerer},
title = {Leveraging High Performance Data Cache Techniques to Save Power in
Embedded Systems},
booktitle = {High Performance Embedded Architectures and Compilers, Second International
Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {4367},
pages = {23--37},
publisher = {Springer},
year = {2007},
url = {https://doi.org/10.1007/978-3-540-69338-3\_3},
doi = {10.1007/978-3-540-69338-3\_3},
timestamp = {Tue, 14 May 2019 10:00:51 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/BhadauriaMST07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/ChuangNCJ07,
author = {Weihaw Chuang and
Satish Narayanasamy and
Brad Calder and
Ranjit Jhala},
editor = {Koen De Bosschere and
David R. Kaeli and
Per Stenstr{\"{o}}m and
David B. Whalley and
Theo Ungerer},
title = {Bounds Checking with Taint-Based Analysis},
booktitle = {High Performance Embedded Architectures and Compilers, Second International
Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {4367},
pages = {71--86},
publisher = {Springer},
year = {2007},
url = {https://doi.org/10.1007/978-3-540-69338-3\_6},
doi = {10.1007/978-3-540-69338-3\_6},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/ChuangNCJ07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/Conte07,
author = {Thomas M. Conte},
editor = {Koen De Bosschere and
David R. Kaeli and
Per Stenstr{\"{o}}m and
David B. Whalley and
Theo Ungerer},
title = {Keynote: Insight, Not (Random) Numbers: An Embedded Perspective},
booktitle = {High Performance Embedded Architectures and Compilers, Second International
Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {4367},
pages = {3},
publisher = {Springer},
year = {2007},
url = {https://doi.org/10.1007/978-3-540-69338-3\_1},
doi = {10.1007/978-3-540-69338-3\_1},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/Conte07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/DAlbertoPF07,
author = {Paolo D'Alberto and
Markus P{\"{u}}schel and
Franz Franchetti},
editor = {Koen De Bosschere and
David R. Kaeli and
Per Stenstr{\"{o}}m and
David B. Whalley and
Theo Ungerer},
title = {Performance/Energy Optimization of {DSP} Transforms on the XScale
Processor},
booktitle = {High Performance Embedded Architectures and Compilers, Second International
Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {4367},
pages = {201--214},
publisher = {Springer},
year = {2007},
url = {https://doi.org/10.1007/978-3-540-69338-3\_14},
doi = {10.1007/978-3-540-69338-3\_14},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/DAlbertoPF07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/FursinCOT07,
author = {Grigori Fursin and
John Cavazos and
Michael F. P. O'Boyle and
Olivier Temam},
editor = {Koen De Bosschere and
David R. Kaeli and
Per Stenstr{\"{o}}m and
David B. Whalley and
Theo Ungerer},
title = {MiDataSets: Creating the Conditions for a More Realistic Evaluation
of Iterative Optimization},
booktitle = {High Performance Embedded Architectures and Compilers, Second International
Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {4367},
pages = {245--260},
publisher = {Springer},
year = {2007},
url = {https://doi.org/10.1007/978-3-540-69338-3\_17},
doi = {10.1007/978-3-540-69338-3\_17},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/FursinCOT07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/GuhaHS07,
author = {Apala Guha and
Kim M. Hazelwood and
Mary Lou Soffa},
editor = {Koen De Bosschere and
David R. Kaeli and
Per Stenstr{\"{o}}m and
David B. Whalley and
Theo Ungerer},
title = {Reducing Exit Stub Memory Consumption in Code Caches},
booktitle = {High Performance Embedded Architectures and Compilers, Second International
Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {4367},
pages = {87--101},
publisher = {Springer},
year = {2007},
url = {https://doi.org/10.1007/978-3-540-69338-3\_7},
doi = {10.1007/978-3-540-69338-3\_7},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/GuhaHS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/HofstraG07,
author = {Klaas L. Hofstra and
Sabih H. Gerez},
editor = {Koen De Bosschere and
David R. Kaeli and
Per Stenstr{\"{o}}m and
David B. Whalley and
Theo Ungerer},
title = {Arx: {A} Toolset for the Efficient Simulation and Direct Synthesis
of High-Performance Signal Processing Algorithms},
booktitle = {High Performance Embedded Architectures and Compilers, Second International
Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {4367},
pages = {215--226},
publisher = {Springer},
year = {2007},
url = {https://doi.org/10.1007/978-3-540-69338-3\_15},
doi = {10.1007/978-3-540-69338-3\_15},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/HofstraG07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/HuJK07,
author = {Chunling Hu and
Daniel A. Jim{\'{e}}nez and
Ulrich Kremer},
editor = {Koen De Bosschere and
David R. Kaeli and
Per Stenstr{\"{o}}m and
David B. Whalley and
Theo Ungerer},
title = {Efficient Program Power Behavior Characterization},
booktitle = {High Performance Embedded Architectures and Compilers, Second International
Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {4367},
pages = {183--197},
publisher = {Springer},
year = {2007},
url = {https://doi.org/10.1007/978-3-540-69338-3\_13},
doi = {10.1007/978-3-540-69338-3\_13},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/HuJK07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/HuynhABT07,
author = {Johnny Huynh and
Jos{\'{e}} Nelson Amaral and
Paul Berube and
Sid Ahmed Ali Touati},
editor = {Koen De Bosschere and
David R. Kaeli and
Per Stenstr{\"{o}}m and
David B. Whalley and
Theo Ungerer},
title = {Evaluation of Offset Assignment Heuristics},
booktitle = {High Performance Embedded Architectures and Compilers, Second International
Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {4367},
pages = {261--275},
publisher = {Springer},
year = {2007},
url = {https://doi.org/10.1007/978-3-540-69338-3\_18},
doi = {10.1007/978-3-540-69338-3\_18},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/HuynhABT07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/KeramidasXK07,
author = {Georgios Keramidas and
Polychronis Xekalakis and
Stefanos Kaxiras},
editor = {Koen De Bosschere and
David R. Kaeli and
Per Stenstr{\"{o}}m and
David B. Whalley and
Theo Ungerer},
title = {Applying Decay to Reduce Dynamic Power in Set-Associative Caches},
booktitle = {High Performance Embedded Architectures and Compilers, Second International
Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {4367},
pages = {38--53},
publisher = {Springer},
year = {2007},
url = {https://doi.org/10.1007/978-3-540-69338-3\_4},
doi = {10.1007/978-3-540-69338-3\_4},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/KeramidasXK07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/KluyskensE07,
author = {Simon Kluyskens and
Lieven Eeckhout},
editor = {Koen De Bosschere and
David R. Kaeli and
Per Stenstr{\"{o}}m and
David B. Whalley and
Theo Ungerer},
title = {Branch History Matching: Branch Predictor Warmup for Sampled Simulation},
booktitle = {High Performance Embedded Architectures and Compilers, Second International
Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {4367},
pages = {153--167},
publisher = {Springer},
year = {2007},
url = {https://doi.org/10.1007/978-3-540-69338-3\_11},
doi = {10.1007/978-3-540-69338-3\_11},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/KluyskensE07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/LiuLCJ07,
author = {Lixia Liu and
Xiao{-}Feng Li and
Michael K. Chen and
Roy Dz{-}Ching Ju},
editor = {Koen De Bosschere and
David R. Kaeli and
Per Stenstr{\"{o}}m and
David B. Whalley and
Theo Ungerer},
title = {A Throughput-Driven Task Creation and Mapping for Network Processors},
booktitle = {High Performance Embedded Architectures and Compilers, Second International
Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {4367},
pages = {227--241},
publisher = {Springer},
year = {2007},
url = {https://doi.org/10.1007/978-3-540-69338-3\_16},
doi = {10.1007/978-3-540-69338-3\_16},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/LiuLCJ07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/LopezDAGL07,
author = {Sonia L{\'{o}}pez and
Steve Dropsho and
David H. Albonesi and
Oscar Garnica and
Juan Lanchares},
editor = {Koen De Bosschere and
David R. Kaeli and
Per Stenstr{\"{o}}m and
David B. Whalley and
Theo Ungerer},
title = {Dynamic Capacity-Speed Tradeoffs in {SMT} Processor Caches},
booktitle = {High Performance Embedded Architectures and Compilers, Second International
Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {4367},
pages = {136--150},
publisher = {Springer},
year = {2007},
url = {https://doi.org/10.1007/978-3-540-69338-3\_10},
doi = {10.1007/978-3-540-69338-3\_10},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/LopezDAGL07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/NagarajanGK07,
author = {Vijay Nagarajan and
Rajiv Gupta and
Arvind Krishnaswamy},
editor = {Koen De Bosschere and
David R. Kaeli and
Per Stenstr{\"{o}}m and
David B. Whalley and
Theo Ungerer},
title = {Compiler-Assisted Memory Encryption for Embedded Processors},
booktitle = {High Performance Embedded Architectures and Compilers, Second International
Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {4367},
pages = {7--22},
publisher = {Springer},
year = {2007},
url = {https://doi.org/10.1007/978-3-540-69338-3\_2},
doi = {10.1007/978-3-540-69338-3\_2},
timestamp = {Tue, 27 Feb 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/NagarajanGK07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/SaghirEA07,
author = {Mazen A. R. Saghir and
Mohamad El{-}Majzoub and
Patrick Akl},
editor = {Koen De Bosschere and
David R. Kaeli and
Per Stenstr{\"{o}}m and
David B. Whalley and
Theo Ungerer},
title = {Customizing the Datapath and {ISA} of Soft {VLIW} Processors},
booktitle = {High Performance Embedded Architectures and Compilers, Second International
Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {4367},
pages = {276--290},
publisher = {Springer},
year = {2007},
url = {https://doi.org/10.1007/978-3-540-69338-3\_19},
doi = {10.1007/978-3-540-69338-3\_19},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/SaghirEA07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/Stanley-MarbellM07,
author = {Phillip Stanley{-}Marbell and
Diana Marculescu},
editor = {Koen De Bosschere and
David R. Kaeli and
Per Stenstr{\"{o}}m and
David B. Whalley and
Theo Ungerer},
title = {\emph{Sunflower : } Full-System, Embedded Microarchitecture Evaluation},
booktitle = {High Performance Embedded Architectures and Compilers, Second International
Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {4367},
pages = {168--182},
publisher = {Springer},
year = {2007},
url = {https://doi.org/10.1007/978-3-540-69338-3\_12},
doi = {10.1007/978-3-540-69338-3\_12},
timestamp = {Fri, 02 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/Stanley-MarbellM07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/VandierendonckS07,
author = {Hans Vandierendonck and
Andr{\'{e}} Seznec},
editor = {Koen De Bosschere and
David R. Kaeli and
Per Stenstr{\"{o}}m and
David B. Whalley and
Theo Ungerer},
title = {Fetch Gating Control Through Speculative Instruction Window Weighting},
booktitle = {High Performance Embedded Architectures and Compilers, Second International
Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {4367},
pages = {120--135},
publisher = {Springer},
year = {2007},
url = {https://doi.org/10.1007/978-3-540-69338-3\_9},
doi = {10.1007/978-3-540-69338-3\_9},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/VandierendonckS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/WuHCS07,
author = {I{-}Wei Wu and
Shih{-}Chia Huang and
Chung{-}Ping Chung and
Jean Jyh{-}Jiun Shann},
editor = {Koen De Bosschere and
David R. Kaeli and
Per Stenstr{\"{o}}m and
David B. Whalley and
Theo Ungerer},
title = {Instruction Set Extension Generation with Considering Physical Constraints},
booktitle = {High Performance Embedded Architectures and Compilers, Second International
Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {4367},
pages = {291--305},
publisher = {Springer},
year = {2007},
url = {https://doi.org/10.1007/978-3-540-69338-3\_20},
doi = {10.1007/978-3-540-69338-3\_20},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/WuHCS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/YanZ07,
author = {Jun Yan and
Wei Zhang},
editor = {Koen De Bosschere and
David R. Kaeli and
Per Stenstr{\"{o}}m and
David B. Whalley and
Theo Ungerer},
title = {Virtual Registers: Reducing Register Pressure Without Enlarging the
Register File},
booktitle = {High Performance Embedded Architectures and Compilers, Second International
Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {4367},
pages = {57--70},
publisher = {Springer},
year = {2007},
url = {https://doi.org/10.1007/978-3-540-69338-3\_5},
doi = {10.1007/978-3-540-69338-3\_5},
timestamp = {Wed, 11 Jul 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/YanZ07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/YehCCY07,
author = {Chang{-}Ching Yeh and
Kuei{-}Chung Chang and
Tien{-}Fu Chen and
Chingwei Yeh},
editor = {Koen De Bosschere and
David R. Kaeli and
Per Stenstr{\"{o}}m and
David B. Whalley and
Theo Ungerer},
title = {Reducing Branch Misprediction Penalties Via Adaptive Pipeline Scaling},
booktitle = {High Performance Embedded Architectures and Compilers, Second International
Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {4367},
pages = {105--119},
publisher = {Springer},
year = {2007},
url = {https://doi.org/10.1007/978-3-540-69338-3\_8},
doi = {10.1007/978-3-540-69338-3\_8},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/YehCCY07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/hipeac/2007,
editor = {Koen De Bosschere and
David R. Kaeli and
Per Stenstr{\"{o}}m and
David B. Whalley and
Theo Ungerer},
title = {High Performance Embedded Architectures and Compilers, Second International
Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {4367},
publisher = {Springer},
year = {2007},
url = {https://doi.org/10.1007/978-3-540-69338-3},
doi = {10.1007/978-3-540-69338-3},
isbn = {978-3-540-69337-6},
timestamp = {Tue, 14 May 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/2007.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/BiesbrouckEC05,
author = {Michael Van Biesbrouck and
Lieven Eeckhout and
Brad Calder},
editor = {Thomas M. Conte and
Nacho Navarro and
Wen{-}mei W. Hwu and
Mateo Valero and
Theo Ungerer},
title = {Efficient Sampling Startup for Sampled Processor Simulation},
booktitle = {High Performance Embedded Architectures and Compilers, First International
Conference, HiPEAC 2005, Barcelona, Spain, November 17-18, 2005, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3793},
pages = {47--67},
publisher = {Springer},
year = {2005},
url = {https://doi.org/10.1007/11587514\_5},
doi = {10.1007/11587514\_5},
timestamp = {Tue, 14 May 2019 10:00:51 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/BiesbrouckEC05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/BuytaertVEB05,
author = {Dries Buytaert and
Kris Venstermans and
Lieven Eeckhout and
Koen De Bosschere},
editor = {Thomas M. Conte and
Nacho Navarro and
Wen{-}mei W. Hwu and
Mateo Valero and
Theo Ungerer},
title = {Garbage Collection Hints},
booktitle = {High Performance Embedded Architectures and Compilers, First International
Conference, HiPEAC 2005, Barcelona, Spain, November 17-18, 2005, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3793},
pages = {233--248},
publisher = {Springer},
year = {2005},
url = {https://doi.org/10.1007/11587514\_16},
doi = {10.1007/11587514\_16},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/BuytaertVEB05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/FursinCOT05,
author = {Grigori Fursin and
Albert Cohen and
Michael F. P. O'Boyle and
Olivier Temam},
editor = {Thomas M. Conte and
Nacho Navarro and
Wen{-}mei W. Hwu and
Mateo Valero and
Theo Ungerer},
title = {A Practical Method for Quickly Evaluating Program Optimizations},
booktitle = {High Performance Embedded Architectures and Compilers, First International
Conference, HiPEAC 2005, Barcelona, Spain, November 17-18, 2005, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3793},
pages = {29--46},
publisher = {Springer},
year = {2005},
url = {https://doi.org/10.1007/11587514\_4},
doi = {10.1007/11587514\_4},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/FursinCOT05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/GarciaFDJQN05,
author = {Pedro Javier Garc{\'{\i}}a and
Jos{\'{e}} Flich and
Jos{\'{e}} Duato and
Ian Johnson and
Francisco J. Quiles and
Finbar Naven},
editor = {Thomas M. Conte and
Nacho Navarro and
Wen{-}mei W. Hwu and
Mateo Valero and
Theo Ungerer},
title = {Dynamic Evolution of Congestion Trees: Analysis and Impact on Switch
Architecture},
booktitle = {High Performance Embedded Architectures and Compilers, First International
Conference, HiPEAC 2005, Barcelona, Spain, November 17-18, 2005, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3793},
pages = {266--285},
publisher = {Springer},
year = {2005},
url = {https://doi.org/10.1007/11587514\_18},
doi = {10.1007/11587514\_18},
timestamp = {Mon, 18 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/GarciaFDJQN05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/GeigerMT05,
author = {Michael J. Geiger and
Sally A. McKee and
Gary S. Tyson},
editor = {Thomas M. Conte and
Nacho Navarro and
Wen{-}mei W. Hwu and
Mateo Valero and
Theo Ungerer},
title = {Beyond Basic Region Caching: Specializing Cache Structures for High
Performance and Energy Conservation},
booktitle = {High Performance Embedded Architectures and Compilers, First International
Conference, HiPEAC 2005, Barcelona, Spain, November 17-18, 2005, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3793},
pages = {102--115},
publisher = {Springer},
year = {2005},
url = {https://doi.org/10.1007/11587514\_8},
doi = {10.1007/11587514\_8},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/GeigerMT05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/GomathisankaranT05,
author = {Mahadevan Gomathisankaran and
Akhilesh Tyagi},
editor = {Thomas M. Conte and
Nacho Navarro and
Wen{-}mei W. Hwu and
Mateo Valero and
Theo Ungerer},
title = {Arc3D: {A} 3D Obfuscation Architecture},
booktitle = {High Performance Embedded Architectures and Compilers, First International
Conference, HiPEAC 2005, Barcelona, Spain, November 17-18, 2005, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3793},
pages = {184--199},
publisher = {Springer},
year = {2005},
url = {https://doi.org/10.1007/11587514\_13},
doi = {10.1007/11587514\_13},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/GomathisankaranT05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/KimKHLY05,
author = {Jinpyo Kim and
Sreekumar V. Kodakara and
Wei{-}Chung Hsu and
David J. Lilja and
Pen{-}Chung Yew},
editor = {Thomas M. Conte and
Nacho Navarro and
Wen{-}mei W. Hwu and
Mateo Valero and
Theo Ungerer},
title = {Dynamic Code Region {(DCR)} Based Program Phase Tracking and Prediction
for Dynamic Optimizations},
booktitle = {High Performance Embedded Architectures and Compilers, First International
Conference, HiPEAC 2005, Barcelona, Spain, November 17-18, 2005, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3793},
pages = {203--217},
publisher = {Springer},
year = {2005},
url = {https://doi.org/10.1007/11587514\_14},
doi = {10.1007/11587514\_14},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/KimKHLY05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/KimO05,
author = {Hyun{-}Gyu Kim and
Hyeong{-}Cheol Oh},
editor = {Thomas M. Conte and
Nacho Navarro and
Wen{-}mei W. Hwu and
Mateo Valero and
Theo Ungerer},
title = {A Low-Power DSP-Enhanced 32-Bit {EISC} Processor},
booktitle = {High Performance Embedded Architectures and Compilers, First International
Conference, HiPEAC 2005, Barcelona, Spain, November 17-18, 2005, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3793},
pages = {302--316},
publisher = {Springer},
year = {2005},
url = {https://doi.org/10.1007/11587514\_20},
doi = {10.1007/11587514\_20},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/KimO05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/LeeLHWMMF05,
author = {Hyunseok Lee and
Yuan Lin and
Yoav Harel and
Mark Woh and
Scott A. Mahlke and
Trevor N. Mudge and
Kriszti{\'{a}}n Flautner},
editor = {Thomas M. Conte and
Nacho Navarro and
Wen{-}mei W. Hwu and
Mateo Valero and
Theo Ungerer},
title = {Software Defined Radio - {A} High Performance Embedded Challenge},
booktitle = {High Performance Embedded Architectures and Compilers, First International
Conference, HiPEAC 2005, Barcelona, Spain, November 17-18, 2005, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3793},
pages = {6--26},
publisher = {Springer},
year = {2005},
url = {https://doi.org/10.1007/11587514\_3},
doi = {10.1007/11587514\_3},
timestamp = {Thu, 26 Apr 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/LeeLHWMMF05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/Levy05,
author = {Markus Levy},
editor = {Thomas M. Conte and
Nacho Navarro and
Wen{-}mei W. Hwu and
Mateo Valero and
Theo Ungerer},
title = {Using {EEMBC} Benchmarks to Understand Processor Behavior in Embedded
Applications},
booktitle = {High Performance Embedded Architectures and Compilers, First International
Conference, HiPEAC 2005, Barcelona, Spain, November 17-18, 2005, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3793},
pages = {3--4},
publisher = {Springer},
year = {2005},
url = {https://doi.org/10.1007/11587514\_1},
doi = {10.1007/11587514\_1},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/Levy05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/LiVCG05,
author = {Bengu Li and
Ganesh Venkatesh and
Brad Calder and
Rajiv Gupta},
editor = {Thomas M. Conte and
Nacho Navarro and
Wen{-}mei W. Hwu and
Mateo Valero and
Theo Ungerer},
title = {Exploiting a Computation Reuse Cache to Reduce Energy in Network Processors},
booktitle = {High Performance Embedded Architectures and Compilers, First International
Conference, HiPEAC 2005, Barcelona, Spain, November 17-18, 2005, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3793},
pages = {251--265},
publisher = {Springer},
year = {2005},
url = {https://doi.org/10.1007/11587514\_17},
doi = {10.1007/11587514\_17},
timestamp = {Tue, 27 Feb 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipeac/LiVCG05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/MoloneyGMM05,
author = {David Moloney and
Dermot Geraghty and
Colm McSweeney and
Ciar{\'{a}}n McElroy},
editor = {Thomas M. Conte and
Nacho Navarro and
Wen{-}mei W. Hwu and
Mateo Valero and
Theo Ungerer},
title = {Streaming Sparse Matrix Compression/Decompression},
booktitle = {High Performance Embedded Architectures and Compilers, First International
Conference, HiPEAC 2005, Barcelona, Spain, November 17-18, 2005, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3793},
pages = {116--129},
publisher = {Springer},
year = {2005},
url = {https://doi.org/10.1007/11587514\_9},
doi = {10.1007/11587514\_9},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/MoloneyGMM05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/MoyaGRFE05,
author = {Victor Moya Del Barrio and
Carlos Gonz{\'{a}}lez and
Jordi Roca and
Agust{\'{\i}}n Fern{\'{a}}ndez and
Roger Espasa},
editor = {Thomas M. Conte and
Nacho Navarro and
Wen{-}mei W. Hwu and
Mateo Valero and
Theo Ungerer},
title = {A Single (Unified) Shader {GPU} Microarchitecture for Embedded Systems},
booktitle = {High Performance Embedded Architectures and Compilers, First International
Conference, HiPEAC 2005, Barcelona, Spain, November 17-18, 2005, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3793},
pages = {286--301},
publisher = {Springer},
year = {2005},
url = {https://doi.org/10.1007/11587514\_19},
doi = {10.1007/11587514\_19},
timestamp = {Mon, 30 Mar 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/MoyaGRFE05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/NingK05,
author = {Ke Ning and
David R. Kaeli},
editor = {Thomas M. Conte and
Nacho Navarro and
Wen{-}mei W. Hwu and
Mateo Valero and
Theo Ungerer},
title = {Power Aware External Bus Arbitration for System-on-a-Chip Embedded
Systems},
booktitle = {High Performance Embedded Architectures and Compilers, First International
Conference, HiPEAC 2005, Barcelona, Spain, November 17-18, 2005, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3793},
pages = {87--101},
publisher = {Springer},
year = {2005},
url = {https://doi.org/10.1007/11587514\_7},
doi = {10.1007/11587514\_7},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/NingK05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/PopCS05,
author = {Sebastian Pop and
Albert Cohen and
Georges{-}Andr{\'{e}} Silber},
editor = {Thomas M. Conte and
Nacho Navarro and
Wen{-}mei W. Hwu and
Mateo Valero and
Theo Ungerer},
title = {Induction Variable Analysis with Delayed Abstractions},
booktitle = {High Performance Embedded Architectures and Compilers, First International
Conference, HiPEAC 2005, Barcelona, Spain, November 17-18, 2005, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3793},
pages = {218--232},
publisher = {Springer},
year = {2005},
url = {https://doi.org/10.1007/11587514\_15},
doi = {10.1007/11587514\_15},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/PopCS05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/ShiLL05,
author = {Weidong Shi and
Chenghuai Lu and
Hsien{-}Hsin S. Lee},
editor = {Thomas M. Conte and
Nacho Navarro and
Wen{-}mei W. Hwu and
Mateo Valero and
Theo Ungerer},
title = {Memory-Centric Security Architecture},
booktitle = {High Performance Embedded Architectures and Compilers, First International
Conference, HiPEAC 2005, Barcelona, Spain, November 17-18, 2005, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3793},
pages = {153--168},
publisher = {Springer},
year = {2005},
url = {https://doi.org/10.1007/11587514\_11},
doi = {10.1007/11587514\_11},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/ShiLL05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/ShoufanHC05,
author = {Abdulhadi Shoufan and
Sorin A. Huss and
Murtuza Cutleriwala},
editor = {Thomas M. Conte and
Nacho Navarro and
Wen{-}mei W. Hwu and
Mateo Valero and
Theo Ungerer},
title = {A Novel Batch Rekeying Processor Architecture for Secure Multicast
Key Management},
booktitle = {High Performance Embedded Architectures and Compilers, First International
Conference, HiPEAC 2005, Barcelona, Spain, November 17-18, 2005, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3793},
pages = {169--183},
publisher = {Springer},
year = {2005},
url = {https://doi.org/10.1007/11587514\_12},
doi = {10.1007/11587514\_12},
timestamp = {Thu, 15 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/ShoufanHC05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/Stenstrom05,
author = {Per Stenstr{\"{o}}m},
editor = {Thomas M. Conte and
Nacho Navarro and
Wen{-}mei W. Hwu and
Mateo Valero and
Theo Ungerer},
title = {The Chip-Multiprocessing Paradigm Shift: Opportunities and Challenges},
booktitle = {High Performance Embedded Architectures and Compilers, First International
Conference, HiPEAC 2005, Barcelona, Spain, November 17-18, 2005, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3793},
pages = {5},
publisher = {Springer},
year = {2005},
url = {https://doi.org/10.1007/11587514\_2},
doi = {10.1007/11587514\_2},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/Stenstrom05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/WuZLFGPY05,
author = {Gansha Wu and
Xin Zhou and
Guei{-}Yuan Lueh and
Jesse Z. Fang and
Peng Guo and
Jinzhan Peng and
Victor Ying},
editor = {Thomas M. Conte and
Nacho Navarro and
Wen{-}mei W. Hwu and
Mateo Valero and
Theo Ungerer},
title = {{XAMM:} {A} High-Performance Automatic Memory Management System with
Memory-Constrained Designs},
booktitle = {High Performance Embedded Architectures and Compilers, First International
Conference, HiPEAC 2005, Barcelona, Spain, November 17-18, 2005, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3793},
pages = {130--149},
publisher = {Springer},
year = {2005},
url = {https://doi.org/10.1007/11587514\_10},
doi = {10.1007/11587514\_10},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/WuZLFGPY05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/YuYCLB05,
author = {Jia Yu and
Jun Yang and
Shaojie Chen and
Yan Luo and
Laxmi N. Bhuyan},
editor = {Thomas M. Conte and
Nacho Navarro and
Wen{-}mei W. Hwu and
Mateo Valero and
Theo Ungerer},
title = {Enhancing Network Processor Simulation Speed with Statistical Input
Sampling},
booktitle = {High Performance Embedded Architectures and Compilers, First International
Conference, HiPEAC 2005, Barcelona, Spain, November 17-18, 2005, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3793},
pages = {68--83},
publisher = {Springer},
year = {2005},
url = {https://doi.org/10.1007/11587514\_6},
doi = {10.1007/11587514\_6},
timestamp = {Thu, 26 Sep 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/YuYCLB05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/hipeac/2005,
editor = {Thomas M. Conte and
Nacho Navarro and
Wen{-}mei W. Hwu and
Mateo Valero and
Theo Ungerer},
title = {High Performance Embedded Architectures and Compilers, First International
Conference, HiPEAC 2005, Barcelona, Spain, November 17-18, 2005, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3793},
publisher = {Springer},
year = {2005},
url = {https://doi.org/10.1007/11587514},
doi = {10.1007/11587514},
isbn = {3-540-30317-0},
timestamp = {Tue, 14 May 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hipeac/2005.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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