:facetid:toc:\"db/conf/itc/itc2002.bht\"OK:facetid:toc:db/conf/itc/itc2002.bhtJacob A. AbrahamVivekananda M. VedulaDaniel G. SaabVerifying Properties Using Sequential ATPG.ITC194-2022002Conference and Workshop Papersclosedconf/itc/AbrahamVS0210.1109/TEST.2002.1041761https://doi.org/10.1109/TEST.2002.1041761https://dblp.org/rec/conf/itc/AbrahamVS02URL#6294041Bartomeu AlordaM. RosalesJerry M. SodenCharles F. HawkinsJaume Segura 0001Charge Based Transient Current Testing (CBT) for Submicron CMOS SRAMs.ITC947-9532002Conference and Workshop Papersclosedconf/itc/AlordaRSHS0210.1109/TEST.2002.1041850https://doi.org/10.1109/TEST.2002.1041850https://dblp.org/rec/conf/itc/AlordaRSHS02URL#6294042Anthony P. AmblerIs It Rocket Science?ITC1188-11892002Conference and Workshop Papersclosedconf/itc/Ambler0210.1109/TEST.2002.1041896https://doi.org/10.1109/TEST.2002.1041896https://dblp.org/rec/conf/itc/Ambler02URL#6294043Davide AppelloThe Yield of Test Outsourcing.ITC12152002Conference and Workshop Papersclosedconf/itc/Appello0210.1109/TEST.2002.1041919https://doi.org/10.1109/TEST.2002.1041919https://dblp.org/rec/conf/itc/Appello02URL#6294044Karim ArabiMixed-Signal BIST: Fact or Fiction.ITC12022002Conference and Workshop Papersclosedconf/itc/Arabi0210.1109/TEST.2002.1041908https://doi.org/10.1109/TEST.2002.1041908https://dblp.org/rec/conf/itc/Arabi02URL#6294045Koji AsamiYasuo FurukawaMichael PurtellMotoo UedaKarl WatanabeToshifumi WatanabeWCDMA Testing with a Baseband/IF Range AWG.ITC1140-11452002Conference and Workshop Papersclosedconf/itc/AsamiFPUWW0210.1109/TEST.2002.1041871https://doi.org/10.1109/TEST.2002.1041871https://dblp.org/rec/conf/itc/AsamiFPUWW02URL#6294046Tom AustinCharisma CanlasBrady MorganJorge L. RodriguezAcross the Great Divide: Examination of Simulation Data with Actual Silicon Waveforms Improves Device Characterization and Production Test Development.ITC270-2792002Conference and Workshop Papersclosedconf/itc/AustinCMR0210.1109/TEST.2002.1041769https://doi.org/10.1109/TEST.2002.1041769https://dblp.org/rec/conf/itc/AustinCMR02URL#6294047Robert BaileyA. MetayerB. SvrcekNandu TendolkarE. WolfEric FieneMike AlexanderRick WoltenbergRajesh RainaTest Methodology for Motorola's High Performance e500 Core Based on PowerPC Instruction Set Architecture.ITC574-5832002Conference and Workshop Papersclosedconf/itc/BaileyMSTWFAWR0210.1109/TEST.2002.1041808https://doi.org/10.1109/TEST.2002.1041808https://dblp.org/rec/conf/itc/BaileyMSTWFAWR02URL#6294048Hari BalachandranKenneth M. ButlerNeil SimpsonFacilitating Rapid First Silicon Debug.ITC628-6372002Conference and Workshop Papersclosedconf/itc/BalachandranBS0210.1109/TEST.2002.1041814https://doi.org/10.1109/TEST.2002.1041814https://dblp.org/rec/conf/itc/BalachandranBS02URL#6294049Andrea BaldiniAlfredo BensoPaolo PrinettoSergio MoAndrea TaddeiEfficient Design of System Test: A Layered Architecture.ITC930-9392002Conference and Workshop Papersclosedconf/itc/BaldiniBPMT0210.1109/TEST.2002.1041848https://doi.org/10.1109/TEST.2002.1041848https://dblp.org/rec/conf/itc/BaldiniBPMT02URL#6294050Thomas S. BarnettMatt GradyKathleen G. PurdyAdit D. SinghRedundancy Implications for Early-Life Reliability: Experimental Verification of an Integrated Yield-Reliability Model.ITC693-6992002Conference and Workshop Papersclosedconf/itc/BarnettGPS0210.1109/TEST.2002.1041821https://doi.org/10.1109/TEST.2002.1041821https://dblp.org/rec/conf/itc/BarnettGPS02URL#6294051Roger BarthSelective Optimization of Test for Embedded Flash Memory.ITC12222002Conference and Workshop Papersclosedconf/itc/Barth0210.1109/TEST.2002.1041925https://doi.org/10.1109/TEST.2002.1041925https://dblp.org/rec/conf/itc/Barth02URL#6294052Nadir Z. BasturkmenSudhakar M. ReddyIrith PomeranzPseudo Random Patterns Using Markov Sources for Scan BIST.ITC1013-10212002Conference and Workshop Papersclosedconf/itc/BasturkmenRP0210.1109/TEST.2002.1041857https://doi.org/10.1109/TEST.2002.1041857https://dblp.org/rec/conf/itc/BasturkmenRP02URL#6294053Frank te BeestAd M. G. PeetersMarc VerraKees van Berkel 0001Hans G. KerkhoffAutomatic Scan Insertion and Test Generation for Asynchronous Circuits.ITC804-8132002Conference and Workshop Papersclosedconf/itc/BeestPVBK0210.1109/TEST.2002.1041834https://doi.org/10.1109/TEST.2002.1041834https://dblp.org/rec/conf/itc/BeestPVBK02URL#6294054Dawit BeleteAshutosh RazdanWilliam SchwarzRajesh RainaChristopher HawkinsJeff MoreheadUse of DFT Techniques In Speed Grading a 1GHz+ Microprocessor .ITC1111-11192002Conference and Workshop Papersclosedconf/itc/BeleteRSRHM0210.1109/TEST.2002.1041868https://doi.org/10.1109/TEST.2002.1041868https://dblp.org/rec/conf/itc/BeleteRSRHM02URL#6294055Alfredo BensoStefano Di CarloGiorgio Di NatalePaolo PrinettoStatic Analysis of SEU Effects on Software Applications.ITC500-5082002Conference and Workshop Papersclosedconf/itc/BensoCNP0210.1109/TEST.2002.1041800https://doi.org/10.1109/TEST.2002.1041800https://dblp.org/rec/conf/itc/BensoCNP02URL#6294056David I. BergmanHans EnglerImproved IDDQ Testing with Empirical Linear Prediction.ITC954-9632002Conference and Workshop Papersclosedconf/itc/BergmanE0210.1109/TEST.2002.1041851https://doi.org/10.1109/TEST.2002.1041851https://dblp.org/rec/conf/itc/BergmanE02URL#6294057David BerthelotSamit ChaudhuriHamid SavojAn Efficient Linear Time Algorithm for Scan Chain Optimization and Repartitioning.ITC781-7872002Conference and Workshop Papersclosedconf/itc/BerthelotCS0210.1109/TEST.2002.1041831https://doi.org/10.1109/TEST.2002.1041831https://dblp.org/rec/conf/itc/BerthelotCS02URL#6294058Jayanta BhadraNarayanan KrishnamurthyAutomatic Generation of Design Constraints in Verifying High Performance Embedded Dynamic Circuits.ITC213-2222002Conference and Workshop Papersclosedconf/itc/BhadraK0210.1109/TEST.2002.1041763https://doi.org/10.1109/TEST.2002.1041763https://dblp.org/rec/conf/itc/BhadraK02URL#6294059Ronald D. BlantonJohn T. ChenRao DesineniKumar N. DwarakanathWojciech MalyThomas J. VogelsFault Tuples in Diagnosis of Deep-Submicron Circuits.ITC233-2412002Conference and Workshop Papersclosedconf/itc/BlantonCDDMV0210.1109/TEST.2002.1041765https://doi.org/10.1109/TEST.2002.1041765https://dblp.org/rec/conf/itc/BlantonCDDMV02URL#6294060Yannick BonhommePatrick Girard 0001Christian LandraultSerge PravossoudovitchPower Driven Chaining of Flip-Flops in Scan Architectures.ITC796-8032002Conference and Workshop Papersclosedconf/itc/BonhommeGLP0210.1109/TEST.2002.1041833https://doi.org/10.1109/TEST.2002.1041833https://dblp.org/rec/conf/itc/BonhommeGLP02URL#6294061Bill BottomsHomegrown Tools and Equipment versus EDA and ATE Vendors: The Future of Design to Test Product Lines.ITC242002Conference and Workshop Papersclosedconf/itc/Bottoms0210.1109/ITC.2002.10006https://doi.ieeecomputersociety.org/10.1109/ITC.2002.10006https://dblp.org/rec/conf/itc/Bottoms02URL#6294062Kenneth M. ButlerIs ITC Bored with Board Test?ITC12372002Conference and Workshop Papersclosedconf/itc/Butler0210.1109/TEST.2002.1041938https://doi.org/10.1109/TEST.2002.1041938https://dblp.org/rec/conf/itc/Butler02URL#6294063Yi CaiS. A. WernerG. J. ZhangM. J. OlsenRobert D. BrinkJitter Testing for Multi-Gigabit Backplane SerDes - Techniques to Decompose and Combine Various Types of Jitter.ITC700-7092002Conference and Workshop Papersclosedconf/itc/CaiWZOB0210.1109/TEST.2002.1041822https://doi.org/10.1109/TEST.2002.1041822https://dblp.org/rec/conf/itc/CaiWZOB02URL#6294064Tapan J. ChakrabortyChen-Huan ChiangA Novel Fault Injection Method for System Verification Based on FPGA Boundary Scan Architectur.ITC923-9292002Conference and Workshop Papersclosedconf/itc/ChakrabortyC0210.1109/TEST.2002.1041847https://doi.org/10.1109/TEST.2002.1041847https://dblp.org/rec/conf/itc/ChakrabortyC02URL#6294065Sreejit ChakravartyAnkur JainNandakumar RadhakrishnanEric W. SavageSujit T. ZachariahExperimental Evaluation of Scan Tests for Bridges.ITC509-5182002Conference and Workshop Papersclosedconf/itc/ChakravartyJRSZ0210.1109/TEST.2002.1041801https://doi.org/10.1109/TEST.2002.1041801https://dblp.org/rec/conf/itc/ChakravartyJRSZ02URL#6294066Bhaskar ChatterjeeManoj SachdevAli KeshavarziA DFT Technique for Low Frequency Delay Fault Testing in High Performance Digital Circuits.ITC1130-11392002Conference and Workshop Papersclosedconf/itc/ChatterjeeSK0210.1109/TEST.2002.1041870https://doi.org/10.1109/TEST.2002.1041870https://dblp.org/rec/conf/itc/ChatterjeeSK02URL#6294067Sau-Kwo ChiuJen-Chieh YehChih-Tsun HuangCheng-Wen WuDiagonal Test and Diagnostic Schemes for Flash Memorie.ITC37-462002Conference and Workshop Papersclosedconf/itc/ChiuYHW0210.1109/TEST.2002.1041743https://doi.org/10.1109/TEST.2002.1041743https://dblp.org/rec/conf/itc/ChiuYHW02URL#6294068Michael CogswellShazia MardhaniKevin MeloccoHina AroraA Structured Graphical Tool for Analyzing Boundary Scan Violations.ITC755-7622002Conference and Workshop Papersclosedconf/itc/CogswellMMA0210.1109/TEST.2002.1041828https://doi.org/10.1109/TEST.2002.1041828https://dblp.org/rec/conf/itc/CogswellMMA02URL#6294069Dennis R. ContiMission Impossible? Open Architecture ATE.ITC12072002Conference and Workshop Papersclosedconf/itc/Conti0210.1109/TEST.2002.1041912https://doi.org/10.1109/TEST.2002.1041912https://dblp.org/rec/conf/itc/Conti02URL#6294070Bruce CowanOwen FarnsworthPeter JakobsenSteven F. OaklandMichael OuelletteDonald L. WheaterOn-Chip Repair and an ATE Independent Fusing Methodology.ITC178-1862002Conference and Workshop Papersclosedconf/itc/CowanFJOOW0210.1109/TEST.2002.1041759https://doi.org/10.1109/TEST.2002.1041759https://dblp.org/rec/conf/itc/CowanFJOOW02URL#6294071Mark CraigAlvin JeePrashant ManiarAn Integrated Approach to Yield Loss Characterization.ITC350-3562002Conference and Workshop Papersclosedconf/itc/CraigJM0210.1109/TEST.2002.1041778https://doi.org/10.1109/TEST.2002.1041778https://dblp.org/rec/conf/itc/CraigJM02URL#6294072Alfred L. CrouchTesting the Tester: What Broke? Where? When? Why?ITC282002Conference and Workshop Papersclosedconf/itc/Crouch0210.1109/ITC.2002.10003https://doi.ieeecomputersociety.org/10.1109/ITC.2002.10003https://dblp.org/rec/conf/itc/Crouch02URL#6294073W. Robert DaaschKevin CotaJames McNamesRobert MadgeNeighbor Selection for Variance Reduction in IDDQ and Other Parametric Data.ITC12402002Conference and Workshop Papersclosedconf/itc/DaaschCMM01a10.1109/TEST.2002.1041882https://doi.org/10.1109/TEST.2002.1041882https://dblp.org/rec/conf/itc/DaaschCMM01aURL#6294074Jean Michel DagaTest and Repair of Embedded Flash Memories.ITC12192002Conference and Workshop Papersclosedconf/itc/Daga0210.1109/TEST.2002.1041922https://doi.org/10.1109/TEST.2002.1041922https://dblp.org/rec/conf/itc/Daga02URL#6294075Scott Davidson 0001What Can IC Test Teach System Test?ITC11872002Conference and Workshop Papersclosedconf/itc/Davidson0210.1109/TEST.2002.1041895https://doi.org/10.1109/TEST.2002.1041895https://dblp.org/rec/conf/itc/Davidson02URL#6294076John S. DavisDavid C. KeezerMulti-Purpose Digital Test Core Utilizing Programmable Logic.ITC438-4452002Conference and Workshop Papersclosedconf/itc/DavisK0210.1109/TEST.2002.1041793https://doi.org/10.1109/TEST.2002.1041793https://dblp.org/rec/conf/itc/DavisK02URL#6294077Nilmoni DebR. D. (Shawn) BlantonBuilt-In Self Test of CMOS-MEMS Accelerometers.ITC1075-10842002Conference and Workshop Papersclosedconf/itc/DebB0210.1109/TEST.2002.1041864https://doi.org/10.1109/TEST.2002.1041864https://dblp.org/rec/conf/itc/DebB02URL#6294078Rainer DorschRamón Huerta RiveraHans-Joachim WunderlichMartin FischerAdapting an SoC to ATE Concurrent Test Capabilities.ITC1169-11752002Conference and Workshop Papersclosedconf/itc/DorschRWF0210.1109/TEST.2002.1041875https://doi.org/10.1109/TEST.2002.1041875https://dblp.org/rec/conf/itc/DorschRWF02URL#6294079Eric DupontMichael NicolaidisRobustness IPs for Reliability and Security of SoCs.ITC357-3642002Conference and Workshop Papersclosedconf/itc/DupontN0210.1109/TEST.2002.1041779https://doi.org/10.1109/TEST.2002.1041779https://dblp.org/rec/conf/itc/DupontN02URL#6294080Bill EklowIs Board Test Worth Talking About?ITC12352002Conference and Workshop Papersclosedconf/itc/Eklow0210.1109/TEST.2002.1041936https://doi.org/10.1109/TEST.2002.1041936https://dblp.org/rec/conf/itc/Eklow02URL#6294081Bill EklowCarl BarnhartKenneth P. ParkerIEEE P1149.6: A Boundary-Scan Standard for Advanced Digital Networks.ITC1056-10652002Conference and Workshop Papersclosedconf/itc/EklowBP0210.1109/TEST.2002.1041862https://doi.org/10.1109/TEST.2002.1041862https://dblp.org/rec/conf/itc/EklowBP02URL#6294082John FerrarioRandy WolfSteve MossArchitecting Millisecond Test Solutions for Wireless Phone RFIC's.ITC1151-11582002Conference and Workshop Papersclosedconf/itc/FerrarioWM0210.1109/TEST.2002.1041873https://doi.org/10.1109/TEST.2002.1041873https://dblp.org/rec/conf/itc/FerrarioWM02URL#6294083Arnold FrischA/MS BISTs: The FACTS, Just the Facts.ITC12012002Conference and Workshop Papersclosedconf/itc/Frisch0210.1109/TEST.2002.1041907https://doi.org/10.1109/TEST.2002.1041907https://dblp.org/rec/conf/itc/Frisch02URL#6294084John GatejLee SongCarol PyronRajesh RainaTom Munnsvaluating ATE Features in Terms of Test Escape Rates and Other Cost of Test Culprits.ITC1040-10492002Conference and Workshop Papersclosedconf/itc/GatejSPRM0210.1109/TEST.2002.1041860https://doi.org/10.1109/TEST.2002.1041860https://dblp.org/rec/conf/itc/GatejSPRM02URL#6294085Maurizio GavardoniUse of Pipeline Converters for ATE Applications.ITC879-8842002Conference and Workshop Papersclosedconf/itc/Gavardoni0210.1109/TEST.2002.1041842https://doi.org/10.1109/TEST.2002.1041842https://dblp.org/rec/conf/itc/Gavardoni02URL#6294086David GesselAlexander H. SlcoumAlexander D. SpruntScott ZiegenhagenRealistic Spring Probe Testing Methods and Results.ITC417-4232002Conference and Workshop Papersclosedconf/itc/GesselSSZ0210.1109/TEST.2002.1041790https://doi.org/10.1109/TEST.2002.1041790https://dblp.org/rec/conf/itc/GesselSSZ02URL#6294087M. J. GeuzebroekJ. Th. van der LindenAd J. van de GoorTest Point Insertion that Facilitates ATPG in Reducing Test Time and Data Volume.ITC138-1472002Conference and Workshop Papersclosedconf/itc/GeuzebroekLG0210.1109/TEST.2002.1041754https://doi.org/10.1109/TEST.2002.1041754https://dblp.org/rec/conf/itc/GeuzebroekLG02URL#6294088Grady GilesIs Scan (Alone) Sufficient to Test Today?s Microprocessors? Not Quite, but We Can?t Get the Job Done Without It.ITC11972002Conference and Workshop Papersclosedconf/itc/Giles0210.1109/TEST.2002.1041904https://doi.org/10.1109/TEST.2002.1041904https://dblp.org/rec/conf/itc/Giles02URL#6294089Sandeep Kumar GoelErik Jan MarinissenEffective and Efficient Test Architecture Design for SOCs.ITC529-5382002Conference and Workshop Papersclosedconf/itc/GoelM0210.1109/TEST.2002.1041803https://doi.org/10.1109/TEST.2002.1041803https://dblp.org/rec/conf/itc/GoelM02URL#6294090Sandeep Kumar GoelBart VermeulenHierarchical Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips.ITC1103-11102002Conference and Workshop Papersclosedconf/itc/GoelV0210.1109/TEST.2002.1041867https://doi.org/10.1109/TEST.2002.1041867https://dblp.org/rec/conf/itc/GoelV02URL#6294091Paul Theo GonciariBashir M. Al-HashimiNicola NicoliciIntegrated Test Data Decompression and Core Wrapper Design for Low-Cost System-on-a-Chip Testing.ITC64-732002Conference and Workshop Papersclosedconf/itc/GonciariAN0210.1109/TEST.2002.1041746https://doi.org/10.1109/TEST.2002.1041746https://dblp.org/rec/conf/itc/GonciariAN02URL#6294092Sezer Gören 0001F. Joel FergusonTesting Finite State Machines Based on a Structural Coverage Metric .ITC773-7802002Conference and Workshop Papersclosedconf/itc/GorenF0210.1109/TEST.2002.1041830https://doi.org/10.1109/TEST.2002.1041830https://dblp.org/rec/conf/itc/GorenF02URL#6294093Xinli GuWeili WangKevin LiHeon C. KimSung Soo ChungRe-Using DFT Logic for Functional and Silicon Debugging Test.ITC648-6562002Conference and Workshop Papersclosedconf/itc/GuWLKC0210.1109/TEST.2002.1041816https://doi.org/10.1109/TEST.2002.1041816https://dblp.org/rec/conf/itc/GuWLKC02URL#6294094Loïs GuillerFrederic NeuveuxS. DuggiralaR. ChandramouliRohit KapurIntegrating DFT in the Physical Synthesis Flow.ITC788-7952002Conference and Workshop Papersclosedconf/itc/GuillerNDCK0210.1109/TEST.2002.1041832https://doi.org/10.1109/TEST.2002.1041832https://dblp.org/rec/conf/itc/GuillerNDCK02URL#6294095Mohamed M. HafedGordon W. RobertsTest and Evaluation of Multiple Embedded Mixed-Signal Test Cores.ITC1022-10302002Conference and Workshop Papersclosedconf/itc/HafedR0210.1109/TEST.2002.1041858https://doi.org/10.1109/TEST.2002.1041858https://dblp.org/rec/conf/itc/HafedR02URL#6294096Kazumi HatayamaMichinobu NakaoYoshikazu KiyoshigeKoichiro NatsumeYasuo SatoTakaharu NagumoApplication of High-Quality Built-In Test to Industrial Designs.ITC1003-10122002Conference and Workshop Papersclosedconf/itc/HatayamaNKNSN0210.1109/TEST.2002.1041856https://doi.org/10.1109/TEST.2002.1041856https://dblp.org/rec/conf/itc/HatayamaNKNSN02URL#6294097Chuck HawkinsJaume Segura 0001GHz Testing and Its Fuzzy Targets.ITC12282002Conference and Workshop Papersunavailableconf/itc/HawkinsS02https://dblp.org/rec/conf/itc/HawkinsS02URL#6294098Osamu HirabayashiAzuma SuzukiTomoaki YabeAtsushi KawasumiYasuhisa TakeyamaKeiichi KushidaAkihito TohataNobuaki OtsukaDFT Techniques for Wafer-Level At-Speed Testing of High-Speed SRAMs.ITC164-1692002Conference and Workshop Papersclosedconf/itc/HirabayashiSYKTKTO0210.1109/TEST.2002.1041757https://doi.org/10.1109/TEST.2002.1041757https://dblp.org/rec/conf/itc/HirabayashiSYKTKTO02URL#6294099Kathy HirdKenneth P. ParkerBill FollisTest Coverage: What Does It Mean When a Board Test Passes?.ITC1066-10742002Conference and Workshop Papersclosedconf/itc/HirdPF0210.1109/TEST.2002.1041863https://doi.org/10.1109/TEST.2002.1041863https://dblp.org/rec/conf/itc/HirdPF02URL#6294100Dale E. HoffmanHomegrown Tools and Equipment versus EDA and ATE Vendors: The Future of Design to Test Product Lines.ITC262002Conference and Workshop Papersclosedconf/itc/Hoffman0210.1109/ITC.2002.10010https://doi.ieeecomputersociety.org/10.1109/ITC.2002.10010https://dblp.org/rec/conf/itc/Hoffman02URL#6294101Camelia HoraRene SegersStefan EichenbergerMaurice LousbergAn Effective Diagnosis Method to Support Yield Improvement.ITC260-2692002Conference and Workshop Papersclosedconf/itc/HoraSEL0210.1109/TEST.2002.1041768https://doi.org/10.1109/TEST.2002.1041768https://dblp.org/rec/conf/itc/HoraSEL02URL#6294102Yu Huang 0005Sudhakar M. ReddyWu-Tung ChengPaul ReuterNilanjan Mukherjee 0001Chien-Chung TsaiOmer SammanYahya ZaidanOptimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm.ITC74-822002Conference and Workshop Papersclosedconf/itc/HuangRCRMTSZ0210.1109/TEST.2002.1041747https://doi.org/10.1109/TEST.2002.1041747https://dblp.org/rec/conf/itc/HuangRCRMTSZ02URL#6294103Wolfram HumannCompensation of Transmission Line Loss for Gbit/s Test on ATEs.ITC430-4372002Conference and Workshop Papersclosedconf/itc/Humann0210.1109/TEST.2002.1041792https://doi.org/10.1109/TEST.2002.1041792https://dblp.org/rec/conf/itc/Humann02URL#6294104Sungbae HwangJacob A. AbrahamOptimal BIST Using an Embedded Microprocessor.ITC736-7452002Conference and Workshop Papersclosedconf/itc/HwangA0210.1109/TEST.2002.1041826https://doi.org/10.1109/TEST.2002.1041826https://dblp.org/rec/conf/itc/HwangA02URL#6294105Vikram IyengarSandeep Kumar GoelErik Jan MarinissenKrishnendu ChakrabartyTest Resource Optimization for Multi-Site Testing of SOCs Under ATE Memory Depth Constraints.ITC1159-11682002Conference and Workshop Papersclosedconf/itc/IyengarGMC0210.1109/TEST.2002.1041874https://doi.org/10.1109/TEST.2002.1041874https://dblp.org/rec/conf/itc/IyengarGMC02URL#6294106Mark JagielaAn Open Architecture for Semiconductor Test: Enablers and Challenges.ITC12112002Conference and Workshop Papersclosedconf/itc/Jagiela0210.1109/TEST.2002.1041916https://doi.org/10.1109/TEST.2002.1041916https://dblp.org/rec/conf/itc/Jagiela02URL#6294107Vishal JainJohn A. WaicukauskiScan Test Data Volume Reduction in Multi-Clocked Designs with Safe Capture Technique.ITC148-1532002Conference and Workshop Papersclosedconf/itc/JainW0210.1109/TEST.2002.1041755https://doi.org/10.1109/TEST.2002.1041755https://dblp.org/rec/conf/itc/JainW02URL#6294108Jayasanker JayabalanJuraj PovazanecIntegration of SRAM Redundancy into Production Test.ITC187-1932002Conference and Workshop Papersclosedconf/itc/JayabalanP0210.1109/TEST.2002.1041760https://doi.org/10.1109/TEST.2002.1041760https://dblp.org/rec/conf/itc/JayabalanP02URL#6294109Zhigang JiangSandeep K. Gupta 0001An ATPG for Threshold Testing: Obtaining Acceptable Yield in Future Processes.ITC824-8332002Conference and Workshop Papersclosedconf/itc/JiangG0210.1109/TEST.2002.1041836https://doi.org/10.1109/TEST.2002.1041836https://dblp.org/rec/conf/itc/JiangG02URL#6294110John C. JohnsonTesting the Tester: Specification and Validation Approaches.ITC292002Conference and Workshop Papersclosedconf/itc/Johnson0210.1109/ITC.2002.10004https://doi.ieeecomputersociety.org/10.1109/ITC.2002.10004https://dblp.org/rec/conf/itc/Johnson02URL#6294111Don Douglas JosephsonThe Manic Depression of Microprocessor Debug.ITC657-6632002Conference and Workshop Papersclosedconf/itc/Josephson0210.1109/TEST.2002.1041817https://doi.org/10.1109/TEST.2002.1041817https://dblp.org/rec/conf/itc/Josephson02URL#6294112Alan KaftonWireless SOC Testing: Can RF Testing Costs Be Reduced?ITC1226-12272002Conference and Workshop Papersclosedconf/itc/Kafton0210.1109/TEST.2002.1041928https://doi.org/10.1109/TEST.2002.1041928https://dblp.org/rec/conf/itc/Kafton02URL#6294113Bozena KaminskaHomegrown Tools and Equipment versus EDA and ATE Vendors: The Future of Design to Test Product Lines.ITC232002Conference and Workshop Papersclosedconf/itc/Kaminska0210.1109/ITC.2002.10014https://doi.ieeecomputersociety.org/10.1109/ITC.2002.10014https://dblp.org/rec/conf/itc/Kaminska02URL#6294114Kenichi KataokaToshihiro ItohKatsuya OkumuraTadatomo SugaLow-Contact-Force Probing on Copper Electrodes.ITC424-4292002Conference and Workshop Papersclosedconf/itc/KataokaIOS0210.1109/TEST.2002.1041791https://doi.org/10.1109/TEST.2002.1041791https://dblp.org/rec/conf/itc/KataokaIOS02URL#6294115David C. KeezerChallenges and Solutions for Multi-Gigahertz Testing.ITC12302002Conference and Workshop Papersclosedconf/itc/Keezer0210.1109/TEST.2002.1041931https://doi.org/10.1109/TEST.2002.1041931https://dblp.org/rec/conf/itc/Keezer02URL#6294116Sandeep KoranneVikram IyengarOn the Use of k-tuples for SoC Test Schedule Representation.ITC539-5482002Conference and Workshop Papersclosedconf/itc/KoranneI0210.1109/TEST.2002.1041804https://doi.org/10.1109/TEST.2002.1041804https://dblp.org/rec/conf/itc/KoranneI02URL#6294117Gunter KramplMarco RonaHermann TauberTest Setup Simulation - A High-Performance VHDL-Based Virtual Test Solution Meeting Industrial Requirements.ITC870-8782002Conference and Workshop Papersclosedconf/itc/KramplRT0210.1109/TEST.2002.1041841https://doi.org/10.1109/TEST.2002.1041841https://dblp.org/rec/conf/itc/KramplRT02URL#6294118C. V. KrishnaNur A. ToubaReducing Test Dat Volume Using LFSR Reseeding with Seed Compression.ITC321-3302002Conference and Workshop Papersclosedconf/itc/KrishnaT0210.1109/TEST.2002.1041775https://doi.org/10.1109/TEST.2002.1041775https://dblp.org/rec/conf/itc/KrishnaT02URL#6294119Adam KristofImproved Digital I/O Ports Enhance Testability of Interconnections.ITC763-7722002Conference and Workshop Papersclosedconf/itc/Kristof0210.1109/TEST.2002.1041829https://doi.org/10.1109/TEST.2002.1041829https://dblp.org/rec/conf/itc/Kristof02URL#6294120Bram KrusemanStefan van den OetelaarJosep Rius 0001Comparison of IDDQ Testing and Very-Low Voltage Testing.ITC964-9732002Conference and Workshop Papersclosedconf/itc/KrusemanOR0210.1109/TEST.2002.1041852https://doi.org/10.1109/TEST.2002.1041852https://dblp.org/rec/conf/itc/KrusemanOR02URL#6294121David B. LavoIsmed HartantoTracy LarrabeeMultiplets, Models, and the Search for Meaning: Improving Per-Test Fault Diagnosis.ITC250-2592002Conference and Workshop Papersclosedconf/itc/LavoHL0210.1109/TEST.2002.1041767https://doi.org/10.1109/TEST.2002.1041767https://dblp.org/rec/conf/itc/LavoHL02URL#6294122Mike P. LiJan B. WilstrupOn the Accuracy of Jitter Separation from Bit Error Rate Function.ITC710-7162002Conference and Workshop Papersclosedconf/itc/LiW0210.1109/TEST.2002.1041823https://doi.org/10.1109/TEST.2002.1041823https://dblp.org/rec/conf/itc/LiW02URL#6294123Jing-Jia LiouLi-C. WangKwang-Ting ChengJennifer DworakM. Ray MercerRohit KapurThomas W. WilliamsAnalysis of Delay Test Effectiveness with a Multiple-Clock Scheme.ITC407-4162002Conference and Workshop Papersclosedconf/itc/LiouWCDMKW0210.1109/TEST.2002.1041786https://doi.org/10.1109/TEST.2002.1041786https://dblp.org/rec/conf/itc/LiouWCDMKW02URL#6294124Timothe LittSupport for Debugging in the Alpha 21364 Microprocessor.ITC584-5892002Conference and Workshop Papersclosedconf/itc/Litt0210.1109/TEST.2002.1041809https://doi.org/10.1109/TEST.2002.1041809https://dblp.org/rec/conf/itc/Litt02URL#6294125Xiao Liu 0010Michael S. HsiaoSreejit ChakravartyPaul J. ThadikaranTechniques to Reduce Data Volume and Application Time for Transition Test.ITC983-9922002Conference and Workshop Papersclosedconf/itc/LiuHCT0210.1109/TEST.2002.1041854https://doi.org/10.1109/TEST.2002.1041854https://dblp.org/rec/conf/itc/LiuHCT02URL#6294126Jiang Brandon LiuAndreas G. VenerisHiroshi TakahashiIncremental Diagnosis of Multiple Open-Interconnects.ITC1085-10922002Conference and Workshop Papersclosedconf/itc/LiuVT0210.1109/TEST.2002.1041865https://doi.org/10.1109/TEST.2002.1041865https://dblp.org/rec/conf/itc/LiuVT02URL#6294127Monica Lobetti BodoniPanel: "Board Test and ITC: What Does the Future Hold?".ITC12392002Conference and Workshop Papersclosedconf/itc/Lobetti-Bodoni0210.1109/TEST.2002.1041940https://doi.org/10.1109/TEST.2002.1041940https://dblp.org/rec/conf/itc/Lobetti-Bodoni02URL#6294128Kevin M. MacKayTesting Wireless Local Area Network Transceiver ICs at 5 GHz.ITC1146-11502002Conference and Workshop Papersclosedconf/itc/MacKay0210.1109/TEST.2002.1041872https://doi.org/10.1109/TEST.2002.1041872https://dblp.org/rec/conf/itc/MacKay02URL#6294129Robert MadgeB. H. GohV. RajagopalanC. MacchiettoW. Robert DaaschChris SchuermyerC. TaylorDavid TurnerScreening MinVDD Outliers Using Feed-Forward Voltage Testing.ITC673-6822002Conference and Workshop Papersclosedconf/itc/MadgeGRMDSTT0210.1109/TEST.2002.1041819https://doi.org/10.1109/TEST.2002.1041819https://dblp.org/rec/conf/itc/MadgeGRMDSTT02URL#6294130Rajneesh MahajanRamesh GovindarajuluJames R. ArmstrongF. Gail GrayA Multi-Language Goal-Tree Based Functional Test Planning System.ITC472-4812002Conference and Workshop Papersclosedconf/itc/MahajanGAG0210.1109/TEST.2002.1041797https://doi.org/10.1109/TEST.2002.1041797https://dblp.org/rec/conf/itc/MahajanGAG02URL#6294131Jean-Pascal MalletHigh Current DPS Architecture for Sort Test Challenge.ITC913-9222002Conference and Workshop Papersclosedconf/itc/Mallet0210.1109/TEST.2002.1041846https://doi.org/10.1109/TEST.2002.1041846https://dblp.org/rec/conf/itc/Mallet02URL#6294132Erik Jan MarinissenVikram IyengarKrishnendu ChakrabartyA Set of Benchmarks fo Modular Testing of SOCs.ITC519-5282002Conference and Workshop Papersclosedconf/itc/MarinissenIC0210.1109/TEST.2002.1041802https://doi.org/10.1109/TEST.2002.1041802https://dblp.org/rec/conf/itc/MarinissenIC02URL#6294133Gregory A. MastonConsiderations for STIL Data Application.ITC290-2962002Conference and Workshop Papersclosedconf/itc/Maston0210.1109/TEST.2002.1041771https://doi.org/10.1109/TEST.2002.1041771https://dblp.org/rec/conf/itc/Maston02URL#6294134Peter C. MaxwellThe Heisenberg Uncertainty of Test.ITC132002Conference and Workshop Papersclosedconf/itc/Maxwell0210.1109/ITC.2002.10002https://doi.ieeecomputersociety.org/10.1109/ITC.2002.10002https://dblp.org/rec/conf/itc/Maxwell02URL#6294135Peter C. MaxwellWafer/Package Test Mix for Optimal Defect Detection.ITC1050-10552002Conference and Workshop Papersclosedconf/itc/Maxwell02a10.1109/TEST.2002.1041861https://doi.org/10.1109/TEST.2002.1041861https://dblp.org/rec/conf/itc/Maxwell02aURL#6294136Mike MayberryJohn JohnsonNavid ShahriariMike TrippRealizing the Benefits of Structural Test for Intel Microprocessors.ITC456-4632002Conference and Workshop Papersclosedconf/itc/MayberryJST0210.1109/TEST.2002.1041795https://doi.org/10.1109/TEST.2002.1041795https://dblp.org/rec/conf/itc/MayberryJST02URL#6294137David E. McFeelyThe Process and Challenges of a High-Speed DUT Board Project.ITC565-5732002Conference and Workshop Papersclosedconf/itc/McFeely0210.1109/TEST.2002.1041807https://doi.org/10.1109/TEST.2002.1041807https://dblp.org/rec/conf/itc/McFeely02URL#6294138Teresa L. McLaurinTAPS All Over My Chips.ITC1193-11942002Conference and Workshop Papersclosedconf/itc/McLaurin0210.1109/ITC.2002.10020https://doi.ieeecomputersociety.org/10.1109/ITC.2002.10020https://dblp.org/rec/conf/itc/McLaurin02URL#6294139Cecilia MetraStefano Di FrancescantonioT. M. MakClock Faults? Impact on Manufacturing Testing and Their Possible Detection Through On-Line Testing.ITC100-1092002Conference and Workshop Papersclosedconf/itc/MetraFM0210.1109/TEST.2002.1041750https://doi.org/10.1109/TEST.2002.1041750https://dblp.org/rec/conf/itc/MetraFM02URL#6294140Liviu MicleaSzilárd EnyediAlfredo BensoItelligent Agents and BIST/BISR - Working Together in Distributed Systems.ITC940-9462002Conference and Workshop Papersclosedconf/itc/MicleaSB0210.1109/TEST.2002.1041849https://doi.org/10.1109/TEST.2002.1041849https://dblp.org/rec/conf/itc/MicleaSB02URL#6294141Subhasish MitraKee Sup KimX-Compact: An Efficient Response Compaction Technique for Test Cost Reduction.ITC311-3202002Conference and Workshop Papersclosedconf/itc/MitraK0210.1109/TEST.2002.1041774https://doi.org/10.1109/TEST.2002.1041774https://dblp.org/rec/conf/itc/MitraK02URL#6294142Peter MuhmenthalerOutsourcing Test without Standards?ITC1217-12182002Conference and Workshop Papersclosedconf/itc/Muhmenthaler0210.1109/TEST.2002.1041921https://doi.org/10.1109/TEST.2002.1041921https://dblp.org/rec/conf/itc/Muhmenthaler02URL#6294143Fidel MuradaliThe Impact of Outsourcing on Test.ITC12162002Conference and Workshop Papersclosedconf/itc/Muradali0210.1109/TEST.2002.1041920https://doi.org/10.1109/TEST.2002.1041920https://dblp.org/rec/conf/itc/Muradali02URL#6294144Mohsen NahviAndré IvanovResve A. SalehDedicated Autonomous Scan-Based Testing (DAST) for Embedded Cores.ITC1176-11842002Conference and Workshop Papersclosedconf/itc/NahviIS0210.1109/TEST.2002.1041876https://doi.org/10.1109/TEST.2002.1041876https://dblp.org/rec/conf/itc/NahviIS02URL#6294145Shahin NazarianHang HuangSuriyaprakash NatarajanSandeep K. Gupta 0001Melvin A. BreuerXIDEN: Crosstalk Target Identification Framework.ITC365-3742002Conference and Workshop Papersclosedconf/itc/NazarianHNGB0210.1109/TEST.2002.1041780https://doi.org/10.1109/TEST.2002.1041780https://dblp.org/rec/conf/itc/NazarianHNGB02URL#6294146Phil NighScan-Based Testing: The Only Practical Solution for Testing ASIC/Consumer Products.ITC11982002Conference and Workshop Papersclosedconf/itc/Nigh0210.1109/TEST.2002.1041905https://doi.org/10.1109/TEST.2002.1041905https://dblp.org/rec/conf/itc/Nigh02URL#6294147Steven F. OaklandTAPs All Over My Chips.ITC11922002Conference and Workshop Papersclosedconf/itc/Oakland0210.1109/TEST.2002.1041899https://doi.org/10.1109/TEST.2002.1041899https://dblp.org/rec/conf/itc/Oakland02URL#6294148Hideo OkawaraFrequency/Phase Movement Analy i by Orthogonal Demodulation.ITC110-1192002Conference and Workshop Papersclosedconf/itc/Okawara0210.1109/TEST.2002.1041751https://doi.org/10.1109/TEST.2002.1041751https://dblp.org/rec/conf/itc/Okawara02URL#6294149Toshiyuki OkayasuMasakatsu SudaKazuhiro YamamotoCMOS Circuit Technology for Precise GHz Timing Generator.ITC894-9022002Conference and Workshop Papersclosedconf/itc/OkayasuSY0210.1109/TEST.2002.1041844https://doi.org/10.1109/TEST.2002.1041844https://dblp.org/rec/conf/itc/OkayasuSY02URL#6294150Paul OkinoTest Time Impact of Redundancy Repair in Embedded Flash Memory.ITC12202002Conference and Workshop Papersclosedconf/itc/Okino0210.1109/TEST.2002.1041923https://doi.org/10.1109/TEST.2002.1041923https://dblp.org/rec/conf/itc/Okino02URL#6294151Kenneth P. ParkerBoard Test Is NOT Mature.ITC12382002Conference and Workshop Papersclosedconf/itc/Parker0210.1109/TEST.2002.1041939https://doi.org/10.1109/TEST.2002.1041939https://dblp.org/rec/conf/itc/Parker02URL#6294152Ganapathy ParthasarathyMadhu K. IyerTao Feng 0012Li-C. WangKwang-Ting ChengMagdy S. AbadirCombining ATPG and Symbolic Simulation for Efficient Validation of Embedded Array Systems.ITC203-2122002Conference and Workshop Papersclosedconf/itc/ParthasarathyIFWCA0210.1109/TEST.2002.1041762https://doi.org/10.1109/TEST.2002.1041762https://dblp.org/rec/conf/itc/ParthasarathyIFWCA02URL#6294153Ishwar ParulkarThomas A. ZiajaRajesh PendurkarAnand D'SouzaAmitava MajumdarA Scalable, Low Cost Design-for-Test Architecture for UltraSPARCTM Chip Multi-Processors.ITC726-7352002Conference and Workshop Papersclosedconf/itc/ParulkarZPDM0210.1109/TEST.2002.1041825https://doi.org/10.1109/TEST.2002.1041825https://dblp.org/rec/conf/itc/ParulkarZPDM02URL#6294154Praveen ParvathalaKaila ManeparambilWilliam LindsayFRITS - A Microprocessor Functional BIST Method.ITC590-5982002Conference and Workshop Papersclosedconf/itc/ParvathalaML0210.1109/TEST.2002.1041810https://doi.org/10.1109/TEST.2002.1041810https://dblp.org/rec/conf/itc/ParvathalaML02URL#6294155Bipul Chandra PaulKaushik Roy 0001Testing CrossTalk Induced Delay Faults in Static CMOS Circuits Through Dynamic Timing Analysis.ITC384-3902002Conference and Workshop Papersclosedconf/itc/PaulR0210.1109/TEST.2002.1041782https://doi.org/10.1109/TEST.2002.1041782https://dblp.org/rec/conf/itc/PaulR02URL#6294156Sergio M. PerezThe Consequences of an Open ATE Architecture.ITC12102002Conference and Workshop Papersclosedconf/itc/Perez0210.1109/TEST.2002.1041915https://doi.org/10.1109/TEST.2002.1041915https://dblp.org/rec/conf/itc/Perez02URL#6294157Guy PetersonVerification of Device Interface Hardware Interconnections Prior to the Start of Testing.ITC297-3002002Conference and Workshop Papersclosedconf/itc/Peterson0210.1109/TEST.2002.1041772https://doi.org/10.1109/TEST.2002.1041772https://dblp.org/rec/conf/itc/Peterson02URL#6294158Jean-Michel PortalL. ForliHassen AzizaDidier NéeAn Automated Methodology to Diagnose Geometric Defect in the EEPROM Cell.ITC31-362002Conference and Workshop Papersclosedconf/itc/PortalFAN0210.1109/TEST.2002.1041742https://doi.org/10.1109/TEST.2002.1041742https://dblp.org/rec/conf/itc/PortalFAN02URL#6294159A. V. S. S. PrasadVishwani D. AgrawalMadhusudan V. AtreA New Algorithm for Global Fault Collapsing into Equivalence and Dominance Sets.ITC391-3972002Conference and Workshop Papersclosedconf/itc/PrasadAA0210.1109/TEST.2002.1041783https://doi.org/10.1109/TEST.2002.1041783https://dblp.org/rec/conf/itc/PrasadAA02URL#6294160Bill PriceThe Role of Test in a Highly Outsourced Business Model.ITC12142002Conference and Workshop Papersclosedconf/itc/Price0210.1109/TEST.2002.1041918https://doi.org/10.1109/TEST.2002.1041918https://dblp.org/rec/conf/itc/Price02URL#6294161Carol PyronScan and BIST Can Almost Achieve Test Quality Levels.ITC11962002Conference and Workshop Papersclosedconf/itc/Pyron0210.1109/TEST.2002.1041903https://doi.org/10.1109/TEST.2002.1041903https://dblp.org/rec/conf/itc/Pyron02URL#6294162Carol PyronRekha BangaloreDawit BeleteJason GoertzAshutosh RazdanDenise YoungerSilicon Symptoms to Solutions: Applying Design for Debug Techniques.ITC664-6722002Conference and Workshop Papersclosedconf/itc/PyronBBGRY0210.1109/TEST.2002.1041818https://doi.org/10.1109/TEST.2002.1041818https://dblp.org/rec/conf/itc/PyronBBGRY02URL#6294163Minh QuachTuan PhamTim FigalBob KopitzkePete O'NeillWafer-Level Defect-Based Testing Using Enhanced Voltage Stress and Statistical Test Data Evaluation.ITC683-6922002Conference and Workshop Papersclosedconf/itc/QuachPFKO0210.1109/TEST.2002.1041820https://doi.org/10.1109/TEST.2002.1041820https://dblp.org/rec/conf/itc/QuachPFKO02URL#6294164Janusz RajskiJerzy TyszerMark KassabNilanjan Mukherjee 0001Rob ThompsonKun-Han TsaiAndre HertwigNagesh TamarapalliGrzegorz MrugalskiGeir EideJun QianEmbedded Deterministic Test for Low-Cost Manufacturing Test.ITC301-3102002Conference and Workshop Papersclosedconf/itc/RajkiTKMTTHTMEQ0210.1109/TEST.2002.1041773https://doi.org/10.1109/TEST.2002.1041773https://dblp.org/rec/conf/itc/RajkiTKMTTHTMEQ02URL#6294165Rochit RajsumanTesting The Tester.ITC272002Conference and Workshop Papersclosedconf/itc/Rajsuman0210.1109/ITC.2002.10016https://doi.ieeecomputersociety.org/10.1109/ITC.2002.10016https://dblp.org/rec/conf/itc/Rajsuman02URL#6294166Rochit RajsumanTesting The Tester.ITC302002Conference and Workshop Papersclosedconf/itc/Rajsuman02a10.1109/ITC.2002.10007https://doi.ieeecomputersociety.org/10.1109/ITC.2002.10007https://dblp.org/rec/conf/itc/Rajsuman02aURL#6294167Rochit RajsumanCan IC Test Learn from How a Tester is Tested.ITC11862002Conference and Workshop Papersclosedconf/itc/Rajsuman02b10.1109/TEST.2002.1041894https://doi.org/10.1109/TEST.2002.1041894https://dblp.org/rec/conf/itc/Rajsuman02bURL#6294168Sudhakar M. ReddyIrith PomeranzHuaxing TangSeiji KajiharaKozo KinoshitaOn Testing of Interconnect Open Defects in Combinational Logic Circuits with Stems of Large Fanout.ITC83-892002Conference and Workshop Papersclosedconf/itc/ReddyPTKK0210.1109/TEST.2002.1041748https://doi.org/10.1109/TEST.2002.1041748https://dblp.org/rec/conf/itc/ReddyPTKK02URL#6294169Gordon W. RobertsMixed-Signal BIST: Fact or Fiction.ITC12042002Conference and Workshop Papersclosedconf/itc/Roberts0210.1109/TEST.2002.1041910https://doi.org/10.1109/TEST.2002.1041910https://dblp.org/rec/conf/itc/Roberts02URL#6294170Gordon D. RobinsonBoard Test: Wanted Dead or Alive.ITC12362002Conference and Workshop Papersclosedconf/itc/Robinson0210.1109/TEST.2002.1041937https://doi.org/10.1109/TEST.2002.1041937https://dblp.org/rec/conf/itc/Robinson02URL#6294171Paul D. RoddyIs an Open Architecture Tester Really Achievable?ITC12092002Conference and Workshop Papersclosedconf/itc/Roddy0210.1109/TEST.2002.1041914https://doi.org/10.1109/TEST.2002.1041914https://dblp.org/rec/conf/itc/Roddy02URL#6294172Aubin RoyStephen K. SunterAlessandra FudoliDavide AppelloHigh Accuracy Stimulus Generation for A/D Converter BIST.ITC1031-10392002Conference and Workshop Papersclosedconf/itc/RoySFA0210.1109/TEST.2002.1041859https://doi.org/10.1109/TEST.2002.1041859https://dblp.org/rec/conf/itc/RoySFA02URL#6294173Manoj SachdevMulti-Gigahertz Digital Test Challenges and Techniques.ITC12312002Conference and Workshop Papersclosedconf/itc/Sachdev0210.1109/TEST.2002.1041932https://doi.org/10.1109/TEST.2002.1041932https://dblp.org/rec/conf/itc/Sachdev02URL#6294174Marcelino B. SantosIsabel C. TeixeiraJoão Paulo Teixeira 0001Salvador ManichRosa Rodríguez-MontañésJoan FiguerasRTL Level Preparation of High-Quality/Low-Energy/Low-Power BIST.ITC814-8232002Conference and Workshop Papersclosedconf/itc/SantosTTMRF0210.1109/TEST.2002.1041835https://doi.org/10.1109/TEST.2002.1041835https://dblp.org/rec/conf/itc/SantosTTMRF02URL#6294175Todd SargentPhysical Principles of Interface Design.ITC549-5542002Conference and Workshop Papersclosedconf/itc/Sargent0210.1109/TEST.2002.1041805https://doi.org/10.1109/TEST.2002.1041805https://dblp.org/rec/conf/itc/Sargent02URL#6294176Aditya D. SatheMichael L. BushnellVishwani D. AgrawalAnalog Macromodeling of Capacitive Coupling Faults in Digital Circuit Interconnects.ITC375-3832002Conference and Workshop Papersclosedconf/itc/SatheBA0210.1109/TEST.2002.1041781https://doi.org/10.1109/TEST.2002.1041781https://dblp.org/rec/conf/itc/SatheBA02URL#6294177Yasuo SatoIwao YamazakiHiroki YamanakaToshio IkedaMasahiro TakakuraA Persistent Diagnostic Technique for Unstable Defects.ITC242-2492002Conference and Workshop Papersclosedconf/itc/SatoYYIT0210.1109/TEST.2002.1041766https://doi.org/10.1109/TEST.2002.1041766https://dblp.org/rec/conf/itc/SatoYYIT02URL#6294178Jayashree SaxenaKenneth M. ButlerJohn GattR. RaghuramanSudheendra Phani KumarSupatra BasuDavid J. CampbellJohn BerechScan-Based Transition Fault Testing - Implementation and Low Cost Test Challenges .ITC1120-11292002Conference and Workshop Papersclosedconf/itc/SaxenaBGRKBCB0210.1109/TEST.2002.1041869https://doi.org/10.1109/TEST.2002.1041869https://dblp.org/rec/conf/itc/SaxenaBGRKBCB02URL#6294179Ulrich SchoettmerMulti-Gigahertz Digital Test Challenges and Techniques.ITC1233-12342002Conference and Workshop Papersclosedconf/itc/Schoettmer0210.1109/TEST.2002.1041934https://doi.org/10.1109/TEST.2002.1041934https://dblp.org/rec/conf/itc/Schoettmer02URL#6294180Paul F. ScrivensMission Possible? Open Architecture ATE.ITC12082002Conference and Workshop Papersclosedconf/itc/Scrivens0210.1109/ITC.2002.10019https://doi.ieeecomputersociety.org/10.1109/ITC.2002.10019https://dblp.org/rec/conf/itc/Scrivens02URL#6294181Jaume Segura 0001Ali KeshavarziJerry M. SodenCharles F. HawkinsParametric Failures in CMOS ICs - A Defect-Based Analysis.ITC90-992002Conference and Workshop Papersclosedconf/itc/SeguraKSH0210.1109/TEST.2002.1041749https://doi.org/10.1109/TEST.2002.1041749https://dblp.org/rec/conf/itc/SeguraKSH02URL#6294182Manish SharmaJanak H. PatelFinding a Small Set of Longest Testable Paths that Cover Every Gate.ITC974-9822002Conference and Workshop Papersclosedconf/itc/SharmaP0210.1109/TEST.2002.1041853https://doi.org/10.1109/TEST.2002.1041853https://dblp.org/rec/conf/itc/SharmaP02URL#6294183Masashi ShimanouchiNew Paradigm for Signal Paths in ATE Pin Electronics are Needed for Serialcom Device Testing.ITC903-9122002Conference and Workshop Papersclosedconf/itc/Shimanouchi0210.1109/TEST.2002.1041845https://doi.org/10.1109/TEST.2002.1041845https://dblp.org/rec/conf/itc/Shimanouchi02URL#6294184Riichiro ShirotaTest and Repair of Non-Volatile Commodity and Embedded Memories (NAND Flash Memory).ITC12212002Conference and Workshop Papersclosedconf/itc/Shirota0210.1109/TEST.2002.1041924https://doi.org/10.1109/TEST.2002.1041924https://dblp.org/rec/conf/itc/Shirota02URL#6294185Ozgur SinanogluIsmet BayraktarogluAlex OrailogluScan Power Reduction Through Test Data Transition Frequency Analysis.ITC844-8502002Conference and Workshop Papersclosedconf/itc/SinanogluBO0210.1109/TEST.2002.1041838https://doi.org/10.1109/TEST.2002.1041838https://dblp.org/rec/conf/itc/SinanogluBO02URL#6294186A. T. SivaramWilliam FritzscheToshitaka KoshiNam LaiDUT Capture Using Simultaneous Logic Acquisition.ITC280-2892002Conference and Workshop Papersclosedconf/itc/SivaramFKL0210.1109/TEST.2002.1041770https://doi.org/10.1109/TEST.2002.1041770https://dblp.org/rec/conf/itc/SivaramFKL02URL#6294187A. T. SivaramDaniel FanA. YiinEfficient Embedded Memory Testing with APG.ITC47-542002Conference and Workshop Papersclosedconf/itc/SivaramFY0210.1109/TEST.2002.1041744https://doi.org/10.1109/TEST.2002.1041744https://dblp.org/rec/conf/itc/SivaramFY02URL#6294188Mustapha SlamaniTesting Highly Integrated Wireless Circuits and Systems with Low Cost Tester: How to Overcome the Challenge?ITC12252002Conference and Workshop Papersclosedconf/itc/Slamani0210.1109/TEST.2002.1041927https://doi.org/10.1109/TEST.2002.1041927https://dblp.org/rec/conf/itc/Slamani02URL#6294189Mani SomaWelela HaileselassieJessica YanRajesh RainaA Wavelet-Based Timing Parameter Extraction Method.ITC120-1282002Conference and Workshop Papersclosedconf/itc/SomaHYR0210.1109/TEST.2002.1041752https://doi.org/10.1109/TEST.2002.1041752https://dblp.org/rec/conf/itc/SomaHYR02URL#6294190Lee Y. SongMixed Signal BIST: Fact or Fiction.ITC12032002Conference and Workshop Papersclosedconf/itc/Song0210.1109/TEST.2002.1041909https://doi.org/10.1109/TEST.2002.1041909https://dblp.org/rec/conf/itc/Song02URL#6294191Gregory S. SpirakisHomegrown Tools and Equipment versus EDA and ATE Vendors: The Future of Design to Test Product Lines.ITC252002Conference and Workshop Papersclosedconf/itc/Spirakis0210.1109/ITC.2002.10000https://doi.ieeecomputersociety.org/10.1109/ITC.2002.10000https://dblp.org/rec/conf/itc/Spirakis02URL#6294192M. StancicLiquan FangM. H. H. WeusthofR. M. W. TijinkHans G. KerkhoffA New Test Generation Approach for Embedded Analogue Cores in SoC.ITC861-8692002Conference and Workshop Papersclosedconf/itc/StancicFWTK0210.1109/TEST.2002.1041840https://doi.org/10.1109/TEST.2002.1041840https://dblp.org/rec/conf/itc/StancicFWTK02URL#6294193Dave StangRamaswami DandapaniAn Implementation of IEEE 1149.1 to Avoid Timing Violations and Other Practical In-Compliance Improvements.ITC746-7542002Conference and Workshop Papersclosedconf/itc/StangD0210.1109/TEST.2002.1041827https://doi.org/10.1109/TEST.2002.1041827https://dblp.org/rec/conf/itc/StangD02URL#6294194Charles E. StroudJeremy NallMatthew LashinskyMiron AbramoviciBIST-Based Diagnosis of FPGA Interconnect.ITC618-6272002Conference and Workshop Papersclosedconf/itc/StroudNLA0210.1109/TEST.2002.1041813https://doi.org/10.1109/TEST.2002.1041813https://dblp.org/rec/conf/itc/StroudNLA02URL#6294195Stephen K. SunterIC Mixed-Signal BIST: Separating Facts from Fiction.ITC12052002Conference and Workshop Papersclosedconf/itc/Sunter0210.1109/TEST.2002.1041911https://doi.org/10.1109/TEST.2002.1041911https://dblp.org/rec/conf/itc/Sunter02URL#6294196Stephen K. SunterBenoit Nadeau-DostieComplete, Contactless I/O Testing - Reaching the Boundary in Minimizing Digital IC Testing Cost.ITC446-4552002Conference and Workshop Papersclosedconf/itc/SunterN0210.1109/TEST.2002.1041794https://doi.org/10.1109/TEST.2002.1041794https://dblp.org/rec/conf/itc/SunterN02URL#6294197Ahmed Rashid SyedR4X/D4X - Formatters for Flexible Test System Architecture.ITC885-8932002Conference and Workshop Papersclosedconf/itc/Syed0210.1109/TEST.2002.1041843https://doi.org/10.1109/TEST.2002.1041843https://dblp.org/rec/conf/itc/Syed02URL#6294198Sassan TabatabaeiAndré IvanovAn Embedded Core for Sub-Picosecond Timing Measurements.ITC129-1372002Conference and Workshop Papersclosedconf/itc/TabatabaeiI0210.1109/TEST.2002.1041753https://doi.org/10.1109/TEST.2002.1041753https://dblp.org/rec/conf/itc/TabatabaeiI02URL#6294199Mehdi Baradaran TahooriSubhasish MitraShahin ToutounchiEdward J. McCluskeyFault Grading FPGA Interconnect Test Configurations.ITC608-6172002Conference and Workshop Papersclosedconf/itc/TahooriMTM0210.1109/TEST.2002.1041812https://doi.org/10.1109/TEST.2002.1041812https://dblp.org/rec/conf/itc/TahooriMTM02URL#6294200Mohammad H. TehranipourMehrdad NouraniSignal Integrity Loss in SoC's Interconnects: A Diagnosis Approach Using Embedded Microprocessor.ITC1093-11022002Conference and Workshop Papersclosedconf/itc/TehranipourN0210.1109/TEST.2002.1041866https://doi.org/10.1109/TEST.2002.1041866https://dblp.org/rec/conf/itc/TehranipourN02URL#6294201Ramesh C. TekumallaScott Davidson 0001On Identifying Indistinguishable Path Delay Faults and Improving Diagnosis.ITC993-10022002Conference and Workshop Papersclosedconf/itc/TekumallaD0210.1109/TEST.2002.1041855https://doi.org/10.1109/TEST.2002.1041855https://dblp.org/rec/conf/itc/TekumallaD02URL#6294202Shigeki TomishimaHiroaki TanizakiMitsutaka NiiroMasanao MarutaHideto HidakaT. TadaKenji GamoA Variable Drivability (VD) Output Buffer for the System In a Package (SIP) and High Frequency Wafer Test.ITC170-1772002Conference and Workshop Papersclosedconf/itc/TomishimaTNMHTG0210.1109/TEST.2002.1041758https://doi.org/10.1109/TEST.2002.1041758https://dblp.org/rec/conf/itc/TomishimaTNMHTG02URL#6294203Shahin ToutounchiAndrew LaiFPGA Test and Coverage.ITC599-6072002Conference and Workshop Papersclosedconf/itc/ToutounchiL0210.1109/TEST.2002.1041811https://doi.org/10.1109/TEST.2002.1041811https://dblp.org/rec/conf/itc/ToutounchiL02URL#6294204Mike TrippOn-Die DFT Based Solutions are Sufficient for Testing Multi-GHz Interfaces in Manufacturing (and Are Also Key to Enabling Lower Cost ATE Platforms).ITC12322002Conference and Workshop Papersclosedconf/itc/Tripp0210.1109/TEST.2002.1041933https://doi.org/10.1109/TEST.2002.1041933https://dblp.org/rec/conf/itc/Tripp02URL#6294205Shigeo TsuchidaTest and Repair of Nonvolatile Commodity and Embedded Memories.ITC1223-12242002Conference and Workshop Papersclosedconf/itc/Tsuchida0210.1109/TEST.2002.1041926https://doi.org/10.1109/TEST.2002.1041926https://dblp.org/rec/conf/itc/Tsuchida02URL#6294206David TurnerDavid AbercrombieJames McNamesW. Robert DaaschRobert MadgeIsolating and Removing Sources of Variation in Test Data.ITC464-4712002Conference and Workshop Papersclosedconf/itc/TurnerAMDM0210.1109/TEST.2002.1041796https://doi.org/10.1109/TEST.2002.1041796https://dblp.org/rec/conf/itc/TurnerAMDM02URL#6294207Andreas G. VenerisMagdy S. AbadirMandana AmiriDesign Rewiring Using ATPG.ITC223-2322002Conference and Workshop Papersclosedconf/itc/VenerisAA0210.1109/TEST.2002.1041764https://doi.org/10.1109/TEST.2002.1041764https://dblp.org/rec/conf/itc/VenerisAA02URL#6294208Bart VermeulenTAPS All Over My Chips! So Now What Do I Do?ITC11902002Conference and Workshop Papersclosedconf/itc/Vermeulen0210.1109/TEST.2002.1041897https://doi.org/10.1109/TEST.2002.1041897https://dblp.org/rec/conf/itc/Vermeulen02URL#6294209Bart VermeulenTom WaayersSjaak BakkerEEE 1149.1-Compliant Access Architecture for Multiple Core Debug on Digital System Chips.ITC55-632002Conference and Workshop Papersclosedconf/itc/VermeulenWB0210.1109/TEST.2002.1041745https://doi.org/10.1109/TEST.2002.1041745https://dblp.org/rec/conf/itc/VermeulenWB02URL#6294210Bart VermeulenTom WaayersSandeep Kumar GoelCore-Based Scan Architecture for Silicon Debug.ITC638-6472002Conference and Workshop Papersclosedconf/itc/VermeulenWG0210.1109/TEST.2002.1041815https://doi.org/10.1109/TEST.2002.1041815https://dblp.org/rec/conf/itc/VermeulenWG02URL#6294211Anjali Kinra VijGood Scan = Good Quality Level? Well, It Depends ?ITC11952002Conference and Workshop Papersclosedconf/itc/Vij0210.1109/TEST.2002.1041902https://doi.org/10.1109/TEST.2002.1041902https://dblp.org/rec/conf/itc/Vij02URL#6294212Erik H. VolkerinkAjay KhocheSubhasish MitraPacket-Based Input Test Data Compression Techniques.ITC154-1632002Conference and Workshop Papersclosedconf/itc/VolkerinkKM0210.1109/TEST.2002.1041756https://doi.org/10.1109/TEST.2002.1041756https://dblp.org/rec/conf/itc/VolkerinkKM02URL#6294213Seongmoon WangGeneration of Low Power Dissipation and High Fault Coverage Patterns for Scan-Based BIST.ITC834-8432002Conference and Workshop Papersclosedconf/itc/Wang0210.1109/TEST.2002.1041837https://doi.org/10.1109/TEST.2002.1041837https://dblp.org/rec/conf/itc/Wang02URL#6294214Li-C. WangMagdy S. AbadirJuhong ZhuOn Testing High-Performance Custom Circuits without Explicit Testing of the Internal Faults.ITC398-4062002Conference and Workshop Papersclosedconf/itc/WangAZ0210.1109/TEST.2002.1041785https://doi.org/10.1109/TEST.2002.1041785https://dblp.org/rec/conf/itc/WangAZ02URL#6294215Thomas P. WarwickWhat a Device Interface Board Really Costs: An Evaluation of Technical Considerations for Testing Products Operating in the Gigabit Region.ITC555-5642002Conference and Workshop Papersclosedconf/itc/Warwick0210.1109/TEST.2002.1041806https://doi.org/10.1109/TEST.2002.1041806https://dblp.org/rec/conf/itc/Warwick02URL#6294216Carsten WegenerMichael Peter KennedyImplementation of Model-Based Testing for Medium to High-Resolution Nyquist-Rate ADCs.ITC851-8602002Conference and Workshop Papersclosedconf/itc/WegenerK0210.1109/TEST.2002.1041839https://doi.org/10.1109/TEST.2002.1041839https://dblp.org/rec/conf/itc/WegenerK02URL#6294217Burnell G. WestOpen ATE Architecture: Key Challenges.ITC1212-12132002Conference and Workshop Papersclosedconf/itc/West0210.1109/TEST.2002.1041917https://doi.org/10.1109/TEST.2002.1041917https://dblp.org/rec/conf/itc/West02URL#6294218Lee WhetselInevitable Use of TAP Domains in SOCs.ITC11912002Conference and Workshop Papersclosedconf/itc/Whetsel0210.1109/TEST.2002.1041898https://doi.org/10.1109/TEST.2002.1041898https://dblp.org/rec/conf/itc/Whetsel02URL#6294219David WilliamsTest Coverage Models for System Test?ITC11852002Conference and Workshop Papersclosedconf/itc/Williams0210.1109/TEST.2002.1041893https://doi.org/10.1109/TEST.2002.1041893https://dblp.org/rec/conf/itc/Williams02URL#6294220David WilliamsAnthony P. AmblerSystem Manufacturing Test Cost Model.ITC482-4902002Conference and Workshop Papersclosedconf/itc/WilliamsA0210.1109/TEST.2002.1041798https://doi.org/10.1109/TEST.2002.1041798https://dblp.org/rec/conf/itc/WilliamsA02URL#6294221Francis G. WolffChristos A. PapachristouMultiscan-Based Test Compression and Hardware Decompression Using LZ77.ITC331-3392002Conference and Workshop Papersclosedconf/itc/WolffP0210.1109/TEST.2002.1041776https://doi.org/10.1109/TEST.2002.1041776https://dblp.org/rec/conf/itc/WolffP02URL#6294222David M. WuTrouble With Scan.ITC1199-12002002Conference and Workshop Papersclosedconf/itc/Wu0210.1109/TEST.2002.1041906https://doi.org/10.1109/TEST.2002.1041906https://dblp.org/rec/conf/itc/Wu02URL#6294223Takahiro J. YamaguchiMulti-GHz interface devices should be tested using external test resources.ITC12292002Conference and Workshop Papersclosedconf/itc/Yamaguchi0210.1109/TEST.2002.1041930https://doi.org/10.1109/TEST.2002.1041930https://dblp.org/rec/conf/itc/Yamaguchi02URL#6294224Takahiro J. YamaguchiMani SomaMasahiro IshidaHirobumi MushaLouis MalarsieA New Method for Testing Jitter Tolerance of SerDes Devices Using Sinusoidal Jitter.ITC717-7252002Conference and Workshop Papersclosedconf/itc/YamaguchiSIMM0210.1109/TEST.2002.1041824https://doi.org/10.1109/TEST.2002.1041824https://dblp.org/rec/conf/itc/YamaguchiSIMM02URL#6294225Yi ZhaoLi ChenSujit DeyOn-Line Testing of Multi-Source Noise-Induced Errors on the Interconnects and Buses of System-on-Chips.ITC491-4992002Conference and Workshop Papersclosedconf/itc/ZhaoCD0210.1109/TEST.2002.1041799https://doi.org/10.1109/TEST.2002.1041799https://dblp.org/rec/conf/itc/ZhaoCD02URL#6294226Yervant ZorianEmbedded Memory Test and Repair: Infrastructure IP for SOC Yield.ITC340-3492002Conference and Workshop Papersclosedconf/itc/Zorian0210.1109/TEST.2002.1041777https://doi.org/10.1109/TEST.2002.1041777https://dblp.org/rec/conf/itc/Zorian02URL#6294227Alex d'ArbeloffManaging in the ATE Business - Postcards from the Past, Lessons for the Future.ITC122002Conference and Workshop Papersclosedconf/itc/dArbeloff0210.1109/ITC.2002.10001https://doi.ieeecomputersociety.org/10.1109/ITC.2002.10001https://dblp.org/rec/conf/itc/dArbeloff02URL#6294228Proceedings IEEE International Test Conference 2002, Baltimore, MD, USA, October 7-10, 2002IEEE Computer Society2002Editorshipconf/itc/2002https://ieeexplore.ieee.org/xpl/conhome/8073/proceedinghttps://dblp.org/rec/conf/itc/2002URL#6313076