:facetid:toc:\"db/conf/codes/codes2007.bht\"OK:facetid:toc:db/conf/codes/codes2007.bhtJaved AbsarMin Li 0001Praveen RaghavanAndy LambrechtsMurali JayapalaArnout VandecappelleFrancky CatthoorLocality optimization in wireless applications.CODES+ISSS125-1302007Conference and Workshop Papersclosedconf/codes/AbsarLRLJVC0710.1145/1289816.1289850https://doi.org/10.1145/1289816.1289850https://dblp.org/rec/conf/codes/AbsarLRLJVC07URL#5528080Benny AkessonKees GoossensMarkus RinghoferPredator: a predictable SDRAM memory controller.CODES+ISSS251-2562007Conference and Workshop Papersclosedconf/codes/AkessonGR0710.1145/1289816.1289877https://doi.org/10.1145/1289816.1289877https://dblp.org/rec/conf/codes/AkessonGR07URL#5528081Bruno C. AlbertiniSandro RigoGuido AraujoCristiano C. de AraújoEdna BarrosWillians AzevedoA computational reflection mechanism to support platform debugging in SystemC.CODES+ISSS81-862007Conference and Workshop Papersclosedconf/codes/AlbertiniRAABA0710.1145/1289816.1289838https://doi.org/10.1145/1289816.1289838https://dblp.org/rec/conf/codes/AlbertiniRAABA07URL#5528082Jude Angelo AmbroseRoshan G. RagelSri ParameswaranA smart random code injection to mask power analysis based side channel attacks.CODES+ISSS51-562007Conference and Workshop Papersclosedconf/codes/AmbroseRP0710.1145/1289816.1289832https://doi.org/10.1145/1289816.1289832https://dblp.org/rec/conf/codes/AmbroseRP07URL#5528083Michael A. BakerAviral ShrivastavaKaram S. ChathaSmart driver for power reduction in next generation bistable electrophoretic display technology.CODES+ISSS197-2022007Conference and Workshop Papersclosedconf/codes/BakerSC0710.1145/1289816.1289865https://doi.org/10.1145/1289816.1289865https://dblp.org/rec/conf/codes/BakerSC07URL#5528084Reinaldo A. BergamaschiIndira NairGero DittmannHiren D. PatelGeert JanssenNagu R. DhanwadaAlper BuyuktosunogluEmrah AcarGi-Joon NamDorothy KucarPradip BoseJohn A. DarringerGuoling HanPerformance modeling for early analysis of multi-core systems.CODES+ISSS209-2142007Conference and Workshop Papersclosedconf/codes/BergamaschiNDPJDBANKBDH0710.1145/1289816.1289868https://doi.org/10.1145/1289816.1289868https://dblp.org/rec/conf/codes/BergamaschiNDPJDBANKBDH07URL#5528085Alex BobrekJoAnn M. PaulDonald E. ThomasEvent-based re-training of statistical contention models for heterogeneous multiprocessors.CODES+ISSS69-742007Conference and Workshop Papersclosedconf/codes/BobrekPT0710.1145/1289816.1289836https://doi.org/10.1145/1289816.1289836https://dblp.org/rec/conf/codes/BobrekPT07URL#5528086Pramod ChandraiahRainer DömerPointer re-coding for creating definitive MPSoC models.CODES+ISSS33-382007Conference and Workshop Papersclosedconf/codes/ChandraiahD0710.1145/1289816.1289828https://doi.org/10.1145/1289816.1289828https://dblp.org/rec/conf/codes/ChandraiahD07URL#5528087Chen-Ling ChouRadu MarculescuIncremental run-time application mapping for homogeneous NoCs with multiple voltage levels.CODES+ISSS161-1662007Conference and Workshop Papersclosedconf/codes/ChouM0710.1145/1289816.1289857https://doi.org/10.1145/1289816.1289857https://dblp.org/rec/conf/codes/ChouM07URL#5528088Siddharth ChoudhuriTony GivargisPerformance improvement of block based NAND flash translation layer.CODES+ISSS257-2622007Conference and Workshop Papersclosedconf/codes/ChoudhuriG0710.1145/1289816.1289878https://doi.org/10.1145/1289816.1289878https://dblp.org/rec/conf/codes/ChoudhuriG07URL#5528089Rolf ErnstGernot SpiegelbergThomas Weber 0002Hermann KopetzAlberto L. Sangiovanni-VincentelliMarek JersakAutomotive networks: are new busses and gateways the answer or just another challenge?CODES+ISSS2632007Conference and Workshop Papersclosedconf/codes/ErnstSWKSJ0710.1145/1289816.1289880https://doi.org/10.1145/1289816.1289880https://dblp.org/rec/conf/codes/ErnstSWKSJ07URL#5528090Hermann EulComplexity challenges towards 4th generation communication solutions.CODES+ISSS1232007Conference and Workshop Papersclosedconf/codes/Eul0710.1145/1289816.1289817https://doi.org/10.1145/1289816.1289817https://dblp.org/rec/conf/codes/Eul07URL#5528091Heiko FalkSascha PlazarHenrik TheilingCompile-time decided instruction cache locking using worst-case execution paths.CODES+ISSS143-1482007Conference and Workshop Papersclosedconf/codes/FalkPT0710.1145/1289816.1289853https://doi.org/10.1145/1289816.1289853https://dblp.org/rec/conf/codes/FalkPT07URL#5528092Leandro FiorinGianluca PalermoSlobodan LukovicCristina SilvanoA data protection unit for NoC-based architectures.CODES+ISSS167-1722007Conference and Workshop Papersclosedconf/codes/FiorinPLS0710.1145/1289816.1289858https://doi.org/10.1145/1289816.1289858https://dblp.org/rec/conf/codes/FiorinPLS07URL#5528093Sascha GädtkeClaus TraulsenReinhard von HanxledenHW/SW co-design for Esterel processing.CODES+ISSS99-1042007Conference and Workshop Papersclosedconf/codes/GadtkeTH0710.1145/1289816.1289842https://doi.org/10.1145/1289816.1289842https://dblp.org/rec/conf/codes/GadtkeTH07URL#5528094Siddharth GargDiana MarculescuOn the impact of manufacturing process variations on the lifetime of sensor networks.CODES+ISSS203-2082007Conference and Workshop Papersclosedconf/codes/GargM0710.1145/1289816.1289866https://doi.org/10.1145/1289816.1289866https://dblp.org/rec/conf/codes/GargM07URL#5528095Wolfgang HaidLothar ThieleComplex task activation schemes in system level performance analysis.CODES+ISSS173-1782007Conference and Workshop Papersclosedconf/codes/HaidT0710.1145/1289816.1289860https://doi.org/10.1145/1289816.1289860https://dblp.org/rec/conf/codes/HaidT07URL#5528096Andreas Hansson 0001Martijn CoenenKees GoossensChannel trees: reducing latency by sharing time slots in time-multiplexed networks on chip.CODES+ISSS149-1542007Conference and Workshop Papersclosedconf/codes/HanssonCG0710.1145/1289816.1289855https://doi.org/10.1145/1289816.1289855https://dblp.org/rec/conf/codes/HanssonCG07URL#5528097Pao-Ann HsiungPin-Hsien LuChih-Wen LiuEnergy efficient co-scheduling in dynamically reconfigurable systems.CODES+ISSS87-922007Conference and Workshop Papersclosedconf/codes/HsiungLL0710.1145/1289816.1289840https://doi.org/10.1145/1289816.1289840https://dblp.org/rec/conf/codes/HsiungLL07URL#5528098Hiroaki InoueAkihisa IkenoTsuyoshi AbeJunji SakaiMasato EdahiroDynamic security domain scaling on symmetric multiprocessors for future high-end embedded systems.CODES+ISSS39-442007Conference and Workshop Papersclosedconf/codes/InoueIASE0710.1145/1289816.1289830https://doi.org/10.1145/1289816.1289830https://dblp.org/rec/conf/codes/InoueIASE07URL#5528099Hirofumi IwatoKeishi SakanushiYoshinori TakeuchiMasaharu ImaiA low power VLIW processor generation method by means of extracting non-redundant activation conditions.CODES+ISSS227-2322007Conference and Workshop Papersclosedconf/codes/IwatoSTI0710.1145/1289816.1289872https://doi.org/10.1145/1289816.1289872https://dblp.org/rec/conf/codes/IwatoSTI07URL#5528100Iyad Al KhatibDavide BertozziAxel JantschLuca BeniniPerformance analysis and design space exploration for high-end biomedical applications: challenges and solutions.CODES+ISSS217-2262007Conference and Workshop Papersclosedconf/codes/KhatibBJB0710.1145/1289816.1289870https://doi.org/10.1145/1289816.1289870https://dblp.org/rec/conf/codes/KhatibBJB07URL#5528101Seunghoon KimRobert P. DickRuss JosephPower deregulation: eliminating off-chip voltage regulation circuitry from embedded systems.CODES+ISSS105-1102007Conference and Workshop Papersclosedconf/codes/KimDJ0710.1145/1289816.1289844https://doi.org/10.1145/1289816.1289844https://dblp.org/rec/conf/codes/KimDJ07URL#5528102Wolfgang KlingaufRobert GünzelChristian SchröderEmbedded software development on top of transaction-level models.CODES+ISSS27-322007Conference and Workshop Papersclosedconf/codes/KlingaufGS0710.1145/1289816.1289827https://doi.org/10.1145/1289816.1289827https://dblp.org/rec/conf/codes/KlingaufGS07URL#5528103Stefan KraemerLei GaoJan WeinstockRainer LeupersGerd AscheidHeinrich MeyrHySim: a fast simulation framework for embedded software development.CODES+ISSS75-802007Conference and Workshop Papersclosedconf/codes/KraemerGWLAM0710.1145/1289816.1289837https://doi.org/10.1145/1289816.1289837https://dblp.org/rec/conf/codes/KraemerGWLAM07URL#5528104Simon Künzli 0001Arne HamannRolf ErnstLothar ThieleCombined approach to system level performance analysis of embedded systems.CODES+ISSS63-682007Conference and Workshop Papersclosedconf/codes/KunzliHET0710.1145/1289816.1289835https://doi.org/10.1145/1289816.1289835https://dblp.org/rec/conf/codes/KunzliHET07URL#5528105Glenn LearyKrishna MehtaKaram S. ChathaPerformance and resource optimization of NoC router architecture for master and slave IP cores.CODES+ISSS155-1602007Conference and Workshop Papersclosedconf/codes/LearyMC0710.1145/1289816.1289856https://doi.org/10.1145/1289816.1289856https://dblp.org/rec/conf/codes/LearyMC07URL#5528106Paul LokuciejewskiHeiko FalkMartin SchwarzerPeter MarwedelHenrik TheilingInfluence of procedure cloning on WCET prediction.CODES+ISSS137-1422007Conference and Workshop Papersclosedconf/codes/LokuciejewskiFSMT0710.1145/1289816.1289852https://doi.org/10.1145/1289816.1289852https://dblp.org/rec/conf/codes/LokuciejewskiFSMT07URL#5528107Radu MarculescuBorivoje NikolicAlberto L. Sangiovanni-VincentelliFresh air: the emerging landscape of design for networked embedded systems.CODES+ISSS1242007Conference and Workshop Papersclosedconf/codes/MarculescuNS0710.1145/1289816.1289848https://doi.org/10.1145/1289816.1289848https://dblp.org/rec/conf/codes/MarculescuNS07URL#5528108Brett H. MeyerDonald E. ThomasSimultaneous synthesis of buses, data mapping and memory allocation for MPSoC.CODES+ISSS3-82007Conference and Workshop Papersclosedconf/codes/MeyerT0710.1145/1289816.1289822https://doi.org/10.1145/1289816.1289822https://dblp.org/rec/conf/codes/MeyerT07URL#5528109Srinivasan MuraliAlmir MutapcicDavid AtienzaRajesh Gupta 0001Stephen P. BoydGiovanni De MicheliTemperature-aware processor frequency assignment for MPSoCs using convex optimization.CODES+ISSS111-1162007Conference and Workshop Papersclosedconf/codes/MuraliMAGBM0710.1145/1289816.1289845https://doi.org/10.1145/1289816.1289845https://dblp.org/rec/conf/codes/MuraliMAGBM07URL#5528110Walid A. NajjarCompiling code accelerators for FPGAs.CODES+ISSS22007Conference and Workshop Papersclosedconf/codes/Najjar0710.1145/1289816.1289820https://doi.org/10.1145/1289816.1289820https://dblp.org/rec/conf/codes/Najjar07URL#5528111A. C. H. NgJan-Willem WeijersMiguel GlasseeThomas SchusterBruno BougardLiesbet Van der PerreESL design and HW/SW co-verification of high-end software defined radio platforms.CODES+ISSS191-1962007Conference and Workshop Papersclosedconf/codes/NgWGSBP0710.1145/1289816.1289864https://doi.org/10.1145/1289816.1289864https://dblp.org/rec/conf/codes/NgWGSBP07URL#5528112Krutartha PatelSridevan ParameswaranSeng Lin SheeEnsuring secure program execution in multiprocessor embedded systems: a case study.CODES+ISSS57-622007Conference and Workshop Papersclosedconf/codes/PatelPS0710.1145/1289816.1289833https://doi.org/10.1145/1289816.1289833https://dblp.org/rec/conf/codes/PatelPS07URL#5528113Antoine PerrinFrank GhenassiaBridging gap between simulation and spreadsheet study.CODES+ISSS215-2162007Conference and Workshop Papersclosedconf/codes/PerrinG0710.1145/1289816.1289869https://doi.org/10.1145/1289816.1289869https://dblp.org/rec/conf/codes/PerrinG07URL#5528114Paul PopKåre Harbo PoulsenViacheslav IzosimovPetru ElesScheduling and voltage scaling for energy/reliability trade-offs in fault-tolerant time-triggered embedded systems.CODES+ISSS233-2382007Conference and Workshop Papersclosedconf/codes/PopPIE0710.1145/1289816.1289873https://doi.org/10.1145/1289816.1289873https://dblp.org/rec/conf/codes/PopPIE07URL#5528115Rodric M. RabbahBeyond gaming: programming the PLAYSTATION®3 cell architecture for cost-effective parallel processing.CODES+ISSS12007Conference and Workshop Papersclosedconf/codes/Rabbah0710.1145/1289816.1289819https://doi.org/10.1145/1289816.1289819https://dblp.org/rec/conf/codes/Rabbah07URL#5528116Razvan RacuLi Li 0027Rafik HeniaArne HamannRolf ErnstImproved response time analysis of tasks scheduled under preemptive Round-Robin.CODES+ISSS179-1842007Conference and Workshop Papersclosedconf/codes/RacuLHHE0710.1145/1289816.1289861https://doi.org/10.1145/1289816.1289861https://dblp.org/rec/conf/codes/RacuLHHE07URL#5528117Tarvo RaudvereIngo SanderAxel JantschSynchronization after design refinements with sensitive delay elements.CODES+ISSS21-262007Conference and Workshop Papersclosedconf/codes/RaudvereSJ0710.1145/1289816.1289826https://doi.org/10.1145/1289816.1289826https://dblp.org/rec/conf/codes/RaudvereSJ07URL#5528118Hanno ScharwächterJonghee M. YounRainer LeupersYunheung PaekGerd AscheidHeinrich MeyrA code-generator generator for multi-output instructions.CODES+ISSS131-1362007Conference and Workshop Papersclosedconf/codes/ScharwachterYLPAM0710.1145/1289816.1289851https://doi.org/10.1145/1289816.1289851https://dblp.org/rec/conf/codes/ScharwachterYLPAM07URL#5528119Greg StittFrank VahidThread warping: a framework for dynamic synthesis of thread accelerators.CODES+ISSS93-982007Conference and Workshop Papersclosedconf/codes/StittV0710.1145/1289816.1289841https://doi.org/10.1145/1289816.1289841https://dblp.org/rec/conf/codes/StittV07URL#5528120Chong SunLi ShangRobert P. DickThree-dimensional multiprocessor system-on-chip thermal optimization.CODES+ISSS117-1222007Conference and Workshop Papersclosedconf/codes/SunSD0710.1145/1289816.1289846https://doi.org/10.1145/1289816.1289846https://dblp.org/rec/conf/codes/SunSD07URL#5528121Mark Thompson 0001Hristo NikolovTodor P. StefanovAndy D. PimentelCagkan ErbasSimon PolstraEd F. DeprettereA framework for rapid system-level exploration, synthesis, and programming of multimedia MP-SoCs.CODES+ISSS9-142007Conference and Workshop Papersclosedconf/codes/ThompsonNSPEPD0710.1145/1289816.1289823https://doi.org/10.1145/1289816.1289823https://dblp.org/rec/conf/codes/ThompsonNSPEPD07URL#5528122Alexander ViehlMarkus SchwarzOliver Bringmann 0001Wolfgang RosenstielProbabilistic performance risk analysis at system-level.CODES+ISSS185-1902007Conference and Workshop Papersclosedconf/codes/ViehlSBR0710.1145/1289816.1289862https://doi.org/10.1145/1289816.1289862https://dblp.org/rec/conf/codes/ViehlSBR07URL#5528123Chengmo YangAlex OrailogluPredictable execution adaptivity through embedding dynamic reconfigurability into static MPSoC schedules.CODES+ISSS15-202007Conference and Workshop Papersclosedconf/codes/YangO0710.1145/1289816.1289824https://doi.org/10.1145/1289816.1289824https://dblp.org/rec/conf/codes/YangO07URL#5528124Chenjie YuPeter PetrovAggressive snoop reduction for synchronized producer-consumer communication in energy-efficient embedded multi-processors.CODES+ISSS245-2502007Conference and Workshop Papersclosedconf/codes/YuP0710.1145/1289816.1289876https://doi.org/10.1145/1289816.1289876https://dblp.org/rec/conf/codes/YuP07URL#5528125Pengyuan YuPatrick SchaumontSecure FPGA circuits using controlled placement and routing.CODES+ISSS45-502007Conference and Workshop Papersclosedconf/codes/YuS0710.1145/1289816.1289831https://doi.org/10.1145/1289816.1289831https://dblp.org/rec/conf/codes/YuS07URL#5528126Changyun ZhuZhenyu (Peter) GuRobert P. DickLi ShangReliable multiprocessor system-on-chip synthesis.CODES+ISSS239-2442007Conference and Workshop Papersclosedconf/codes/ZhuGDS0710.1145/1289816.1289874https://doi.org/10.1145/1289816.1289874https://dblp.org/rec/conf/codes/ZhuGDS07URL#5528127Soonhoi HaKiyoung ChoiNikil D. DuttJürgen TeichProceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2007, Salzburg, Austria, September 30 - October 3, 2007CODES+ISSSACM2007Editorshipconf/codes/200710.1145/1289816https://doi.org/10.1145/1289816https://dblp.org/rec/conf/codes/2007URL#5620715