:facetid:stream:\"streams/conf/mbmv\"OK:facetid:stream:streams/conf/mbmvMark DeutelPhilipp WollerChristopher MutschlerJürgen TeichEnergy-efficient Deployment of Deep Learning Applications on Cortex-M based Microcontrollers using Deep Compression.MBMV1-122023Conference and Workshop Papersclosedconf/mbmv/DeutelWMT23https://ieeexplore.ieee.org/document/10173060https://dblp.org/rec/conf/mbmv/DeutelWMT23URL#412450Iwan Feras FattohiChristian PrehoferFrank SlomkaWorst-Case Response Time Analysis of Earliest Deadline First in an Industrial Case Study.MBMV1-82023Conference and Workshop Papersclosedconf/mbmv/FattohiPS23https://ieeexplore.ieee.org/document/10173062https://dblp.org/rec/conf/mbmv/FattohiPS23URL#412451Lars LuchterhandtTom NelliusRobert BeckRainer DömerPascal KneuperWolfgang MuellerBabak SadiyeTowards a Rocket Chip Based Implementation of the RISC-V GPC Architecture.MBMV1-72023Conference and Workshop Papersclosedconf/mbmv/LuchterhandtNBD23https://ieeexplore.ieee.org/document/10173063https://dblp.org/rec/conf/mbmv/LuchterhandtNBD23URL#412452Julius RoobAnoop BhagyanathKlaus Schneider 0001Towards Buffers as a Scalable Alternative to Registers for Processor-Local Memory.MBMV1-122023Conference and Workshop Papersclosedconf/mbmv/RoobB023https://ieeexplore.ieee.org/document/10173059https://dblp.org/rec/conf/mbmv/RoobB023URL#412453Philipp SchmitzJohannes MuellerChristian Bartsch 0001Dominik StoffelWolfgang KunzUPEC-PN: Exhaustive constant time verification of low-level software using property checking.MBMV1-82023Conference and Workshop Papersclosedconf/mbmv/SchmitzMBSK23https://ieeexplore.ieee.org/document/10173064https://dblp.org/rec/conf/mbmv/SchmitzMBSK23URL#412454Johannes SchreinerVasundhara Raje GontiaSebastian PrebeckWolfgang EckerGenerator IP-reuse and Automated Infrastructure Generation for Model-based Full-Chip Generation.MBMV1-122023Conference and Workshop Papersclosedconf/mbmv/SchreinerGPE23https://ieeexplore.ieee.org/document/10173061https://dblp.org/rec/conf/mbmv/SchreinerGPE23URL#412455Methods and Description Languages for Modelling and Verification of Circuits and Systems, MBMV 2023, 26th Workshop, Freiburg, Germany, 23-24 March 2023MBMVVDE/IEEE2023Editorshipconf/mbmv/2023https://ieeexplore.ieee.org/xpl/conhome/10173057/proceedinghttps://dblp.org/rec/conf/mbmv/2023URL#461528Klaus Schneider 0001Anoop BhagyanathJulius RoobVirtual Buffers for Exposed Datapath Architectures.MBMV1-112022Conference and Workshop Papersclosedconf/mbmv/0001BR22https://ieeexplore.ieee.org/document/9788583https://dblp.org/rec/conf/mbmv/0001BR22URL#904424Christian Bartsch 0001Stephan WilhelmDaniel KästnerDominik StoffelWolfgang KunzCompositional Fault Propagation Analysis in Embedded Systems using Abstract Interpretation.MBMV1-42022Conference and Workshop Papersclosedconf/mbmv/BartschWKSK22https://ieeexplore.ieee.org/document/9788577https://dblp.org/rec/conf/mbmv/BartschWKSK22URL#904425Mehran GoliRolf DrechslerSimulation-based Verification of SystemC-based VPs at the ESL.MBMV1-42022Conference and Workshop Papersclosedconf/mbmv/GoliD22https://ieeexplore.ieee.org/document/9788580https://dblp.org/rec/conf/mbmv/GoliD22URL#904426Ming HuLeonore WintererRalf Wimmer 0001Diagnosing Partially Observable Markov Decision Processes.MBMV1-102022Conference and Workshop Papersclosedconf/mbmv/HuW022https://ieeexplore.ieee.org/document/9788584https://dblp.org/rec/conf/mbmv/HuW022URL#904427Alireza MahzoonRolf DrechslerPolynomial Formal Verification of Complex Multipliers.MBMV1-42022Conference and Workshop Papersclosedconf/mbmv/MahzoonD22https://ieeexplore.ieee.org/document/9788585https://dblp.org/rec/conf/mbmv/MahzoonD22URL#904428Lukas MentelKarsten ScheiblerTino TeigeDetection and Elimination of Constants to Strengthen k-Induction.MBMV1-102022Conference and Workshop Papersclosedconf/mbmv/MentelST22https://ieeexplore.ieee.org/document/9788578https://dblp.org/rec/conf/mbmv/MentelST22URL#904429Sebastian PrebeckSathya AshokMounika VaddeboinaKeerthikumara DevarajegowdaWolfgang EckerA Scalable, Configurable and Programmable Vector Dot-Product Unit for Edge AI.MBMV1-92022Conference and Workshop Papersclosedconf/mbmv/PrebeckAVDE22https://ieeexplore.ieee.org/document/9788581https://dblp.org/rec/conf/mbmv/PrebeckAVDE22URL#904430Omair RafiqueKlaus Schneider 0001Data-aware Global Scheduling of Dataflow Process Networks.MBMV1-92022Conference and Workshop Papersclosedconf/mbmv/Rafique022https://ieeexplore.ieee.org/document/9788582https://dblp.org/rec/conf/mbmv/Rafique022URL#904431Tobias SeufertChristoph Scholl 0001Arun ChandrasekharanSven ReimerTobias WelpMaking PROGRESS in Property Directed Reachability.MBMV1-22022Conference and Workshop Papersclosedconf/mbmv/Seufert0CRW22https://ieeexplore.ieee.org/document/9788579https://dblp.org/rec/conf/mbmv/Seufert0CRW22URL#904432Methods and Description Languages for Modelling and Verification of Circuits and Systems, MBMV 2022, 25th Workshop, Virtual Event, Germany, February 17-18, 2022MBMVVDE/IEEE2022Editorshipconf/mbmv/2022https://ieeexplore.ieee.org/xpl/conhome/9788575/proceedinghttps://dblp.org/rec/conf/mbmv/2022URL#954398Christoph Grimm 0001Frank WawrzikAlexander Louis-Ferdinand JungKonstantin LübeckSebastian PostJohannes KochOliver Bringmann 0001APPEL - AGILA ProPErty and Dependency Description Language.MBMV1-112021Conference and Workshop Papersclosedconf/mbmv/0001WJLPK021https://ieeexplore.ieee.org/document/9399724https://dblp.org/rec/conf/mbmv/0001WJLPK021URL#1371739Peer AdeltBastian KoppelmannWolfgang MuellerChristoph ScheyttRegister and Instruction Coverage Analysis for Different RISC-V ISA Modules.MBMV1-82021Conference and Workshop Papersclosedconf/mbmv/AdeltKMS21https://ieeexplore.ieee.org/document/9399723https://dblp.org/rec/conf/mbmv/AdeltKMS21URL#1371740Sallar Ahmadi-PourVladimir HerdtRolf DrechslerConstrained Random Verification for RISC-V: Overview, Evaluation and Discussion.MBMV1-82021Conference and Workshop Papersclosedconf/mbmv/Ahmadi-PourHD21https://ieeexplore.ieee.org/document/9399722https://dblp.org/rec/conf/mbmv/Ahmadi-PourHD21URL#1371741Max BrandAlbrecht MayerFrank SlomkaA Matter of Overhead - Response Time Analysis of Hard Real-Time Systems in Theory and Practice.MBMV1-72021Conference and Workshop Papersclosedconf/mbmv/BrandMS21https://ieeexplore.ieee.org/document/9399717https://dblp.org/rec/conf/mbmv/BrandMS21URL#1371742Zhao HanShahzaib QaziMichael WernerKeerthikumara DevarajegowdaWolfgang EckerOn Self-Verifying DSL Generation for Embedded Systems Automation.MBMV1-72021Conference and Workshop Papersclosedconf/mbmv/HanQWDE21https://ieeexplore.ieee.org/document/9399726https://dblp.org/rec/conf/mbmv/HanQWDE21URL#1371743Jie HouMartin RadetzkiComprehensive modeling and evaluation of Network-on-Chip performability.MBMV1-122021Conference and Workshop Papersclosedconf/mbmv/HouR21https://ieeexplore.ieee.org/document/9399719https://dblp.org/rec/conf/mbmv/HouR21URL#1371744Endri KajaNicolas Ojeda LeonMichael WernerBogdan-Andrei TabacaruKeerthikumara DevarajegowdaWolfgang EckerExtending Verilator to Enable Fault Simulation.MBMV1-62021Conference and Workshop Papersclosedconf/mbmv/KajaLWTDE21https://ieeexplore.ieee.org/document/9399725https://dblp.org/rec/conf/mbmv/KajaLWTDE21URL#1371745Martín LetrasJoachim FalkJürgen TeichDecision Tree-based Throughput Estimation to Accelerate Design Space Exploration for Multi-Core Applications.MBMV1-112021Conference and Workshop Papersclosedconf/mbmv/LetrasFT21https://ieeexplore.ieee.org/document/9399720https://dblp.org/rec/conf/mbmv/LetrasFT21URL#1371746Lukas MentelKarsten ScheiblerFelix WintererBernd Becker 0001Tino TeigeBenchmarking SMT Solvers on Automotive Code.MBMV1-102021Conference and Workshop Papersclosedconf/mbmv/MentelSW0T21https://ieeexplore.ieee.org/document/9399716https://dblp.org/rec/conf/mbmv/MentelSW0T21URL#1371747Lukas SteinerMatthias Jung 0001Norbert WehnExploration of DDR5 with the Open-Source Simulator DRAMSys.MBMV1-112021Conference and Workshop Papersclosedconf/mbmv/Steiner0W21https://ieeexplore.ieee.org/document/9399718https://dblp.org/rec/conf/mbmv/Steiner0W21URL#1371748Felix WintererTobias SeufertKarsten ScheiblerTino TeigeChritsoph SchollBernd Becker 0001ICP and IC3 with Stronger Generalization.MBMV1-122021Conference and Workshop Papersclosedconf/mbmv/WintererSSTS021https://ieeexplore.ieee.org/document/9399721https://dblp.org/rec/conf/mbmv/WintererSSTS021URL#1371749Methods and Description Languages for Modelling and Verification of Circuits and Systems, MBMV 2021, 24th Workshop, Virtual Event, Germany, March 18-19, 2021MBMVVDE/IEEE2021Editorshipconf/mbmv/2021https://ieeexplore.ieee.org/xpl/conhome/9399714/proceedinghttps://dblp.org/rec/conf/mbmv/2021URL#1419246Peer AdeltBastian KoppelmannWolfgang MuellerChristoph ScheyttA Scalable Platform for QEMU Based Fault Effect Analysis for RISC-V Hardware Architectures.MBMV1-82020Conference and Workshop Papersclosedconf/mbmv/AdeltKMS20https://ieeexplore.ieee.org/document/9094540https://dblp.org/rec/conf/mbmv/AdeltKMS20URL#1814517Jens FroemmerYara GowayedNico BannowWolfgang KunzChristoph Grimm 0001Klaus Schneider 0001Area Estimation Framework for Digital Hardware Design using Machine Learning.MBMV1-102020Conference and Workshop Papersclosedconf/mbmv/FroemmerGBK0020https://ieeexplore.ieee.org/document/9094535https://dblp.org/rec/conf/mbmv/FroemmerGBK0020URL#1814518Jakob HellerChristoph NiemannFranz PlockstiesChristian HaubeltDirk TimmermannTowards Virtual Prototyping of Electrically Active Implants Using SystemC-AMS.MBMV1-82020Conference and Workshop Papersclosedconf/mbmv/HellerNPHT20https://ieeexplore.ieee.org/document/9094537https://dblp.org/rec/conf/mbmv/HellerNPHT20URL#1814519Martin KöhlerFelix HasselwanderKlaus Schneider 0001Properties of Invariants and Induction Lemmata.MBMV1-102020Conference and Workshop Papersclosedconf/mbmv/KohlerH020https://ieeexplore.ieee.org/document/9094539https://dblp.org/rec/conf/mbmv/KohlerH020URL#1814520Daniel LuenemannMaher FakihKim GrüttnerCapturing Neural-Networks as Synchronous Dataflow Graphs.MBMV1-102020Conference and Workshop Papersclosedconf/mbmv/LuenemannFG20https://ieeexplore.ieee.org/document/9094536https://dblp.org/rec/conf/mbmv/LuenemannFG20URL#1814521Jens RudolfFlorian GrützmacherChristian HaubeltModel-based Analysis of Sensor-Subsystems Using Scenario-Aware Dataflow Graphs.MBMV1-92020Conference and Workshop Papersclosedconf/mbmv/RudolfGH20https://ieeexplore.ieee.org/document/9094538https://dblp.org/rec/conf/mbmv/RudolfGH20URL#181452223rd GMM/ITG/GI Workshop on Methods and Description Languages for Modelling and Verification of Circuits and Systems, MBMV 2020, Stuttgart, Germany, March 19-20, 2020MBMVVDE / IEEE2020Editorshipconf/mbmv/2020https://ieeexplore.ieee.org/xpl/conhome/9094533/proceeding?isnumber=9094534https://dblp.org/rec/conf/mbmv/2020URL#1861749Fin Hendrik BahnsenGörschwin FeyApproximation of Neural Networks for Verification.MBMV1-102019Conference and Workshop Papersclosedconf/mbmv/BahnsenF19https://ieeexplore.ieee.org/document/8727156/https://dblp.org/rec/conf/mbmv/BahnsenF19URL#2243021Keerthikumara DevarajegowdaWolfgang EckerWolfgang KunzHow to Keep 4-Eyes Principle in a Design and Property Generation Flow.MBMV1-62019Conference and Workshop Papersclosedconf/mbmv/DevarajegowdaEK19https://ieeexplore.ieee.org/document/8727160/https://dblp.org/rec/conf/mbmv/DevarajegowdaEK19URL#2243022Görschwin FeyRolf DrechslerSelf-Explaining Digital Systems - Some Technical Steps.MBMV1-82019Conference and Workshop Papersclosedconf/mbmv/FeyD19https://ieeexplore.ieee.org/document/8727157/https://dblp.org/rec/conf/mbmv/FeyD19URL#2243023Markus HedderichMarkus HeimbergerAxel KlekampSEMAS - System Engineering Methodology for Automated Systems The world described in layers.MBMV1-92019Conference and Workshop Papersclosedconf/mbmv/HedderichHK19https://ieeexplore.ieee.org/document/8727162/https://dblp.org/rec/conf/mbmv/HedderichHK19URL#2243024Iryna KmitinaNico BannowChristoph Grimm 0001Daniel ZielinskiCarna ZivkovicOptimization Framework for Hardware Design of Engine Control Units.MBMV1-82019Conference and Workshop Papersclosedconf/mbmv/KmitinaBGZZ19https://ieeexplore.ieee.org/document/8727158/https://dblp.org/rec/conf/mbmv/KmitinaBGZZ19URL#2243025Martin KöhlerKlaus Schneider 0001Inductive Proof Rules Beyond Safety Properties.MBMV1-92019Conference and Workshop Papersclosedconf/mbmv/KoehlerS19https://ieeexplore.ieee.org/document/8727155/https://dblp.org/rec/conf/mbmv/KoehlerS19URL#2243026Heinz RienerEleonora TestaWinston HaaswijkAlan MishchenkoLuca G. AmarùGiovanni De MicheliMathias SoekenLogic Optimization of Majority-Inverter Graphs.MBMV1-42019Conference and Workshop Papersclosedconf/mbmv/RienerTHMAMS19https://ieeexplore.ieee.org/document/8727159/https://dblp.org/rec/conf/mbmv/RienerTHMAMS19URL#2243027Jens RudolfManuel StrobelJoscha BenzChristian HaubeltMartin RadetzkiOliver Bringmann 0001Automated Sensor Firmware Development - Generation, Optimization, and Analysis.MBMV1-122019Conference and Workshop Papersclosedconf/mbmv/RudolfSBHRB19https://ieeexplore.ieee.org/document/8727161/https://dblp.org/rec/conf/mbmv/RudolfSBHRB19URL#2243028Michael Schwarz 0010Dominik StoffelWolfgang KunzACCESS: HW/SW-Co-Equivalence Checking for Firmware Optimization.MBMV1-42019Conference and Workshop Papersclosedconf/mbmv/SchwarzSK19https://ieeexplore.ieee.org/document/8727154/https://dblp.org/rec/conf/mbmv/SchwarzSK19URL#224302922nd Workshop Methods and Description Languages for Modelling and Verification of Circuits and Systems, MBMV 2019, Kaiserslautern, Germany, March 8-9, 2019.MBMVVDE Verlag2019Editorshipconf/mbmv/2019https://ieeexplore.ieee.org/servlet/opac?punumber=8727152https://dblp.org/rec/conf/mbmv/2019URL#2296469Timo FeldUwe WerkmannFrank SlomkaReal-Time Analysis of Distributed Systems including Tasks with Variable Rate-dependent Behavior.MBMV2018Conference and Workshop Papersclosedconf/mbmv/FeldWS18https://hdl.handle.net/10900/84298https://dblp.org/rec/conf/mbmv/FeldWS18URL#2632454Vladimir HerdtHoang M. LeDaniel GroßeRolf DrechslerTowards Automated Refinement of TLM Properties to RTL.MBMV2018Conference and Workshop Papersclosedconf/mbmv/HerdtLGD18https://hdl.handle.net/10900/84283https://dblp.org/rec/conf/mbmv/HerdtLGD18URL#2632455Florian HockVictor PollexChijun ShenTobias BundFrank SlomkaUpper Bound for Delay Densities.MBMV2018Conference and Workshop Papersclosedconf/mbmv/HockPSBS18https://hdl.handle.net/10900/84297https://dblp.org/rec/conf/mbmv/HockPSBS18URL#2632456Tripti JainKlaus Schneider 0001Routing Partial Permutations in General Interconnection Networks based on Radix Sorting.MBMV2018Conference and Workshop Papersclosedconf/mbmv/JainS18https://hdl.handle.net/10900/84278https://dblp.org/rec/conf/mbmv/JainS18URL#2632457Philipp S. KäsgenMarkus WeinhardtUsing Template Metaprogramming for Hardware Description.MBMV2018Conference and Workshop Papersclosedconf/mbmv/KasgenW18https://hdl.handle.net/10900/84299https://dblp.org/rec/conf/mbmv/KasgenW18URL#2632458Johannes MastStefan RädleJoachim GerlachModellbasierte Analyse und Multikriterien-Optimierung komplexer Systemszenarien unter Anwendung von Methoden der Künstlichen Intelligenz.MBMV2018Conference and Workshop Papersclosedconf/mbmv/MastRG18https://hdl.handle.net/10900/84287https://dblp.org/rec/conf/mbmv/MastRG18URL#2632459Kai NeubauerChristian HaubeltPhilipp WankoTorsten SchaubSystematic Test Case Instance Generation for the Assessment of System-level Design Space Exploration Approaches.MBMV2018Conference and Workshop Papersclosedconf/mbmv/NeubauerHWS18https://hdl.handle.net/10900/84295https://dblp.org/rec/conf/mbmv/NeubauerHWS18URL#2632460Valentina RichthammerMichael GlaßOn Search-Space Restriction for Design Space Exploration of Multi-/Many-Core Systems.MBMV2018Conference and Workshop Papersclosedconf/mbmv/RichthammerG18https://hdl.handle.net/10900/84285https://dblp.org/rec/conf/mbmv/RichthammerG18URL#2632461Marcel RießCedrik BockFrank SlomkaGeneric Reusable Hardware/Software Co-Design Implementation of a Complete FH-FSK Modem for Robust Multi-User Acoustic Underwater Communication and System Validation on a FPGA.MBMV2018Conference and Workshop Papersclosedconf/mbmv/RiessBS18https://hdl.handle.net/10900/84284https://dblp.org/rec/conf/mbmv/RiessBS18URL#2632462Patrick SittelThomas SchönwälderMartin KummPeter ZipfScaLP: A Light-Weighted (MI)LP-Library.MBMV2018Conference and Workshop Papersclosedconf/mbmv/SittelSKZ18https://hdl.handle.net/10900/84296https://dblp.org/rec/conf/mbmv/SittelSKZ18URL#2632463Ralf Wimmer 0001Andreas KarrenbauerRuben BeckerChristoph Scholl 0001Bernd Becker 0001From DQBF to QBF by Dependency Elimination.MBMV2018Conference and Workshop Papersclosedconf/mbmv/WimmerKBSB18https://hdl.handle.net/10900/84276https://dblp.org/rec/conf/mbmv/WimmerKBSB18URL#2632464Leonore WintererSebastian JungesRalf Wimmer 0001Nils Jansen 0001Ufuk TopcuJoost-Pieter KatoenBernd Becker 0001Abstraktions-basierte Verifikation von POMDPs im Motion-Planning-Kontext.MBMV2018Conference and Workshop Papersclosedconf/mbmv/WintererJWJTKB18https://hdl.handle.net/10900/84282https://dblp.org/rec/conf/mbmv/WintererJWJTKB18URL#2632465Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, MBMV 2018, Tübingen, Germany, February 8-9, 2018.MBMVUniversität Tübingen2018Editorshipconf/mbmv/2018https://hdl.handle.net/10900/81790https://dblp.org/rec/conf/mbmv/2018URL#2683945Hananeh AlieeAbbas BanaiyanMofradMichael GlaßJürgen TeichNikil D. DuttRedundancy-aware Design Space Exploration for Memory Reliability in Many-cores.MBMV1-122017Conference and Workshop Papersunavailableconf/mbmv/AlieeBGTD17https://dblp.org/rec/conf/mbmv/AlieeBGTD17URL#2986814Hussam AmrouchJörg HenkelContaining Guardbands: From the Macro to Micro Time Domain.MBMV13-142017Conference and Workshop Papersunavailableconf/mbmv/AmrouchH17https://dblp.org/rec/conf/mbmv/AmrouchH17URL#2986815Benjamin BeichlerMichael RethfeldtHannes RaddatzBjörn KonieczekPeter DanielisChristian HaubeltDirk TimmermannOptimization of a novel WLAN Simulation Framework for Prototyping Network Applications and Protocols.MBMV15-262017Conference and Workshop Papersunavailableconf/mbmv/BeichlerRRKDHT17https://dblp.org/rec/conf/mbmv/BeichlerRRKDHT17URL#2986816Saman FröhlichDaniel GroßeRolf DrechslerExakte BDD Minimierung mit Fehlerschranke für den Einsatz im Approximate Computing.MBMV27-382017Conference and Workshop Papersunavailableconf/mbmv/FrohlichGD17https://dblp.org/rec/conf/mbmv/FrohlichGD17URL#2986817Christoph Grimm 0001Carna RadojicicExtending Affine Arithmetic for Formal Verification of Analog/Mixed-Signal Systems.MBMV39-402017Conference and Workshop Papersunavailableconf/mbmv/GrimmR17https://dblp.org/rec/conf/mbmv/GrimmR17URL#2986818Andreas GrimmerWerner HaselmayrAndreas SpringerRobert WilleVerifikation von Networked Labs-on-Chip Architekturen.MBMV41-422017Conference and Workshop Papersunavailableconf/mbmv/GrimmerHSW17https://dblp.org/rec/conf/mbmv/GrimmerHSW17URL#2986819Amrutansh GudivadaDaniel KriestenUlrich HeinkelRene RölligMatthias LenkOpenCL- Design Flow for High Level Synthesis and Cross-Platform Portability.MBMV43-502017Conference and Workshop Papersunavailableconf/mbmv/GudivadaKHRL17https://dblp.org/rec/conf/mbmv/GudivadaKHRL17URL#2986820M. Ammar Ben KhadraDominik StoffelWolfgang KunzSpeculative disassembly of binary code.MBMV51-522017Conference and Workshop Papersunavailableconf/mbmv/KhadraSK17https://dblp.org/rec/conf/mbmv/KhadraSK17URL#2986821Felix NeubauerKarsten ScheiblerBernd Becker 0001Ahmed MahdiMartin FränzleTino TeigeTom BienmüllerDetlef FehrerAccurate Dead Code Detection in Embedded C Code by Arithmetic Constraint Solving.MBMV53-542017Conference and Workshop Papersunavailableconf/mbmv/NeubauerSBMFTBF17https://dblp.org/rec/conf/mbmv/NeubauerSBMFTBF17URL#2986822Thiyagarajan PurusothamanChristoph Grimm 0001SystemC AMS based Co-simulation Framework for Cyber Physical Systems.MBMV55-662017Conference and Workshop Papersunavailableconf/mbmv/PurusothamanG17https://dblp.org/rec/conf/mbmv/PurusothamanG17URL#2986823Heinz RienerRüdiger EhlersGörschwin FeyCounterexample-Guided EF Synthesis of Boolean Functions.MBMV67-742017Conference and Workshop Papersunavailableconf/mbmv/RienerEF17https://dblp.org/rec/conf/mbmv/RienerEF17URL#2986824Leonard SchneiderOliver KeszöczeJannis StoppeRolf DrechslerEinfluss von Zellformen auf das Routing von Digital Microfluidic Biochips.MBMV75-782017Conference and Workshop Papersunavailableconf/mbmv/SchneiderKSD17https://dblp.org/rec/conf/mbmv/SchneiderKSD17URL#2986825Tobias SeufertChristoph Scholl 0001Sequential Verification Using Reverse PDR.MBMV79-902017Conference and Workshop Papersunavailableconf/mbmv/SeufertS17https://dblp.org/rec/conf/mbmv/SeufertS17URL#2986826Sebastian SimonJérôme KirscherAlexander W. RathZhiqiang ZhangLinus MaurerPre-silicon Verification of an Automotive Battery Management System in the Context of the Application.MBMV91-1022017Conference and Workshop Papersunavailableconf/mbmv/SimonKRZM17https://dblp.org/rec/conf/mbmv/SimonKRZM17URL#2986827Patrick SittelMartin KummKonrad MöllerMartin HardieckPeter ZipfHigh-Level Synthesis for Model-Based Design with Automatic Folding including Combined Common Subcircuits.MBMV103-1142017Conference and Workshop Papersunavailableconf/mbmv/SittelKMHZ17https://dblp.org/rec/conf/mbmv/SittelKMHZ17URL#2986828Ralf StemmerMaher FakihTowards Timing and Power Analysis of FSM-SADFGs on MPSoCs with Shared Memory Communication.MBMV115-1162017Conference and Workshop Papersunavailableconf/mbmv/StemmerF17https://dblp.org/rec/conf/mbmv/StemmerF17URL#2986829Tobias StrauchA Novel RTL ATPG Model Based on Gate Inherent Faults of Complex Gates.MBMV117-1282017Conference and Workshop Papersunavailableconf/mbmv/Strauch17https://dblp.org/rec/conf/mbmv/Strauch17URL#2986830Shrinidhi UdupiJoakim UrdahlDominik StoffelWolfgang KunzDynamic Power Optimization based on Formal Property Checking of Operations.MBMV129-1362017Conference and Workshop Papersunavailableconf/mbmv/UdupiUSK17https://dblp.org/rec/conf/mbmv/UdupiUSK17URL#2986831Daniel GroßeRolf DrechslerMethoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, MBMV 2017, Bremen, Germany, February 8-9, 2017.MBMVShaker Verlag2017Editorshipunavailableconf/mbmv/2017https://dblp.org/rec/conf/mbmv/2017URL#3035746Bo Wang 0010Yang Xu 0019Ralph HasholznerChristian DrewesRafael RosalesSebastian Graf 0002Joachim FalkMichael GlaßJürgen TeichExploration of Power Domain Partitioning for Application-Specific SoCs in System-Level Design.MBMV102-1132016Conference and Workshop Papersclosedconf/mbmv/0010XHDRGFGT1610.6094/UNIFR/10643https://doi.org/10.6094/UNIFR/10643https://dblp.org/rec/conf/mbmv/0010XHDRGFGT16URL#3309576Christian Bartsch 0001Nico RödelCarlos VillarragaDominik StoffelWolfgang KunzA HW-dependent Software Model for Cross-Layer Fault Analysis in Embedded Systems.MBMV10-212016Conference and Workshop Papersclosedconf/mbmv/BartschRVSK1610.6094/UNIFR/10634https://doi.org/10.6094/UNIFR/10634https://dblp.org/rec/conf/mbmv/BartschRVSK16URL#3309577Anoop BhagyanathTripti JainKlaus Schneider 0001Towards Code Generation for the Synchronous Control Asynchronous Dataflow (SCAD) Architectures.MBMV77-882016Conference and Workshop Papersclosedconf/mbmv/BhagyanathJ01610.6094/UNIFR/10641https://doi.org/10.6094/UNIFR/10641https://dblp.org/rec/conf/mbmv/BhagyanathJ016URL#3309578Dimitri BohlenderHendrik SimonStefan KowalewskiSymbolic Verification of PLC Safety-Applications based on PLCopen Automata.MBMV33-452016Conference and Workshop Papersclosedconf/mbmv/BohlenderSK1610.6094/UNIFR/10636https://doi.org/10.6094/UNIFR/10636https://dblp.org/rec/conf/mbmv/BohlenderSK16URL#3309579Arun ChandrasekharanDaniel GroßeMathias SoekenRolf DrechslerSymbolic Error Metric Determination for Approximate Computing.MBMV75-762016Conference and Workshop Papersclosedconf/mbmv/Chandrasekharan1610.6094/UNIFR/10640https://doi.org/10.6094/UNIFR/10640https://dblp.org/rec/conf/mbmv/Chandrasekharan16URL#3309580Christian DehnertSebastian JungesNils Jansen 0001Florian CorziliusMatthias Volk 0001Joost-Pieter KatoenErika ÁbrahámHarold BruintjesParameter Synthesis for Probabilistic Systems.MBMV72-742016Conference and Workshop Papersclosedconf/mbmv/DehnertJ0CVKAB1610.6094/UNIFR/10639https://doi.org/10.6094/UNIFR/10639https://dblp.org/rec/conf/mbmv/DehnertJ0CVKAB16URL#3309581Konstantin LübeckDavid MorgensternThomas SchweizerDustin PetersonWolfgang RosenstielOliver Bringmann 0001Neues Konzept zur Steigerung der Zuverlässigkeit einer ARM-basierten Prozessorarchitektur unter Verwendung eines CGRAs.MBMV46-582016Conference and Workshop Papersclosedconf/mbmv/LubeckMSPRB1610.6094/UNIFR/10637https://doi.org/10.6094/UNIFR/10637https://dblp.org/rec/conf/mbmv/LubeckMSPRB16URL#3309582Thorsten RopertzKarsten BernsXian LiKlaus Schneider 0001Verification of Behavior-Based Control Systems in their Physical Environment.MBMV128-1372016Conference and Workshop Papersclosedconf/mbmv/RopertzBL01610.6094/UNIFR/10646https://doi.org/10.6094/UNIFR/10646https://dblp.org/rec/conf/mbmv/RopertzBL016URL#3309583Andy SauterJoachim GerlachSimulationsbasierte Analyse energietechnischer Systemszenarien.MBMV139-1502016Conference and Workshop Papersclosedconf/mbmv/SauterG1610.6094/UNIFR/10648https://doi.org/10.6094/UNIFR/10648https://dblp.org/rec/conf/mbmv/SauterG16URL#3309584Karsten ScheiblerDominik ErbBernd Becker 0001Applying Tailored Formal Methods to X-ATPG.MBMV1382016Conference and Workshop Papersclosedconf/mbmv/ScheiblerEB1610.6094/UNIFR/10647https://doi.org/10.6094/UNIFR/10647https://dblp.org/rec/conf/mbmv/ScheiblerEB16URL#3309585Carsten SchmittChristoph JäschkeClaudia WolkoberUlla HerterConnecting a C++ based Structural Verification Tool to the Web.MBMV22-322016Conference and Workshop Papersclosedconf/mbmv/SchmittJWH1610.6094/UNIFR/10635https://doi.org/10.6094/UNIFR/10635https://dblp.org/rec/conf/mbmv/SchmittJWH16URL#3309586Thomas SchweizerMurat SimsekOliver Bringmann 0001Wolfgang RosenstielEine Tcl-basierte Methode zur Fehlerinjektion und Fehlereffektsimulation/-emulation auf Xilinx-FPGAs.MBMV59-712016Conference and Workshop Papersclosedconf/mbmv/SchweizerSBR1610.6094/UNIFR/10638https://doi.org/10.6094/UNIFR/10638https://dblp.org/rec/conf/mbmv/SchweizerSBR16URL#3309587Tino TeigeTom BienmüllerHans Jürgen HolbergUniversal Pattern: Formalization, Testing, Coverage, Verification, and Test Case Generation for Safety-Critical Requirements.MBMV6-92016Conference and Workshop Papersclosedconf/mbmv/TeigeBH1610.6094/UNIFR/10633https://doi.org/10.6094/UNIFR/10633https://dblp.org/rec/conf/mbmv/TeigeBH16URL#3309588Jörg Walter 0001Ralph GörgenWolfgang NebelPredicting Performance and Energy Efficiency for Large-Scale Parallel Applications on Highly Heterogeneous Platforms.MBMV116-1272016Conference and Workshop Papersclosedconf/mbmv/WalterGN1610.6094/UNIFR/10645https://doi.org/10.6094/UNIFR/10645https://dblp.org/rec/conf/mbmv/WalterGN16URL#3309589Sebastian WarsitzMaher FakihSimulink-Modell-Übersetzung in synchrone Datenflussgraphen.MBMV89-1012016Conference and Workshop Papersclosedconf/mbmv/WarsitzF1610.6094/UNIFR/10642https://doi.org/10.6094/UNIFR/10642https://dblp.org/rec/conf/mbmv/WarsitzF16URL#3309590Ralf Wimmer 0001Vorwort.MBMV42016Conference and Workshop Papersclosedconf/mbmv/Wimmer1610.6094/UNIFR/10632https://doi.org/10.6094/UNIFR/10632https://dblp.org/rec/conf/mbmv/Wimmer16URL#3309591Karina WimmerLösen von Booleschen Formeln mit Henkin-Quantoren.MBMV114-1152016Conference and Workshop Papersclosedconf/mbmv/Wimmer16a10.6094/UNIFR/10644https://doi.org/10.6094/UNIFR/10644https://dblp.org/rec/conf/mbmv/Wimmer16aURL#3309592Ralf Wimmer 000119th GI/ITG/GMM Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, MBMV 2016, Freiburg im Breisgau, Germany, March 1-2, 2016.MBMVAlbert-Ludwigs-Universität Freiburg2016Editorshipconf/mbmv/2016https://freidok.uni-freiburg.de/data/10617https://dblp.org/rec/conf/mbmv/2016URL#3360168Alexander BiewerPeter MunkJens GladigauChristian HaubeltOn the Influence of Hardware Design Options on Schedule Synthesis in Time-Triggered Real-Time Systems.MBMV105-1142015Conference and Workshop Papersunavailableconf/mbmv/BiewerMGH15https://dblp.org/rec/conf/mbmv/BiewerMGH15URL#3619704Chris DrechslerMatthias SauppeChristian PätzUlrich HeinkelSpecScribe - ein pragmatisch einsetzbares Werkzeug zum Anforderungsmanagement.MBMV41-492015Conference and Workshop Papersunavailableconf/mbmv/DrechslerSPH15https://dblp.org/rec/conf/mbmv/DrechslerSPH15URL#3619705Philipp GorskiTim WegnerDirk TimmermannEvaluation of a software-based centralized traffic management inside run-time reconfigurable regions-of-interest of a mesh-based Network-on-Chip topology.MBMV63-722015Conference and Workshop Papersunavailableconf/mbmv/GorskiWT15https://dblp.org/rec/conf/mbmv/GorskiWT15URL#3619706Sebastian Graf 0002Michael GlaßJürgen TeichSymbolic Message Routing for Multi-Objective Optimization of Automotive E/E Architecture Component Platforms.MBMV115-1242015Conference and Workshop Papersunavailableconf/mbmv/GrafGT15https://dblp.org/rec/conf/mbmv/GrafGT15URL#3619707Xian LiKlaus Schneider 0001A Counterexample-Guided Approach to Symbolic Simulation of Hybrid Systems.MBMV50-622015Conference and Workshop Papersunavailableconf/mbmv/Li015https://dblp.org/rec/conf/mbmv/Li015URL#3619708Matteo MichelJohannes KoestersBenedikt GeukesModulare Verifikation von Non-Mainline Chip-Level Funktionen.MBMV14-192015Conference and Workshop Papersunavailableconf/mbmv/MichelKG15https://dblp.org/rec/conf/mbmv/MichelKG15URL#3619709Stefan MüllerDennis HospachJoachim GerlachOliver Bringmann 0001Wolfgang RosenstielFramework for Varied Sensor Perception in Virtual Prototypes.MBMV145-1542015Conference and Workshop Papersunavailableconf/mbmv/MullerHGBR15https://dblp.org/rec/conf/mbmv/MullerHGBR15URL#3619710Alexander NitschBenjamin BeichlerFrank GolatowskiChristian HaubeltModel-based Systems Engineering with Matlab/Simulink in the Railway Sector.MBMV125-1342015Conference and Workshop Papersunavailableconf/mbmv/NitschBGH15https://dblp.org/rec/conf/mbmv/NitschBGH15URL#3619711Xiao PanJavier Moreno 0003Christoph Grimm 0001Modeling Power Consumption for Design of Power- and Noise-Aware AMS Circuits.MBMV83-922015Conference and Workshop Papersunavailableconf/mbmv/PanM015https://dblp.org/rec/conf/mbmv/PanM015URL#3619712Nils PrzigodaRobert WilleRolf DrechslerVerbesserung der Fehlersuche in inkonsistenten formalen Modellen (Erweiterte Zusammenfassung).MBMV165-1722015Conference and Workshop Papersunavailableconf/mbmv/PrzigodaWD15https://dblp.org/rec/conf/mbmv/PrzigodaWD15URL#3619713Aquib RashidWolfram HardtHOPE: Hardware Optimized Parallel Execution.MBMV155-1592015Conference and Workshop Papersunavailableconf/mbmv/RashidH15https://dblp.org/rec/conf/mbmv/RashidH15URL#3619714Heinz RienerMichael Kirkedal ThomsenGörschwin FeyExecution Tracing of C Code for Formal Analysis (Extended Abstract).MBMV160-1642015Conference and Workshop Papersunavailableconf/mbmv/RienerTF15https://dblp.org/rec/conf/mbmv/RienerTF15URL#3619715Karsten ScheiblerLeonore WintererRalf Wimmer 0001Bernd Becker 0001Towards Verification of Artificial Neural Networks.MBMV30-402015Conference and Workshop Papersunavailableconf/mbmv/ScheiblerWWB15https://dblp.org/rec/conf/mbmv/ScheiblerWWB15URL#3619716Christian SchottMarko RößlerUlrich HeinkelVerfahren zur Assertion basierten Verifikation bei der High-Level-Synthese.MBMV5-132015Conference and Workshop Papersunavailableconf/mbmv/SchottRH15https://dblp.org/rec/conf/mbmv/SchottRH15URL#3619717Sören SchreinerKim GrüttnerSven RosingerWolfgang NebelEin Verfahren zur Bestimmung eines Powermodells von Xilinx MicroBlaze MPSoCs zur Verwendung in Virtuellen Plattformen.MBMV73-822015Conference and Workshop Papersunavailableconf/mbmv/SchreinerGRN15https://dblp.org/rec/conf/mbmv/SchreinerGRN15URL#3619718Tobias StrauchDeriving AOC C-Models from D&V Languages for Single- or Multi-Threaded Execution Using C or C++.MBMV173-1822015Conference and Workshop Papersunavailableconf/mbmv/Strauch15https://dblp.org/rec/conf/mbmv/Strauch15URL#3619719Joakim UrdahlDominik StoffelWolfgang KunzArchitectural System Modeling for Correct-by-Construction RTL Design.MBMV93-1042015Conference and Workshop Papersunavailableconf/mbmv/UrdahlSK15https://dblp.org/rec/conf/mbmv/UrdahlSK15URL#3619720Thilo VörtlerBenny HöcknerPetra HofstedtThomas KlotzFormale Verifikation von eingebetteter Software für das Betriebssystem Contiki unter Berücksichtigung von Interrupts.MBMV20-292015Conference and Workshop Papersunavailableconf/mbmv/VortlerHHK15https://dblp.org/rec/conf/mbmv/VortlerHHK15URL#3619721Lei YangErik MarkertUlrich HeinkelA new Mapping Method from Fuzzy Logic System into Fuzzy Automaton.MBMV135-1442015Conference and Workshop Papersunavailableconf/mbmv/YangMH15https://dblp.org/rec/conf/mbmv/YangMH15URL#3619722Ulrich HeinkelDaniel KriestenMarko RößlerMethoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, MBMV 2015, Chemnitz, Germany, March 3-4, 2015.MBMVSächsische Landesbibliothek2015Editorshipunavailableconf/mbmv/2015https://d-nb.info/1068405465https://dblp.org/rec/conf/mbmv/2015URL#3668573Christian AppoldA New Approach to Use Partial Results During Image Computation in BDD Based Symbolic Model Checking.MBMV37-472014Conference and Workshop Papersunavailableconf/mbmv/Appold14https://dblp.org/rec/conf/mbmv/Appold14URL#3914632Rafal BaranowskiMichael A. KochteHans-Joachim WunderlichVerifikation Rekonfigurierbarer Scan-Netze.MBMV137-1462014Conference and Workshop Papersunavailableconf/mbmv/BaranowskiKW14https://dblp.org/rec/conf/mbmv/BaranowskiKW14URL#3914633Christian Bartsch 0001Carlos VillarragaBernard SchmidtDominik StoffelWolfgang KunzEfficient SAT/simulation-based model generation for low-level embedded software.MBMV147-1572014Conference and Workshop Papersunavailableconf/mbmv/BartschVSSK14https://dblp.org/rec/conf/mbmv/BartschVSSK14URL#3914634Maarten BoersmaUlrike Schmidt 0002Markus KaltenbachAutomatic detection of sticky clock gating equations.MBMV93-1002014Conference and Workshop Papersunavailableconf/mbmv/BoersmaSK14https://dblp.org/rec/conf/mbmv/BoersmaSK14URL#3914635Sebastian BurgPatrick HeckelerStefan HusterHanno EichelbergerJörg BehrendJürgen RufThomas KropfOliver Bringmann 0001LoCEG: Local Preprocessing in SAT-Solving through Counter-Example Generation.MBMV193-1962014Conference and Workshop Papersunavailableconf/mbmv/BurgHHEBRKB14https://dblp.org/rec/conf/mbmv/BurgHHEBRKB14URL#3914636Hanno EichelbergerPatrick HeckelerJürgen RufStefan HusterSebastian BurgThomas KropfWolfgang RosenstielThomas GreinerErkennen von Speicherverletzungen im Testbetrieb von eingebetteter Software.MBMV61-702014Conference and Workshop Papersunavailableconf/mbmv/EichelbergerHRHBKRG14https://dblp.org/rec/conf/mbmv/EichelbergerHRHBKRG14URL#3914637Robert FischbachMichael DittrichAndy HeinigEffizienter Design Rule Check von 3D Systemaufbauten mit einer hierarchischen XML-basierten Modellierungssprache.MBMV183-1922014Conference and Workshop Papersunavailableconf/mbmv/FischbachDH14https://dblp.org/rec/conf/mbmv/FischbachDH14URL#3914638Manuel GesellFelipe BichuedKlaus Schneider 0001Using Different Representations of Synchronous Systems in SAL.MBMV13-242014Conference and Workshop Papersunavailableconf/mbmv/GesellBS14https://dblp.org/rec/conf/mbmv/GesellBS14URL#3914639Stefan HusterMerdin MacicSebastian BurgHanno EichelbergerPatrick HeckelerJürgen RufThomas KropfWolfgang RosenstielIncreasing Software Reliability by Integrating Formal Verification and Robustness Testing.MBMV125-1362014Conference and Workshop Papersunavailableconf/mbmv/HusterMBEHRKR14https://dblp.org/rec/conf/mbmv/HusterMBEHRKR14URL#3914640Mohamed Ammar Ben KhadraYu Bai 0003Klaus Schneider 0001Synthesis of Distributed Synchronous Specifications to SysteMoC.MBMV71-812014Conference and Workshop Papersunavailableconf/mbmv/KhadraBS14https://dblp.org/rec/conf/mbmv/KhadraBS14URL#3914641Vladimir KolchuzhinJan MehnerMilind ShendeErik MarkertUlrich HeinkelChristian Wagner 0012Thomas GessnerSystem Level Modeling of Piezoresistive Effect of Carbon Nanotubes for Sensor Application.MBMV205-2082014Conference and Workshop Papersunavailableconf/mbmv/KolchuzhinMSMHWG14https://dblp.org/rec/conf/mbmv/KolchuzhinMSMHWG14URL#3914642Bastian KoppelmannMarkus Becker 0001Wolfgang Müller 0003Portierung der TriCore-Architektur auf QEMU.MBMV49-602014Conference and Workshop Papersunavailableconf/mbmv/KoppelmannB014https://dblp.org/rec/conf/mbmv/KoppelmannB014URL#3914643Martin KummPeter ZipfEfficient High Speed Compression Trees on Xilinx FPGAs.MBMV171-1822014Conference and Workshop Papersunavailableconf/mbmv/KummZ14https://dblp.org/rec/conf/mbmv/KummZ14URL#3914644Christoph KuznikBertrand DefoWolfgang Müller 0003Semi-automatische Generierung von Überdeckungsmetriken mittels methodischer Verikationsplan Verarbeitung.MBMV113-1242014Conference and Workshop Papersunavailableconf/mbmv/KuznikD014https://dblp.org/rec/conf/mbmv/KuznikD014URL#3914645Konrad MöllerMartin KummBjörn BarschtipanPeter ZipfDynamically Reconfigurable Constant Multiplication on FPGAs.MBMV159-1692014Conference and Workshop Papersunavailableconf/mbmv/MollerKBZ14https://dblp.org/rec/conf/mbmv/MollerKBZ14URL#3914646Carna RadojicicKristin KrügerChristoph Grimm 0001Semi-Symbolische Analyse eines Sigma-Delta Modulators.MBMV83-922014Conference and Workshop Papersunavailableconf/mbmv/RadojicicKG14https://dblp.org/rec/conf/mbmv/RadojicicKG14URL#3914647Heinz RienerOliver KeszöczeRolf DrechslerGörschwin FeyA Logic for Cardinality Constraints (Extended Abstract).MBMV217-2202014Conference and Workshop Papersunavailableconf/mbmv/RienerKDF14https://dblp.org/rec/conf/mbmv/RienerKDF14URL#3914648Karsten ScheiblerBernd Becker 0001Implication Graph Compression inside the SMT Solver iSAT3.MBMV25-362014Conference and Workshop Papersunavailableconf/mbmv/ScheiblerB14https://dblp.org/rec/conf/mbmv/ScheiblerB14URL#3914649Mathias SoekenMax NitzeRolf DrechslerFormale Methoden für Alle.MBMV213-2162014Conference and Workshop Papersunavailableconf/mbmv/SoekenND14https://dblp.org/rec/conf/mbmv/SoekenND14URL#3914650Sebastian StieberJohann-Peter WolffChristian HaubeltRainer DorschHybride Prototypisierung eines Sensorsubsystems.MBMV209-2122014Conference and Workshop Papersunavailableconf/mbmv/StieberWHD14https://dblp.org/rec/conf/mbmv/StieberWHD14URL#3914651Niels TholeGörschwin FeyEquivalence Checking on System Level using Stepwise Induction.MBMV197-2002014Conference and Workshop Papersunavailableconf/mbmv/TholeF14https://dblp.org/rec/conf/mbmv/TholeF14URL#3914652Roberto UrbanKai LehnigerMaximilian HeyneMario SchölzelHeinrich Theodor VierhausVergleich der Beschreibung und Simulation einer Befehlssatzarchitektur in LISA und CoMet.MBMV101-1112014Conference and Workshop Papersunavailableconf/mbmv/UrbanLHSV14https://dblp.org/rec/conf/mbmv/UrbanLHSV14URL#3914653Aljoscha WindhorstHoang Minh Le 0001Daniel GroßeRolf DrechslerFunktionale Abdeckungsanalyse von C-Programmen.MBMV201-2042014Conference and Workshop Papersunavailableconf/mbmv/WindhorstLGD14https://dblp.org/rec/conf/mbmv/WindhorstLGD14URL#3914654Jürgen RufDirk AllmendingerMatteo MichelMethoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, MBMV 2014, Böblingen, GermanyMBMVCuvillier2014Editorshipunavailableconf/mbmv/2014https://dblp.org/rec/conf/mbmv/2014URL#3962805Benjamin AndresMartin GebserTorsten SchaubChristian HaubeltFelix ReimannMichael GlaßA Combined Mapping and Routing Algorithm for 3D NoCs Based on ASP.MBMV35-462013Conference and Workshop Papersunavailableconf/mbmv/AndresGSHRG13https://dblp.org/rec/conf/mbmv/AndresGSHRG13URL#4200016Binghao BaoJörg BormannMarkus WedlerDominik StoffelWolfgang KunzCompositional Completeness over reactive Constraints.MBMV83-962013Conference and Workshop Papersunavailableconf/mbmv/BaoBWSK13https://dblp.org/rec/conf/mbmv/BaoBWSK13URL#4200017Bettina BraitlingRalf Wimmer 0001Bernd Becker 0001Erika ÁbrahámStochastic Bounded Model Checking: Bounded Rewards and Compositionality.MBMV243-2542013Conference and Workshop Papersunavailableconf/mbmv/BraitlingWBA13https://dblp.org/rec/conf/mbmv/BraitlingWBA13URL#4200018Markus DoblerWolfgang RosenstielMartin BogdanMonica RafailaDirk HammerschmidtGeorg PelzRapid Design Space Exploration of a State-of-the-art PSI 5 Controller.MBMV3-122013Conference and Workshop Papersunavailableconf/mbmv/DoblerRBRHP13https://dblp.org/rec/conf/mbmv/DoblerRBRHP13URL#4200019Hanno EichelbergerPatrick HeckelerStefan HusterSebastian BurgJürgen RufThomas KropfWolfgang RosenstielBastian SchlichBeschleunigte Robustheitstests für verhaltensbeschreibende Zustandsmaschinen.MBMV161-1702013Conference and Workshop Papersunavailableconf/mbmv/EichelbergerHHBRKRS13https://dblp.org/rec/conf/mbmv/EichelbergerHHBRKRS13URL#4200020Martin GagTim WegnerPhilipp GorskiAndreas TockhornDirk TimmermannSystem level modeling of Networks-on-Chip for power estimation and design space exploration.MBMV25-342013Conference and Workshop Papersunavailableconf/mbmv/GagWGTT13https://dblp.org/rec/conf/mbmv/GagWGTT13URL#4200021Manuel GesellKlaus Schneider 0001An Interactive Verification Tool for Synchronous/Reactive Systems.MBMV267-2772013Conference and Workshop Papersunavailableconf/mbmv/GesellS13https://dblp.org/rec/conf/mbmv/GesellS13URL#4200022André GießlerJörg Ritter 0002Paul MolitorModel Checking for PLC based Railway Interlocking Systems.MBMV71-822013Conference and Workshop Papersunavailableconf/mbmv/GiesslerRM13https://dblp.org/rec/conf/mbmv/GiesslerRM13URL#4200023Karina GitinaSven ReimerMatthias Sauer 0002Ralf Wimmer 0001Christoph Scholl 0001Bernd Becker 0001Equivalence Checking for Partial Implementations Revisited.MBMV61-702013Conference and Workshop Papersunavailableconf/mbmv/GitinaRSWSB13https://dblp.org/rec/conf/mbmv/GitinaRSWSB13URL#4200024Sebastian Graf 0002Michael GlaßJürgen TeichInvestigating the Impact of Energy-Efficient Ethernet on Automotive Applications via High-level Modeling.MBMV117-1282013Conference and Workshop Papersunavailableconf/mbmv/GrafGT13https://dblp.org/rec/conf/mbmv/GrafGT13URL#4200025Thomas HornMatthias SauppeErik MarkertUlrich HeinkelWolfgang RösselHans-Werner SahmEinsatz formaler Methoden zur Energieeinsparung.MBMV141-1462013Conference and Workshop Papersunavailableconf/mbmv/HornSMHRS13https://dblp.org/rec/conf/mbmv/HornSMHRS13URL#4200026Stefan HusterPatrick HeckelerJürgen RufSebastian BurgThomas KropfWolfgang RosenstielA Software Testing Framework to Integrate Formal Verification Results.MBMV183-1922013Conference and Workshop Papersunavailableconf/mbmv/HusterHRBKR13https://dblp.org/rec/conf/mbmv/HusterHRBKR13URL#4200027Kai HyllaPhilipp A. HartmannDomenik HelmsWolfgang NebelEarly Power & Timing Estimation of Custom Hardware Blocks based on Automatically Generated Combinatorial Macros.MBMV147-1582013Conference and Workshop Papersunavailableconf/mbmv/HyllaHHN13https://dblp.org/rec/conf/mbmv/HyllaHHN13URL#4200028Philipp IttershagenPhilipp A. HartmannKim GrüttnerWolfgang NebelAnsatz zur Bewertung der HW/SW-Kommunikation in asymmetrischen Multi-Prozessor-Systemen.MBMV197-2072013Conference and Workshop Papersunavailableconf/mbmv/IttershagenHGN13https://dblp.org/rec/conf/mbmv/IttershagenHGN13URL#4200029Lars KosmannAxel ReimerDomenik HelmsWolfgang NebelProfilbasierte Energieabschätzung integrierter Schaltungen auf algorithmischer Ebene.MBMV131-1402013Conference and Workshop Papersunavailableconf/mbmv/KosmannRHN13https://dblp.org/rec/conf/mbmv/KosmannRHN13URL#4200030Oliver MarxMarkus WedlerDominik StoffelWolfgang KunzAlexander DreyerProof Logging for Computer Algebra based SMT Solving.MBMV255-2652013Conference and Workshop Papersunavailableconf/mbmv/MarxWSKD13https://dblp.org/rec/conf/mbmv/MarxWSKD13URL#4200031Fabian MischkallaWolfgang Müller 0003Funktionale Verifikation von Low-Power Designs unter Verwendung Virtueller Prototypen.MBMV171-1812013Conference and Workshop Papersunavailableconf/mbmv/Mischkalla013https://dblp.org/rec/conf/mbmv/Mischkalla013URL#4200032Stefan MüllerYumin ZhouAxel G. BraunJoachim GerlachWolfgang RosenstielEin template-basierter Ansatz zur automatisierten Generierung von SystemC-Modellen aus IP-XACT-Beschreibungen.MBMV209-2182013Conference and Workshop Papersunavailableconf/mbmv/MullerZBGR13https://dblp.org/rec/conf/mbmv/MullerZBGR13URL#4200033Heinz RienerGörschwin FeyYet a Better Error Explanation Algorithm (Extended Abstract).MBMV193-1942013Conference and Workshop Papersunavailableconf/mbmv/RienerF13https://dblp.org/rec/conf/mbmv/RienerF13URL#4200034Marko RößlerJan LangerUlrich HeinkelSynchronisation von Schleifenkörpern zur dynamischen Ablaufplanung über die HW/SW-Grenze eines Configurable System on Chip (CSoC).MBMV219-2282013Conference and Workshop Papersunavailableconf/mbmv/RosslerLH13https://dblp.org/rec/conf/mbmv/RosslerLH13URL#4200035Karsten ScheiblerStefan KupferschmidBernd Becker 0001Recent Improvements in the SMT Solver iSAT.MBMV231-2412013Conference and Workshop Papersunavailableconf/mbmv/ScheiblerKB13https://dblp.org/rec/conf/mbmv/ScheiblerKB13URL#4200036Bernard SchmidtCarlos VillarragaThomas FehmelDominik StoffelWolfgang KunzJörg BormannA Hardware-Dependent Model for SAT-based Verification of Interrupt-Driven Low-level Embedded System Software.MBMV49-602013Conference and Workshop Papersunavailableconf/mbmv/SchmidtVFSKB13https://dblp.org/rec/conf/mbmv/SchmidtVFSKB13URL#4200037Mathias SoekenRobert WilleEugen KuksaRolf DrechslerGenerierung von OCL-Ausdrücken aus natürlichsprachlichen Beschreibungen.MBMV99-1032013Conference and Workshop Papersunavailableconf/mbmv/SoekenWKD13https://dblp.org/rec/conf/mbmv/SoekenWKD13URL#4200038Roberto UrbanMario SchölzelHeinrich Theodor VierhausEin konfigurierbarer Zwischencodesimulator zum compilerzentrierten Mikroprozessorentwurf.MBMV13-242013Conference and Workshop Papersunavailableconf/mbmv/UrbanSV13https://dblp.org/rec/conf/mbmv/UrbanSV13URL#4200039Christian ZebeleinChristian HaubeltJoachim FalkJürgen TeichModel-Based Representation of Schedules for Dataflow Graphs.MBMV105-1152013Conference and Workshop Papersunavailableconf/mbmv/ZebeleinHFT13https://dblp.org/rec/conf/mbmv/ZebeleinHFT13URL#4200040Christian HaubeltDirk TimmermannMethoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Warnemünde, Germany, March 12-14, 2013.MBMVInstitut für Angewandte Mikroelektronik und Datentechnik, Fakultät für Informatik und Elektrotechnik, Universität Rostock2013Editorshipunavailableconf/mbmv/2013https://dblp.org/rec/conf/mbmv/2013URL#4247834Christian AppoldFast Symbolic Model Checking for Partitioned Transition Relations with Isomorphic Partitions.MBMV1-122012Conference and Workshop Papersunavailableconf/mbmv/Appold12https://dblp.org/rec/conf/mbmv/Appold12URL#4468302Sebastian Graf 0002Michael GlaßJürgen TeichUnreliable Data Transmissions und Limited Hardware Communication Buffers in Automotive E/E Virtual Prototypes.MBMV13-242012Conference and Workshop Papersunavailableconf/mbmv/GrafGT12https://dblp.org/rec/conf/mbmv/GrafGT12URL#4468303Alexander GrünhageJörg BehrendPatrick HeckelerJürgen RufThomas KropfWolfgang RosenstielDjones LettninOptimized Static Parameter Assignment for Semiformal Software Verification.MBMV25-352012Conference and Workshop Papersunavailableconf/mbmv/GrunhageBHRKRL12https://dblp.org/rec/conf/mbmv/GrunhageBHRKRL12URL#4468304Finn HaedickeHoang Minh Le 0001Daniel GroßeRolf DrechslerCRAVE: An Advanced Constrained RAndom Verification Environment for SystemC.MBMV37-482012Conference and Workshop Papersunavailableconf/mbmv/HaedickeLGD12https://dblp.org/rec/conf/mbmv/HaedickeLGD12URL#4468305Simon HufnagelNico BannowChristoph Grimm 0001Jiong OuAbstract Modeling of Communication Errors in Cyber-Physical Systems using uPN.MBMV49-592012Conference and Workshop Papersunavailableconf/mbmv/HufnagelBGO12https://dblp.org/rec/conf/mbmv/HufnagelBGO12URL#4468306Thomas KlotzBernd StraubeEva FordranNorman SeßlerJürgen HaufeFrank SchulzeEin Ansatz zur Verifikation von Materialflusssteuerungen.MBMV61-712012Conference and Workshop Papersunavailableconf/mbmv/KlotzSFSHS12https://dblp.org/rec/conf/mbmv/KlotzSFSHS12URL#4468307Daniel Lorenz 0002Philipp A. HartmannKim GrüttnerAchim RettbergNicht-invasive Simulation des Energieverbrauchs von Hardware-Komponenten auf Systemebene mit SystemC.MBMV73-832012Conference and Workshop Papersunavailableconf/mbmv/LorenzHGR12https://dblp.org/rec/conf/mbmv/LorenzHGR12URL#4468308Jan MalburgAlexander FinderGörschwin FeyAutomated Feature Localization for Hardware Designs using Coverage Metrics.MBMV85-962012Conference and Workshop Papersunavailableconf/mbmv/MalburgFF12https://dblp.org/rec/conf/mbmv/MalburgFF12URL#4468309Georges MorbéChristoph Scholl 0001Fully Symbolic Model Checking for Incomplete Systems of Timed Automata.MBMV97-1082012Conference and Workshop Papersunavailableconf/mbmv/MorbeS12https://dblp.org/rec/conf/mbmv/MorbeS12URL#4468310Johanna NellenErika ÁbrahámHybrid Sequential Function Charts.MBMV109-1202012Conference and Workshop Papersunavailableconf/mbmv/NellenA12https://dblp.org/rec/conf/mbmv/NellenA12URL#4468311Gregor NitscheGeorg GlaeserDirk NuernbergkEckhard HennigHardware/Software Co-design of a Smart Sensor Interface Using a Fast but Accurate Close-to-RTL Instruction Set Interpreter.MBMV121-1322012Conference and Workshop Papersunavailableconf/mbmv/NitscheGNH12https://dblp.org/rec/conf/mbmv/NitscheGNH12URL#4468312Sven ReimerFlorian PigorschChristoph Scholl 0001Bernd Becker 0001Enhanced Integration of QBF Solving Techniques.MBMV133-1432012Conference and Workshop Papersunavailableconf/mbmv/ReimerPSB12https://dblp.org/rec/conf/mbmv/ReimerPSB12URL#4468313Hagen SämrowClaas CorneliusPhilipp GorskiJakob SalzmannDirk TimmermannEffiziente Simulation von Gateoxiddefekten auf Gatterebene mit Transistorlevel-Genauigkeit.MBMV157-1682012Conference and Workshop Papersunavailableconf/mbmv/SamrowCGST12https://dblp.org/rec/conf/mbmv/SamrowCGST12URL#4468314Timo SchönwaldBenjamin RanftOliver Bringmann 0001Wolfgang RosenstielLatency-Optimized Force-directed Process Mapping for MPSoC Architectures.MBMV145-1562012Conference and Workshop Papersunavailableconf/mbmv/SchonwaldRBR12https://dblp.org/rec/conf/mbmv/SchonwaldRBR12URL#4468315Ralf Wimmer 0001Bernd Becker 0001Nils Jansen 0001Erika ÁbrahámJoost-Pieter KatoenMinimal Critical Subsystems as Counterexamples for omega-Regular DTMC Properties.MBMV169-1802012Conference and Workshop Papersunavailableconf/mbmv/WimmerBJAK12https://dblp.org/rec/conf/mbmv/WimmerBJAK12URL#4468316Christian ZebeleinChristian HaubeltJoachim FalkJürgen TeichExploiting Model-Knowledge in High-Level Synthesis.MBMV181-1912012Conference and Workshop Papersunavailableconf/mbmv/ZebeleinHFT12https://dblp.org/rec/conf/mbmv/ZebeleinHFT12URL#4468317Liyuan Zhang 0001Michael GlaßMartin StreubührJürgen TeichAndreas von SchwerinKai LiuActor-oriented Modeling und Simulation of Cut-through Communication in Network Controllers.MBMV193-2042012Conference and Workshop Papersunavailableconf/mbmv/ZhangGSTSL12https://dblp.org/rec/conf/mbmv/ZhangGSTSL12URL#4468318Jens Brandt 0001Klaus Schneider 0001Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Kaiserslautern, Germany, March 5-7, 2012MBMVForschungsergebnisse zur Informatik68Verlag Dr. Kovac2012Editorshipconf/mbmv/2012http://www.verlagdrkovac.de/3-8300-6201-X.htmhttps://dblp.org/rec/conf/mbmv/2012URL#4514317Nico AdlerDaniel GebauerClemens ReichmannKlaus D. Müller-GlaserModellbasierte Erfassung von Optimierungsaktivitäten als Grundlage zur Systemoptimierung von Elektrik-/Elektronik-Architekturen.MBMV163-1722011Conference and Workshop Papersunavailableconf/mbmv/AdlerGRM11https://dblp.org/rec/conf/mbmv/AdlerGRM11URL#4724411Christian AppoldSymbolic Model Checking with Isomorphism Exploiting Transition Relations.MBMV29-382011Conference and Workshop Papersunavailableconf/mbmv/Appold11https://dblp.org/rec/conf/mbmv/Appold11URL#4724412Jörg BehrendPatrick HeckelerStefan HusterDjones LettninJürgen RufThomas KropfWolfgang RosenstielScalable and Extendable Hybrid Verification Platform.MBMV259-2682011Conference and Workshop Papersunavailableconf/mbmv/BehrendHHLRKR11https://dblp.org/rec/conf/mbmv/BehrendHHLRKR11URL#4724413Bettina BraitlingRalf Wimmer 0001Bernd Becker 0001Nils Jansen 0001Erika ÁbrahámSMT-based Counterexample Generation for Markov Chains.MBMV19-282011Conference and Workshop Papersunavailableconf/mbmv/BraitlingWBJA11https://dblp.org/rec/conf/mbmv/BraitlingWBJA11URL#4724414Jens Brandt 0001Klaus Schneider 0001Round Trip to Asynchrony and Synchrony.MBMV239-2482011Conference and Workshop Papersunavailableconf/mbmv/BrandtS11https://dblp.org/rec/conf/mbmv/BrandtS11URL#4724415Axel G. BraunJoachim GerlachWolfgang RosenstielSystemC-based Performance Optimization in Embedded System Design: A Synthetic-Aperture-Radar (SAR) Case Study.MBMV101-1092011Conference and Workshop Papersunavailableconf/mbmv/BraunGR11https://dblp.org/rec/conf/mbmv/BraunGR11URL#4724416Gilles B. DefoWolfgang Müller 0003Heinrich RommelSynchronisation eines SystemC Restbus-Simulators mit einem Hardware-In-the-Loop FlexRay Netzwerk.MBMV219-2282011Conference and Workshop Papersunavailableconf/mbmv/Defo0R11https://dblp.org/rec/conf/mbmv/Defo0R11URL#4724417Tobias DornesMartin SchweikertHans EvekingAnalyse von Gegenbeispielen bei Verifikation mit unvollständigen Eigenschaftssätzen.MBMV123-1322011Conference and Workshop Papersunavailableconf/mbmv/DornesSE11https://dblp.org/rec/conf/mbmv/DornesSE11URL#4724418André GießlerJörg Ritter 0002Paul MolitorBDD-based Analysis of Test Cases for PLC-based Railway Interlocking Systems.MBMV133-1432011Conference and Workshop Papersunavailableconf/mbmv/GiesslerRM11https://dblp.org/rec/conf/mbmv/GiesslerRM11URL#4724419Carsten GremzowNico MoserJan LucassysCgen - A Tool for SystemC TLM Simulator Synthesis.MBMV203-2062011Conference and Workshop Papersunavailableconf/mbmv/GremzowML11https://dblp.org/rec/conf/mbmv/GremzowML11URL#4724420Daniel GroßeMarkus GroßUlrich KühneRolf DrechslerSimulation-based Equivalence Checking between SystemC Models at Different Levels of Abstraction.MBMV269-2782011Conference and Workshop Papersunavailableconf/mbmv/GrosseGKD11https://dblp.org/rec/conf/mbmv/GrosseGKD11URL#4724421Jörg HenkelDependable Embedded Systems - Introduction and overview of the DFG SPP-1500.MBMV49-492011Conference and Workshop Papersunavailableconf/mbmv/Henkel11https://dblp.org/rec/conf/mbmv/Henkel11URL#4724422Philipp IttershagenPhilipp A. HartmannKim GrüttnerAchim RettbergEin generisches Treiber-Framework zur HW/SW-Kommunikation mittels OSSS-RMI.MBMV145-1542011Conference and Workshop Papersunavailableconf/mbmv/IttershagenHGR11https://dblp.org/rec/conf/mbmv/IttershagenHGR11URL#4724423Ben H. H. JuurlinkMulti-Core - the Future of Embedded Systems.MBMV111-1112011Conference and Workshop Papersunavailableconf/mbmv/Juurlink11https://dblp.org/rec/conf/mbmv/Juurlink11URL#4724424Henning KleenShangkun XiaoRalph GörgenNico BannowWolfgang NebelAutomatische Übersetzung von MATLAB/Simulink-Modellen nach SystemC-AMS.MBMV173-1822011Conference and Workshop Papersunavailableconf/mbmv/KleenXGBN11https://dblp.org/rec/conf/mbmv/KleenXGBN11URL#4724425Steffen KollmannVictor PollexFrank SlomkaReducing Response Times by Competition Based Dependencies.MBMV91-1002011Conference and Workshop Papersunavailableconf/mbmv/KollmannPS11https://dblp.org/rec/conf/mbmv/KollmannPS11URL#4724426Christian KöllnerHai YaoKlaus D. Müller-GlaserEntwurfsmethodiken zur Echtzeitsimulation physikalisch motivierter Modelle auf FPGAs: Eine Fallstudie.MBMV81-902011Conference and Workshop Papersunavailableconf/mbmv/KollnerYM11https://dblp.org/rec/conf/mbmv/KollnerYM11URL#4724427Matthias KubaZekeriya MansurogluUntersuchung von Methoden zur Hardwarebeschleunigung eines FPGA-basierten Java-Systems mit Soft-IP Prozessor.MBMV155-1622011Conference and Workshop Papersunavailableconf/mbmv/KubaM11https://dblp.org/rec/conf/mbmv/KubaM11URL#4724428Stefan KupferschmidBernd Becker 0001Craigsche Interpolation für Boolesche Kombinationen linearer und nichtlinearer Ungleichungen.MBMV279-2882011Conference and Workshop Papersunavailableconf/mbmv/KupferschmidB11https://dblp.org/rec/conf/mbmv/KupferschmidB11URL#4724429Andreas MaudererJan-Hendrik OetjensWolfgang RosenstielSystem-Level Design for Automotive Mixed-Signal ASICs: An Industrial Point of View.MBMV229-2382011Conference and Workshop Papersunavailableconf/mbmv/MaudererOR11https://dblp.org/rec/conf/mbmv/MaudererOR11URL#4724430Christian MillerChristoph Scholl 0001Bernd Becker 0001Verifying Incomplete Networks of Timed Automata.MBMV113-1222011Conference and Workshop Papersunavailableconf/mbmv/MillerSB11https://dblp.org/rec/conf/mbmv/MillerSB11URL#4724431Georges MorbéChristoph Scholl 0001Fully Symbolic Model Checking for Timed Automata.MBMV9-182011Conference and Workshop Papersunavailableconf/mbmv/MorbeS11https://dblp.org/rec/conf/mbmv/MorbeS11URL#4724432Andreas MorgensternKlaus Schneider 0001Synthesis of Parallel Sorting Networks using SAT Solvers.MBMV71-802011Conference and Workshop Papersunavailableconf/mbmv/MorgensternS11https://dblp.org/rec/conf/mbmv/MorgensternS11URL#4724433Clemens MüllerRequirements for Next Generation Functional Verification.MBMV207-2072011Conference and Workshop Papersunavailableconf/mbmv/Muller11https://dblp.org/rec/conf/mbmv/Muller11URL#4724434Minh D. NguyenMarkus WedlerBernard SchmidtDominik StoffelWolfgang KunzFormal Hardware/Software Co-Verification by Interval Property Checking with Abstraction.MBMV61-702011Conference and Workshop Papersunavailableconf/mbmv/NguyenWSSK11https://dblp.org/rec/conf/mbmv/NguyenWSSK11URL#4724435Evgeny PavlenkoMarkus WedlerDominik StoffelWolfgang KunzAlexander DreyerFrank SeelischGert-Martin GreuelSTABLE: A new QF-BV SMT Solver for hard Verification Problems combining Boolean Reasoning with Computer Algebra.MBMV51-602011Conference and Workshop Papersunavailableconf/mbmv/PavlenkoWSKDSG11https://dblp.org/rec/conf/mbmv/PavlenkoWSKDSG11URL#4724436Martin SchweikertTobias DornesHans EvekingErzeugung von Operationseigenschaften aus UML Sequenzdiagrammen.MBMV209-2182011Conference and Workshop Papersunavailableconf/mbmv/SchweikertDE11https://dblp.org/rec/conf/mbmv/SchweikertDE11URL#4724437André SeffrinSorin A. HussDetermining Minimum Interconnect for Reconfigurable Hardware by Analysis and Verification of Pi-Calculus Design Specifications.MBMV193-2022011Conference and Workshop Papersunavailableconf/mbmv/SeffrinH11https://dblp.org/rec/conf/mbmv/SeffrinH11URL#4724438Mathias SoekenUlrich KühneMartin FreibotheGörschwin FeyRolf DrechslerTowards Automatic Property Generation for the Formal Verification of Bus Bridges.MBMV183-1922011Conference and Workshop Papersunavailableconf/mbmv/SoekenKFFD11https://dblp.org/rec/conf/mbmv/SoekenKFFD11URL#4724439Thilo VörtlerThomas KlotzEva FordranPetra HofstedtFormale Verifikation von Contiki-Anwendungen.MBMV39-482011Conference and Workshop Papersunavailableconf/mbmv/VortlerKFH11https://dblp.org/rec/conf/mbmv/VortlerKFH11URL#4724440Robert WilleMathias SoekenDaniel GroßeEleonora SchönbornRolf DrechslerDesigning a RISC CPU in Reversible Logic.MBMV249-2582011Conference and Workshop Papersunavailableconf/mbmv/WilleSGSD11https://dblp.org/rec/conf/mbmv/WilleSGSD11URL#4724441Frank OppenheimerMethoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Oldenburg, Germany, February 21-23, 2011MBMVOFFIS-Institut für Informatik2011Editorshipunavailableconf/mbmv/2011https://dblp.org/rec/conf/mbmv/2011URL#4765744Daniel BaudischJens Brandt 0001Klaus Schneider 0001Multithreaded Code from Synchronous Programs: Generating Software Pipelines for OpenMP.MBMV11-202010Conference and Workshop Papersunavailableconf/mbmv/BaudischBS10https://dblp.org/rec/conf/mbmv/BaudischBS10URL#4959289Enrico BillichMarko RößlerUlrich HeinkelEffiziente Auslastung der heterogenen Ressourcen eines Systems durch domain-übergreifendes Multithreading.MBMV127-1362010Conference and Workshop Papersunavailableconf/mbmv/BillichRH10https://dblp.org/rec/conf/mbmv/BillichRH10URL#4959290Alexander BolWolfgang Müller 0003Alexander KruppEine strukturierte Methode zur Generierung von SystemVerilog-Testumgebungen aus textuellen Anforderungsbeschreibungen.MBMV167-1762010Conference and Workshop Papersunavailableconf/mbmv/Bol0K10https://dblp.org/rec/conf/mbmv/Bol0K10URL#4959291Jens Brandt 0001Mike GemündeKlaus Schneider 0001From Synchronous Guarded Actions to SystemC.MBMV187-1962010Conference and Workshop Papersunavailableconf/mbmv/BrandtGS10https://dblp.org/rec/conf/mbmv/BrandtGS10URL#4959292Tobias DornesHans EvekingFormale Verifikation von Systemeigenschaften unter Verwendung normalisierter formaler Spezifikationen.MBMV47-562010Conference and Workshop Papersunavailableconf/mbmv/DornesE10https://dblp.org/rec/conf/mbmv/DornesE10URL#4959293Joachim FalkChristian ZebeleinChristian HaubeltJürgen TeichRainer DorschIntegrating Hardware/Firmware Verification Efforts Using SystemC High-Level Models.MBMV137-1462010Conference and Workshop Papersunavailableconf/mbmv/FalkZHTD10https://dblp.org/rec/conf/mbmv/FalkZHTD10URL#4959294Christoph JäschkeCarsten SchmittUlla HerterTobias WichJochen RustStrukturelle Verifikation mittels parser-gesteuerter Netzlisten-Traversierung.MBMV227-2362010Conference and Workshop Papersunavailableconf/mbmv/JaschkeSHWR10https://dblp.org/rec/conf/mbmv/JaschkeSHWR10URL#4959295Natalia KalinnikErika ÁbrahámTobias Schubert 0001Ralf Wimmer 0001Bernd Becker 0001Exploiting Different Strategies for the Parallelization of an SMT Solver.MBMV97-1062010Conference and Workshop Papersunavailableconf/mbmv/KalinnikASWB10https://dblp.org/rec/conf/mbmv/KalinnikASWB10URL#4959296Rainer KieselOtto LöhleinAnestis TerzisMartin StreubührChristian HaubeltJürgen TeichActor-oriented Modeling of Driver Assistance Systems for Efficient Multi-Core ECU Implementation.MBMV117-1262010Conference and Workshop Papersunavailableconf/mbmv/KieselLTSHT10https://dblp.org/rec/conf/mbmv/KieselLTSHT10URL#4959297Steffen KollmannVictor PollexFrank SlomkaHolistic Real-Time Analysis with an Expressive Event Model.MBMV67-762010Conference and Workshop Papersunavailableconf/mbmv/KollmannPS10https://dblp.org/rec/conf/mbmv/KollmannPS10URL#4959298Daniel KriestenUlrich HeinkelJörg SchneiderIntegration von Konfigurationsmechanismen für Xilinx-FPGA in das Linux-OS.MBMV237-2462010Conference and Workshop Papersunavailableconf/mbmv/KriestenHS10https://dblp.org/rec/conf/mbmv/KriestenHS10URL#4959299Jan LangerDimo PepelyashevUlrich HeinkelDeterminierung von Automaten bei der High-Level-Synthese von Operationseigenschaften.MBMV31-402010Conference and Workshop Papersunavailableconf/mbmv/LangerPH10https://dblp.org/rec/conf/mbmv/LangerPH10URL#4959300Christian MillerStefan KupferschmidBernd Becker 0001Exploiting Craig Interpolants in Bounded Model Checking for Incomplete Designs.MBMV77-862010Conference and Workshop Papersunavailableconf/mbmv/MillerKB10https://dblp.org/rec/conf/mbmv/MillerKB10URL#4959301Tobias NopperChristian MillerMatthew Lewis 0004Bernd Becker 0001Christoph Scholl 0001SAT Modulo BDD -- A Combined Verification Approach for Incomplete Designs.MBMV107-1162010Conference and Workshop Papersunavailableconf/mbmv/NopperMLBS10https://dblp.org/rec/conf/mbmv/NopperMLBS10URL#4959302Jiong OuPeter BrunmayrJan Haase 0001Christoph Grimm 0001Ein formales Modell für den Entwurf von flexiblen Kommunikationssystemen.MBMV207-2162010Conference and Workshop Papersunavailableconf/mbmv/OuBHG10https://dblp.org/rec/conf/mbmv/OuBHG10URL#4959303Georg PelzMonica RafailaFrom Requirements to Comprehensive Verification of Smart Power ICs.MBMV41-452010Conference and Workshop Papersunavailableconf/mbmv/PelzR10https://dblp.org/rec/conf/mbmv/PelzR10URL#4959304Uwe ProßKarl KröberUlrich HeinkelAbhängigkeitsanalyse und Parameterberechnung auf Spezifikationsebene.MBMV197-2062010Conference and Workshop Papersunavailableconf/mbmv/ProssKH10https://dblp.org/rec/conf/mbmv/ProssKH10URL#4959305Jens SchönherrAbstracting from Register-Transfer to Algorithmic Level for Verification.MBMV147-1562010Conference and Workshop Papersunavailableconf/mbmv/Schonherr10https://dblp.org/rec/conf/mbmv/Schonherr10URL#4959306Martin SchweikertHans EvekingVerwendung von UML Sequenzdiagrammen zur Spezifikation und Generierung von RTL Eigenschaftssätzen.MBMV177-1862010Conference and Workshop Papersunavailableconf/mbmv/SchweikertE10https://dblp.org/rec/conf/mbmv/SchweikertE10URL#4959307Stephan SeidelThomas KlotzUlrich DonathJürgen HaufeModellierung des Real-Time-Verhaltens von Steuerungen in der Automatisierungstechnik.MBMV157-1662010Conference and Workshop Papersunavailableconf/mbmv/SeidelKDH10https://dblp.org/rec/conf/mbmv/SeidelKDH10URL#4959308Abdulhadi ShoufanHagen StübingSorin A. HussInteractive Optimization of FPGA-based Systems-on-Chips.MBMV217-2262010Conference and Workshop Papersunavailableconf/mbmv/ShoufanSH10https://dblp.org/rec/conf/mbmv/ShoufanSH10URL#4959309Mathias SoekenRobert WilleMirco KuhlmannMartin GogollaRolf DrechslerVerifying UML/OCL Models Using Boolean Satisfiability.MBMV57-662010Conference and Workshop Papersunavailableconf/mbmv/SoekenWKGD10https://dblp.org/rec/conf/mbmv/SoekenWKGD10URL#4959310Max ThalmaierMinh D. NguyenMarkus WedlerDominik StoffelWolfgang KunzAnalyzing k-step induction to compute invariants for SAT-based property checking.MBMV87-962010Conference and Workshop Papersunavailableconf/mbmv/ThalmaierNWSK10https://dblp.org/rec/conf/mbmv/ThalmaierNWSK10URL#4959311Robert WilleSebastian OffermannRolf DrechslerSyReC: A Programming Language for Synthesis of Reversible Circuits.MBMV21-302010Conference and Workshop Papersunavailableconf/mbmv/WilleOD10https://dblp.org/rec/conf/mbmv/WilleOD10URL#4959312Manfred DietrichMethoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Dresden, Germany, February 22-24, 2010MBMVFraunhofer Verlag2010Editorshipunavailableconf/mbmv/2010https://dblp.org/rec/conf/mbmv/2010URL#4998838Markus Becker 0001Henning ZabelWolfgang Müller 0003Ulrich KiffmeierIntegration abstrakter RTOS-Simulation in den Entwurf eingebetteter automobiler E/E-Systeme.MBMV167-1762009Conference and Workshop Papersunavailableconf/mbmv/BeckerZMK09https://dblp.org/rec/conf/mbmv/BeckerZMK09URL#5182146Jens Brandt 0001Klaus Schneider 0001Adrian WillenbücherUsing IP Cores in Synchronous Languages.MBMV97-1062009Conference and Workshop Papersunavailableconf/mbmv/BrandtSW09https://dblp.org/rec/conf/mbmv/BrandtSW09URL#5182147Jens GladigauChristian HaubeltMartin StreubührJürgen TeichAxel SchneiderJoachim KnäbleinMichael LindigTestfallgenerierung für SystemC-Designs mit abstrakten Modellbeschreibungen.MBMV157-1662009Conference and Workshop Papersunavailableconf/mbmv/GladigauHSTSKL09https://dblp.org/rec/conf/mbmv/GladigauHSTSKL09URL#5182148Jürgen HaufeUlrich DonathEva FordranThomas KlotzBernd StraubeModellierung und Verifikation von Steuerungen in der Automatisierungstechnik.MBMV197-2062009Conference and Workshop Papersunavailableconf/mbmv/HaufeDFKS09https://dblp.org/rec/conf/mbmv/HaufeDFKS09URL#5182149Heiko HübertBenno StabernackPower Modeling of an Embedded RISC Core for Function-Accurate Energy Profiling.MBMV147-1562009Conference and Workshop Papersunavailableconf/mbmv/HubertS09https://dblp.org/rec/conf/mbmv/HubertS09URL#5182150Adán KohlerMartin RadetzkiModellierung und Simulation von Networks-on-Chip mit OSCI TLM2.MBMV207-2162009Conference and Workshop Papersunavailableconf/mbmv/KohlerR09https://dblp.org/rec/conf/mbmv/KohlerR09URL#5182151Stefan KupferschmidTino TeigeBernd Becker 0001Martin FränzleProofs of Unsatisfiability for mixed Boolean and Non-linear Arithmetic Constraint Formulae.MBMV27-362009Conference and Workshop Papersunavailableconf/mbmv/KupferschmidTBF09https://dblp.org/rec/conf/mbmv/KupferschmidTBF09URL#5182152Matthew Lewis 0004Tobias Schubert 0001Bernd Becker 0001QmiraXT - A Multithreaded QBF Solver.MBMV7-162009Conference and Workshop Papersunavailableconf/mbmv/LewisSB09https://dblp.org/rec/conf/mbmv/LewisSB09URL#5182153Daniel LüdtkeCarsten GremzowDietmar TutschAn Application-Optimized Network on Chip Platform.MBMV117-1262009Conference and Workshop Papersunavailableconf/mbmv/LudtkeGT09https://dblp.org/rec/conf/mbmv/LudtkeGT09URL#5182154Christian MillerTobias NopperChristoph Scholl 0001Symbolic CTL Model Checking for Incomplete Designs by Selecting Property-Specific Subsets of Local Component Assumptions.MBMV87-962009Conference and Workshop Papersunavailableconf/mbmv/MillerNS09https://dblp.org/rec/conf/mbmv/MillerNS09URL#5182155Nico MoserStefan HauserCarsten GremzowReduzierung der Kommunikation in TTA-Verbindungsnetzen mittels Laufzeitanalyse.MBMV107-1162009Conference and Workshop Papersunavailableconf/mbmv/MoserHG09https://dblp.org/rec/conf/mbmv/MoserHG09URL#5182156Minh D. NguyenMax ThalmaierMarkus WedlerDominik StoffelWolfgang KunzA Re-Use Methodology for SoC Protocol Compliance Verification.MBMV57-662009Conference and Workshop Papersunavailableconf/mbmv/NguyenTWSK09https://dblp.org/rec/conf/mbmv/NguyenTWSK09URL#5182157Martin OberkönigMartin SchickelHans EvekingQuantitative Qualitätsaussagen über Testbenches mittels formaler Eigenschaften.MBMV17-262009Conference and Workshop Papersunavailableconf/mbmv/OberkonigSE09https://dblp.org/rec/conf/mbmv/OberkonigSE09URL#5182158Florian PigorschChristoph Scholl 0001Using Implications for Optimizing State Set Representations of Linear Hybrid Systems.MBMV77-862009Conference and Workshop Papersunavailableconf/mbmv/PigorschS09https://dblp.org/rec/conf/mbmv/PigorschS09URL#5182159Uwe ProßChristian AdamBenjamin BergerUlrich HeinkelModellierung dynamisch partieller Rekonfiguration mit VPRS.MBMV177-1862009Conference and Workshop Papersunavailableconf/mbmv/ProssABH09https://dblp.org/rec/conf/mbmv/ProssABH09URL#5182160Monica RafailaChristian DeckerChristoph Grimm 0001Karsten EinwichThomas MarkwirthGeorg PelzNew Methods for System-level Verification using SystemC-AMS Extensions: Application to an Automotive ECU.MBMV217-2262009Conference and Workshop Papersunavailableconf/mbmv/RafailaDGEMP09https://dblp.org/rec/conf/mbmv/RafailaDGEMP09URL#5182161Herbert ReichlIvan N. NdipEntwurf von Aufbau- und Verbindungstechniken für die Elektromagnetische Zuverlässigkeit von Mikrosystemen unter Verwendung des M3-Ansatzes.MBMV1-22009Conference and Workshop Papersunavailableconf/mbmv/ReichlN09https://dblp.org/rec/conf/mbmv/ReichlN09URL#5182162Jens SchönherrEin gemeinsamer Ansatz für die formale und simulative Verifikation digitaler Schaltungsdesigns.MBMV37-462009Conference and Workshop Papersunavailableconf/mbmv/Schonherr09https://dblp.org/rec/conf/mbmv/Schonherr09URL#5182163Tobias SchwalbPhilipp GrafKlaus D. Müller-GlaserArchitektur für das echtzeitfähige Debugging ausführbarer Modelle auf rekonfigurierbarer Hardware.MBMV127-1362009Conference and Workshop Papersunavailableconf/mbmv/SchwalbGM09https://dblp.org/rec/conf/mbmv/SchwalbGM09URL#5182164Sven SlawinskiLutz ZachariasRobert DornJohann HauerErstellung und Verifizierung eines VHDL-AMS-Modells für einen kapazitiven Delta-Sigma-Modulator.MBMV227-2362009Conference and Workshop Papersunavailableconf/mbmv/SlawinskiZDH09https://dblp.org/rec/conf/mbmv/SlawinskiZDH09URL#5182165Raimund SönningChallenges and Methods in Verification of Complex Graphics Display Controllers.MBMV3-32009Conference and Workshop Papersunavailableconf/mbmv/Sonning09https://dblp.org/rec/conf/mbmv/Sonning09URL#5182166André SülflowGörschwin FeyCécile BraunsteinUlrich KühneRolf DrechslerIncreasing the Accuracy of SAT-based Debugging.MBMV47-562009Conference and Workshop Papersunavailableconf/mbmv/SulflowFBKD09https://dblp.org/rec/conf/mbmv/SulflowFBKD09URL#5182167Jan UerpmannChallenges in the Design of Micro-Processors and other Integrated Circuits.MBMV5-62009Conference and Workshop Papersunavailableconf/mbmv/Uerpmann09https://dblp.org/rec/conf/mbmv/Uerpmann09URL#5182168Yifan Wang 0001Ralf WunderlichStefan HeinenHans-Werner GrohEvent gesteuerte Modellierung analoger Frontends für die funktionale Verifikation des RF-SoCs.MBMV237-2462009Conference and Workshop Papersunavailableconf/mbmv/WangWHG09https://dblp.org/rec/conf/mbmv/WangWHG09URL#5182169Matthias WeberModel-Based Development in Automotive Electronics -- The EAST-ADL.MBMV4-42009Conference and Workshop Papersunavailableconf/mbmv/Weber09https://dblp.org/rec/conf/mbmv/Weber09URL#5182170Robert WilleDaniel GroßeD. Michael MillerRolf DrechslerEquivalence Checking of Reversible Circuits.MBMV67-762009Conference and Workshop Papersunavailableconf/mbmv/WilleGMD09https://dblp.org/rec/conf/mbmv/WilleGMD09URL#5182171Frank Winkler 0001Gerald KellOliver SchrapeHans GustatUlrich JagdholdHDL-Synthese und Simulation von Hochgeschwindigkeits-Digitalschaltungen mit gemischten CMOS- und ECL-Bibliotheken.MBMV137-1452009Conference and Workshop Papersunavailableconf/mbmv/WinklerKSGJ09https://dblp.org/rec/conf/mbmv/WinklerKSGJ09URL#5182172Martin ZabelThomas B. PreußerRainer G. SpallekHigh-Level Architecture Modelling Assisting the Processor Platform Development, Debugging and Simulation.MBMV187-1962009Conference and Workshop Papersunavailableconf/mbmv/ZabelPS09https://dblp.org/rec/conf/mbmv/ZabelPS09URL#5182173Carsten GremzowNico MoserMethoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Berlin, Germany, March 2-4, 2009MBMVUniversitätsbibliothek Berlin, Germany2009Editorshipunavailableconf/mbmv/2009https://dblp.org/rec/conf/mbmv/2009URL#5219567Jens Brandt 0001Klaus Schneider 0001Adrian WillenbücherHardware Acceleration for Model Checking.MBMV179-1872008Conference and Workshop Papersunavailableconf/mbmv/BrandtSW08https://dblp.org/rec/conf/mbmv/BrandtSW08URL#5393251Jens GladigauFrank BlendingerChristian HaubeltJürgen TeichSymbolische Modellprüfung Aktor-orientierter High-level SystemC-Modelle mit Intervalldiagrammen.MBMV109-1182008Conference and Workshop Papersunavailableconf/mbmv/GladigauBHT08https://dblp.org/rec/conf/mbmv/GladigauBHT08URL#5393252Ralph GörgenFrank OppenheimerAndreas SchallenbergWolfgang NebelAnalyse und Optimierung von dynamisch rekonfigurierbaren Systemen mittels Ereignisvisualisierung.MBMV1-102008Conference and Workshop Papersunavailableconf/mbmv/GorgenOSN08https://dblp.org/rec/conf/mbmv/GorgenOSN08URL#5393253Carsten GremzowSimulation and Profiling of Virtual Instruction Set Architectures for HW/SW Co Design.MBMV149-1582008Conference and Workshop Papersunavailableconf/mbmv/Gremzow08https://dblp.org/rec/conf/mbmv/Gremzow08URL#5393254Daniel GroßeRobert WilleUlrich KühneRolf DrechslerUsing Contradiction Analysis for Antecedent Debugging in Bounded Model Checking.MBMV169-1782008Conference and Workshop Papersunavailableconf/mbmv/GrosseWKD08https://dblp.org/rec/conf/mbmv/GrosseWKD08URL#5393255Frank HannigHolger RuckdeschelJürgen TeichThe PAULA Language for Designing Multi-Dimensional Dataflow-Intensive Applications.MBMV129-1382008Conference and Workshop Papersunavailableconf/mbmv/HannigRT08https://dblp.org/rec/conf/mbmv/HannigRT08URL#5393256Henning KleenFrank OppenheimerWolfgang NebelEffizienzanalyse synthetisierter Hardware-Software-Kommunikation am Beispiel eines hardwarebeschleunigten MPEG-Audio-Dekoders.MBMV11-202008Conference and Workshop Papersunavailableconf/mbmv/KleenON08https://dblp.org/rec/conf/mbmv/KleenON08URL#5393257Benjamin LutzChristian KöllnerKlaus D. Müller-GlaserEine durchgängige und werkzeuggestützte Entwicklungsumgebung für eingebettete Hardware/Software Systeme.MBMV71-802008Conference and Workshop Papersunavailableconf/mbmv/LutzKM08https://dblp.org/rec/conf/mbmv/LutzKM08URL#5393258Valerij MatrosePlatzierverfahren zur effizienten Nutzung der lokalen Verdrahtungsressourcen hierarchischer FPGA-Architekturen.MBMV91-982008Conference and Workshop Papersunavailableconf/mbmv/Matrose08https://dblp.org/rec/conf/mbmv/Matrose08URL#5393259Andreas MorgensternKlaus Schneider 0001Sven LambertiGenerating Deterministic $\omega$-Automata for most LTL Formulas by the Breakpoint Construction.MBMV119-1282008Conference and Workshop Papersunavailableconf/mbmv/MorgensternSL08https://dblp.org/rec/conf/mbmv/MorgensternSL08URL#5393260Matthias Müller 0004Joachim GerlachWolfgang RosenstielAbstrakte Modellierung von Hardware/Software-Systemen unter Berücksichtigung von RTOS-Funktionalität.MBMV21-302008Conference and Workshop Papersunavailableconf/mbmv/MullerGR08https://dblp.org/rec/conf/mbmv/MullerGR08URL#5393261Martin OberkönigMartin SchickelHans EvekingEine quantitative Vollständigkeitsanalyse für Eigenschaftssätze.MBMV41-502008Conference and Workshop Papersunavailableconf/mbmv/OberkonigSE08https://dblp.org/rec/conf/mbmv/OberkonigSE08URL#5393262Evgeny PavlenkoMarkus WedlerDominik StoffelWolfgang KunzOliver WienandEvgeny KaribaevModeling of Custom-Designed Arithmetic Components for ABL Normalization.MBMV51-602008Conference and Workshop Papersunavailableconf/mbmv/PavlenkoWSKWK08https://dblp.org/rec/conf/mbmv/PavlenkoWSKWK08URL#5393263Bernard SchmidtSlava BulachKatharina WeinbergerMarkus WedlerFormale Verifikation einer Hardware-Implementierung des LIN-Protokoll Kontrollers.MBMV61-702008Conference and Workshop Papersunavailableconf/mbmv/SchmidtBWW08https://dblp.org/rec/conf/mbmv/SchmidtBWW08URL#5393264Martin StreubührMichael JäntschChristian HaubeltJürgen TeichAxel SchneiderSemi-Automatic Generation of mixed Hardware/Software Prototypes from Simulink Models.MBMV139-1482008Conference and Workshop Papersunavailableconf/mbmv/StreubuhrJHTS08https://dblp.org/rec/conf/mbmv/StreubuhrJHTS08URL#5393265André SülflowGörschwin FeyRoderick BloemRolf DrechslerDebugging Design Errors by Using Unsatisfiable Cores.MBMV159-1682008Conference and Workshop Papersunavailableconf/mbmv/SulflowFBD08https://dblp.org/rec/conf/mbmv/SulflowFBD08URL#5393266Michael VogelMario SchölzelAutomatic Generation of Cycle Accurate SystemC Models for Application Specific Clustered VLIW Processors.MBMV81-902008Conference and Workshop Papersunavailableconf/mbmv/VogelS08https://dblp.org/rec/conf/mbmv/VogelS08URL#5393267Ralf Wimmer 0001Alexander KortusMarc HerbstrittBernd Becker 0001The Demand for Reliability in Probabilistic Verification.MBMV99-1082008Conference and Workshop Papersunavailableconf/mbmv/WimmerKHB08https://dblp.org/rec/conf/mbmv/WimmerKHB08URL#5393268Henning ZabelWolfgang Müller 0003Präzises Interrupt Scheduling in abstrakten RTOS Modellen in SystemC.MBMV31-392008Conference and Workshop Papersunavailableconf/mbmv/Zabel008https://dblp.org/rec/conf/mbmv/Zabel008URL#5393269Christoph Scholl 0001Stefan DischMethoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Freiburg, Germany, March 3-5, 2008MBMVShaker2008Editorshipunavailableconf/mbmv/2008https://dblp.org/rec/conf/mbmv/2008URL#5428686Bernd Becker 0001AVACS -- Automatic Verification and Analysis of Complex Systems.MBMV79-802007Conference and Workshop Papersunavailableconf/mbmv/Becker07https://dblp.org/rec/conf/mbmv/Becker07URL#5587538Claudia BlankEmployment of Property Checking for Functional Hardware Verification in an Industrial Setting.MBMV191-1922007Conference and Workshop Papersunavailableconf/mbmv/Blank07https://dblp.org/rec/conf/mbmv/Blank07URL#5587539Axel G. BraunJoachim GerlachWolfgang RosenstielEine SystemC-basierte Heuristik zur Performanzoptimierung datenflussorientierter Applikationen.MBMV49-582007Conference and Workshop Papersunavailableconf/mbmv/BraunGR07https://dblp.org/rec/conf/mbmv/BraunGR07URL#5587540Martin Braun 0001Minh D. NguyenHans EvekingMartin SchickelWolfgang KunzMethoden zur Verifikation von Kommunikationsstrukturen.MBMV223-2322007Conference and Workshop Papersunavailableconf/mbmv/BraunNESK07https://dblp.org/rec/conf/mbmv/BraunNESK07URL#5587541Rainer DorschJürgen RufTransaction Modeling and RTL Simulation Analysis.MBMV1-82007Conference and Workshop Papersunavailableconf/mbmv/DorschR07https://dblp.org/rec/conf/mbmv/DorschR07URL#5587542Görschwin FeyDaniel GroßeStephan EggersglüßRobert WilleRolf DrechslerFormal Verification on the Word Level using SAT-like Proof Techniques.MBMV81-902007Conference and Workshop Papersunavailableconf/mbmv/FeyGEWD07https://dblp.org/rec/conf/mbmv/FeyGEWD07URL#5587543Raffaella GentiliniKlaus Schneider 0001Alexander DreyerCombining Interval Arithmetic and Three-Valued Temporal Logics for the Verification of Analog Systems.MBMV121-1302007Conference and Workshop Papersunavailableconf/mbmv/GentiliniSD07https://dblp.org/rec/conf/mbmv/GentiliniSD07URL#5587544Christoph Grimm 0001Rüdiger SchrollFlorian BrameKlaus WaldschmidtTop-Down Design analog/digitaler Systeme mit SystemC-AMS.MBMV131-1402007Conference and Workshop Papersunavailableconf/mbmv/GrimmSBW07https://dblp.org/rec/conf/mbmv/GrimmSBW07URL#5587545Daniel JelkmannKarsten AlbersFrank SlomkaImproved Feasibility Tests for Asynchronous Real-Time Periodic Task Sets.MBMV69-782007Conference and Workshop Papersunavailableconf/mbmv/JelkmannAS07https://dblp.org/rec/conf/mbmv/JelkmannAS07URL#5587546Reimund KlemmJavier Prieto SabugoHendrik AhlendorfGerhard P. FettweisUsing LISATek for the Design of an ASIP Core including Floating Point Operations.MBMV161-1692007Conference and Workshop Papersunavailableconf/mbmv/KlemmSAF07https://dblp.org/rec/conf/mbmv/KlemmSAF07URL#5587547Stephan KubischHarald WidigerRonald HechtDirk TimmermannMartin SiemrothArchitektur einer flexiblen, wiederverwendbaren Testbench zur Verifikation paketverarbeitender Hardware in SystemC.MBMV9-182007Conference and Workshop Papersunavailableconf/mbmv/KubischWHTS07https://dblp.org/rec/conf/mbmv/KubischWHTS07URL#5587548Stefan LämmermannJörg BehrendRoland J. WeissJürgen RufThomas KropfWolfgang RosenstielUML/SysML-Systemanalyse zur Generierung von formalen Verifikationseigenschaften für verschiedene Abstraktionsebenen.MBMV29-382007Conference and Workshop Papersunavailableconf/mbmv/LammermannBWRKR07https://dblp.org/rec/conf/mbmv/LammermannBWRKR07URL#5587549Djones LettninPradeep Kumar NallaJürgen RufRoland J. WeissAxel G. BraunJoachim GerlachThomas KropfWolfgang RosenstielSemiformal Verification of Temporal Properties in Embedded Software.MBMV19-282007Conference and Workshop Papersunavailableconf/mbmv/LettninNRWBGKR07https://dblp.org/rec/conf/mbmv/LettninNRWBGKR07URL#5587550Erik MarkertSven KühnJan LangerGöran HerrmannUlrich HeinkelEin SystemC-AMS nach VHDL-AMS Konverter.MBMV151-1602007Conference and Workshop Papersunavailableconf/mbmv/MarkertKLHH07https://dblp.org/rec/conf/mbmv/MarkertKLHH07URL#5587551Valerij MatroseClusteringverfahren zur effektiven Nutzung der Logikressourcen hierarchischer FPGA-Architekturen.MBMV263-2722007Conference and Workshop Papersunavailableconf/mbmv/Matrose07https://dblp.org/rec/conf/mbmv/Matrose07URL#5587552Friedrich Mayer-LindenbergA design language supporting mixed processor and FPGA systems.MBMV233-2422007Conference and Workshop Papersunavailableconf/mbmv/Mayer-Lindenberg07https://dblp.org/rec/conf/mbmv/Mayer-Lindenberg07URL#5587553Silvio MiseraAndré SieberHardwarenahe Fehlersimulation mit effektiven SystemC-Modellen.MBMV39-482007Conference and Workshop Papersunavailableconf/mbmv/MiseraS07https://dblp.org/rec/conf/mbmv/MiseraS07URL#5587554Tobias NopperChristoph Scholl 0001Counterexample Generation for Incomplete Designs.MBMV193-2022007Conference and Workshop Papersunavailableconf/mbmv/NopperS07https://dblp.org/rec/conf/mbmv/NopperS07URL#5587555Evgeny PavlenkoMarkus WedlerDominik StoffelWolfgang KunzArithmetic Constraints in SAT-based Property Checking.MBMV91-1002007Conference and Workshop Papersunavailableconf/mbmv/PavlenkoWSK07https://dblp.org/rec/conf/mbmv/PavlenkoWSK07URL#5587556Oliver PiepenstockEnhanced VerilogA VCO Model for PLL Lock-in Simulations.MBMV141-1502007Conference and Workshop Papersunavailableconf/mbmv/Piepenstock07https://dblp.org/rec/conf/mbmv/Piepenstock07URL#5587557Martin RadetzkiModellierung auf der Transaktionsebene unter Nutzung des Entwurfsmusters des aktiven Objekts.MBMV181-1902007Conference and Workshop Papersunavailableconf/mbmv/Radetzki07https://dblp.org/rec/conf/mbmv/Radetzki07URL#5587558Philipp ReinkemeierKim GrüttnerWolfgang NebelEine Fallstudie zur dynamischen Rekonfiguration von Hardware: "Pain or Gain?".MBMV243-2522007Conference and Workshop Papersunavailableconf/mbmv/ReinkemeierGN07https://dblp.org/rec/conf/mbmv/ReinkemeierGN07URL#5587559Jens SchönherrEin Schritt zur formalen Verifikation auf der Transaktionsebene.MBMV213-2222007Conference and Workshop Papersunavailableconf/mbmv/Schonherr07https://dblp.org/rec/conf/mbmv/Schonherr07URL#5587560Abdulhadi ShoufanRalf Laue 0002Sorin A. HussSecure Multicast Rekeying: A Case Study for HW/SW-Codesign.MBMV171-1802007Conference and Workshop Papersunavailableconf/mbmv/Shoufan0H07https://dblp.org/rec/conf/mbmv/Shoufan0H07URL#5587561Martin StreubührCarsten RiedelChristian HaubeltJürgen TeichSystem Level Modeling and Performance Simulation for Dynamic Reconfigurable Computing Systems in SystemC.MBMV59-682007Conference and Workshop Papersunavailableconf/mbmv/StreubuhrRHT07https://dblp.org/rec/conf/mbmv/StreubuhrRHT07URL#5587562André SülflowGörschwin FeyRolf DrechslerVerbesserte SAT basierte Fehlerdiagnose durch Widerspruchanalyse.MBMV101-1102007Conference and Workshop Papersunavailableconf/mbmv/SulflowFD07https://dblp.org/rec/conf/mbmv/SulflowFD07URL#5587563Katharina WeinbergerSlava BulachWolfgang RosenstielProperty Set Exhaustiveness Estimation Approach for BMC-based Formal Hardware Verification.MBMV111-1192007Conference and Workshop Papersunavailableconf/mbmv/WeinbergerBR07https://dblp.org/rec/conf/mbmv/WeinbergerBR07URL#5587564Ralf Wimmer 0001Marc HerbstrittBernd Becker 0001Forwarding, Splitting, and Block Ordering to Optimize BDD-based Bisimulation Computation.MBMV203-2122007Conference and Workshop Papersunavailableconf/mbmv/WimmerHB07https://dblp.org/rec/conf/mbmv/WimmerHB07URL#5587565Peter ZipfYang QiaoManfred GlesnerEin Beitrag zur automatischen Erzeugung dynamisch rekonfigurierbarer Hardwarestrukturen.MBMV253-2622007Conference and Workshop Papersunavailableconf/mbmv/ZipfQG07https://dblp.org/rec/conf/mbmv/ZipfQG07URL#5587566Christian HaubeltJürgen TeichMethoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Erlangen, Germany, March 5-7, 2007MBMVBerichte aus der InformatikShaker2007Editorshipunavailableconf/mbmv/2007https://dblp.org/rec/conf/mbmv/2007URL#5621545Erika ÁbrahámMarc HerbstrittBernd Becker 0001Martin SteffenMemory-aware Bounded Model Checking for Linear Hybrid Systems.MBMV153-1622006Conference and Workshop Papersunavailableconf/mbmv/AbrahamHBS06https://dblp.org/rec/conf/mbmv/AbrahamHBS06URL#5769942Paul DuplysRoland J. WeissJürgen RufThomas KropfWolfgang RosenstielMonitoring-based Formal Hardware Verification.MBMV217-2212006Conference and Workshop Papersunavailableconf/mbmv/DuplysWRKR06https://dblp.org/rec/conf/mbmv/DuplysWRKR06URL#5769943Andreas EhrenfriedDaniel ScholzTobias WelpAnwendungsmöglichkeiten von Bounded Model Checking und affiner Arithmetik für die Verifikation von Analogschaltungen.MBMV114-1212006Conference and Workshop Papersunavailableconf/mbmv/EhrenfriedSW06https://dblp.org/rec/conf/mbmv/EhrenfriedSW06URL#5769944Görschwin FeyRolf DrechslerSAT-based Calculation of Source Code Coverage for BMC.MBMV163-1702006Conference and Workshop Papersunavailableconf/mbmv/FeyD06https://dblp.org/rec/conf/mbmv/FeyD06URL#5769945Stefan FörsterVerifying Behavioural Extension of Components with Dynamically Evolving Interfaces.MBMV145-1522006Conference and Workshop Papersunavailableconf/mbmv/Forster06https://dblp.org/rec/conf/mbmv/Forster06URL#5769946Martin FreibotheJens DögeTorsten CoymStefan LudwigBernd StraubeErnst KockModellierung des dynamischen Verhaltens nichtlinearer analoger Komponenten für die semi-formale Mixed-Signal-Verifikation.MBMV95-1052006Conference and Workshop Papersunavailableconf/mbmv/FreibotheDCLSK06https://dblp.org/rec/conf/mbmv/FreibotheDCLSK06URL#5769947Darius GrabowskiChristoph Grimm 0001Erich BarkeEin Verfahren zur effizienten Analyse von Schaltungen mit Parametervarianzen.MBMV181-1902006Conference and Workshop Papersunavailableconf/mbmv/GrabowskiGB06https://dblp.org/rec/conf/mbmv/GrabowskiGB06URL#5769948Kim GrüttnerCornelia GrabbeFrank OppenheimerWolfgang NebelModelling and Synthesis of Communication Using OSSS-Channels.MBMV38-472006Conference and Workshop Papersunavailableconf/mbmv/GruttnerGON06https://dblp.org/rec/conf/mbmv/GruttnerGON06URL#5769949Wolfram HardtMathias SporerEin Metamodell für eingebettete Systeme.MBMV255-2602006Conference and Workshop Papersunavailableconf/mbmv/HardtS06https://dblp.org/rec/conf/mbmv/HardtS06URL#5769950Andy HeinigMario SchölzelZeitbeschränkte Clusterung zur Design-Space-Exploration geclusterter VLIW-Prozessoren.MBMV319-3282006Conference and Workshop Papersunavailableconf/mbmv/HeinigS06https://dblp.org/rec/conf/mbmv/HeinigS06URL#5769951Wilhelm HeupkeChristoph Grimm 0001Klaus WaldschmidtSemi-symbolische Modellierung von Abweichungen.MBMV173-1802006Conference and Workshop Papersunavailableconf/mbmv/HeupkeGW06https://dblp.org/rec/conf/mbmv/HeupkeGW06URL#5769952Hermann von IssendorffÜber die formale Beschreibung räumlicher Netze.MBMV203-2132006Conference and Workshop Papersunavailableconf/mbmv/Issendorff06https://dblp.org/rec/conf/mbmv/Issendorff06URL#5769953Christoph JäschkeRalf WinkelmannJohannes KöstersControl Register Specification and Verification in Complex Systems.MBMV349-3582006Conference and Workshop Papersunavailableconf/mbmv/JaschkeWK06https://dblp.org/rec/conf/mbmv/JaschkeWK06URL#5769954Alexander JesserMarkus WedlerLars HedrichWolfgang KunzA case study on applying bounded model checking to analog circuit verification.MBMV106-1132006Conference and Workshop Papersunavailableconf/mbmv/JesserWHK06https://dblp.org/rec/conf/mbmv/JesserWHK06URL#5769955Iyad KebaisySven DomannBernd MeinerzhagenPräzise Modellierung und Parameteranpassung eines 5, 2 GHz LNA für WLAN-Anwendungen.MBMV329-3362006Conference and Workshop Papersunavailableconf/mbmv/KebaisyDM06https://dblp.org/rec/conf/mbmv/KebaisyDM06URL#5769956Ralf KlausenLars HedrichErich BarkeVermeidung fehlerhafter Verifikations-Ergebnisse beim Äquivalenz-Vergleich nichtlinearer analoger Schaltungen.MBMV122-1312006Conference and Workshop Papersunavailableconf/mbmv/KlausenHB06https://dblp.org/rec/conf/mbmv/KlausenHB06URL#5769957Sascha KneipWalter AnheierVergleich und Optimierung von Algorithmen zur Modulo-Multiplikation auf Smartcards.MBMV292-3012006Conference and Workshop Papersunavailableconf/mbmv/KneipA06https://dblp.org/rec/conf/mbmv/KneipA06URL#5769958Matthias Krause 0002Oliver Bringmann 0001Wolfgang RosenstielCommunication Refinement and Target Software Generation using SystemC.MBMV30-372006Conference and Workshop Papersunavailableconf/mbmv/KrauseBR06https://dblp.org/rec/conf/mbmv/KrauseBR06URL#5769959Alexey KupriyanovFrank HannigDmitrij KisslerJürgen TeichRainer SchafferRenate MerkerAn Architecture Description Language for Massively Parallel Processor Architectures.MBMV11-202006Conference and Workshop Papersunavailableconf/mbmv/KupriyanovHKTSM06https://dblp.org/rec/conf/mbmv/KupriyanovHKTSM06URL#5769960Stefan LämmermannRoland J. WeissJürgen RufThomas KropfWolfgang RosenstielAutomatische Eigenschaftsextraktion auf Systemebene aus SystemC Modellen.MBMV222-2262006Conference and Workshop Papersunavailableconf/mbmv/LammermannWRKR06https://dblp.org/rec/conf/mbmv/LammermannWRKR06URL#5769961Valerij MatroseFlächenplanung für FPGA-Architekturen mit heterogenen Verdrahtungsressourcen.MBMV284-2912006Conference and Workshop Papersunavailableconf/mbmv/Matrose06https://dblp.org/rec/conf/mbmv/Matrose06URL#5769962Nico MoserCarsten GremzowMatthias MengeHans-Ulrich PostDecompilationsbasierte High-Level-Synthese.MBMV77-842006Conference and Workshop Papersunavailableconf/mbmv/MoserGMP06https://dblp.org/rec/conf/mbmv/MoserGMP06URL#5769963Beate MurankoRolf DrechslerTechnische Dokumentation von Soft- und Hardware-Systemen: Die vergessene Welt.MBMV227-2312006Conference and Workshop Papersunavailableconf/mbmv/MurankoD06https://dblp.org/rec/conf/mbmv/MurankoD06URL#5769964Ingmar NeumannModelling Synchronous Multi-Clock Circuits for Retiming.MBMV69-762006Conference and Workshop Papersunavailableconf/mbmv/Neumann06https://dblp.org/rec/conf/mbmv/Neumann06URL#5769965Bernhard NiemannChristian HaubeltAssertion-Based Verification of Transaction Level Models.MBMV232-2362006Conference and Workshop Papersunavailableconf/mbmv/NiemannH06https://dblp.org/rec/conf/mbmv/NiemannH06URL#5769966Florian PigorschChristoph Scholl 0001Stefan DischAdvanced Unbounded CTL Model Checking By Using AIGs, BDD Sweeping, and Quantifier Scheduling.MBMV135-1442006Conference and Workshop Papersunavailableconf/mbmv/PigorschSD06https://dblp.org/rec/conf/mbmv/PigorschSD06URL#5769967Daniel PlatteShangjing JingRalf SommerErich BarkeAnsätze zur Verbesserung der Simulationsperformance automatisch generierter analoger Verhaltensmodelle.MBMV191-2002006Conference and Workshop Papersunavailableconf/mbmv/PlatteJSB06https://dblp.org/rec/conf/mbmv/PlatteJSB06URL#5769968Tim SanderWolfgang HessSorin A. HussKonzept zur Taskmigration auf heterogenen rekonfigurierbaren Rechenplattformen.MBMV237-2412006Conference and Workshop Papersunavailableconf/mbmv/SanderHH06https://dblp.org/rec/conf/mbmv/SanderHH06URL#5769969Axel SchneiderThomas BluhmTobias RennerUlrich HeinkelJoachim KnäbleinReynaldo ZavalaFormale Spezifikation und Verifikation abstrakter Beschreibungen von Telekommunikationsprotokollen.MBMV339-3482006Conference and Workshop Papersunavailableconf/mbmv/SchneiderBRHKZ06https://dblp.org/rec/conf/mbmv/SchneiderBRHKZ06URL#5769970Klaus Schneider 0001Tobias SchüleA Framework for Verifying and Implementing Embedded Systems.MBMV242-2472006Conference and Workshop Papersunavailableconf/mbmv/SchneiderS06https://dblp.org/rec/conf/mbmv/SchneiderS06URL#5769971Marius SidaGuido ClemensEfficient Top Down Design and Verification of a Bluetooth Transceiver using the IEEE 1076.1 Language Standard.MBMV311-3182006Conference and Workshop Papersunavailableconf/mbmv/SidaC06https://dblp.org/rec/conf/mbmv/SidaC06URL#5769972Markus SiegleVerifying Finite State Machines in Probabilistic Environments.MBMV248-2542006Conference and Workshop Papersunavailableconf/mbmv/Siegle06https://dblp.org/rec/conf/mbmv/Siegle06URL#5769973Frank SillClaas CorneliusDirk TimmermannReduzierung des Leckstromverbrauchs mit gemischten Gattern in Deep Submicron Technologien.MBMV275-2832006Conference and Workshop Papersunavailableconf/mbmv/SillCT06https://dblp.org/rec/conf/mbmv/SillCT06URL#5769974Øyvind StrømVerification and validation of Atmel's new 32 bit AVR microprocessor.MBMV305-3082006Conference and Workshop Papersunavailableconf/mbmv/Strom06https://dblp.org/rec/conf/mbmv/Strom06URL#5769975Alain VachouxAnalog and Mixed-Signal Extensions to SystemC.MBMV3-82006Conference and Workshop Papersunavailableconf/mbmv/Vachoux06https://dblp.org/rec/conf/mbmv/Vachoux06URL#5769976Martin VersenAchim SchrammDaewon LeeRonny SchneiderAddress Decoder Test and Verification by Generalization of Application Fail Sequences.MBMV261-2652006Conference and Workshop Papersunavailableconf/mbmv/VersenSLS06https://dblp.org/rec/conf/mbmv/VersenSLS06URL#5769977Axel VickHelmut RossmannHeinrich Theodor VierhausTiming-/Power-getriebener Layout-Entwurf für Zellen-basierte Digitalschaltungen.MBMV61-682006Conference and Workshop Papersunavailableconf/mbmv/VickRV06https://dblp.org/rec/conf/mbmv/VickRV06URL#5769978Alexander ViehlOliver Bringmann 0001Wolfgang RosenstielVirtual Prototyping und frühe Evaluierung von Systems-on-Chip mit UML2 und SysML.MBMV266-2702006Conference and Workshop Papersunavailableconf/mbmv/ViehlBR06https://dblp.org/rec/conf/mbmv/ViehlBR06URL#5769979Axel WeißFrank Winkler 0001Entwurf Global Asynchroner Lokal Synchroner Strukturen auf der Basis einer deklarativen Beschreibung mit XML.MBMV21-292006Conference and Workshop Papersunavailableconf/mbmv/WeissW06https://dblp.org/rec/conf/mbmv/WeissW06URL#5769980Klaus WinkelmannGoing Beyond Assertions.MBMV87-912006Conference and Workshop Papersunavailableconf/mbmv/Winkelmann06https://dblp.org/rec/conf/mbmv/Winkelmann06URL#5769981Roberto M. ZillerVerallgemeinerte Überwachersynthese.MBMV271-2712006Conference and Workshop Papersunavailableconf/mbmv/Ziller06https://dblp.org/rec/conf/mbmv/Ziller06URL#5769982Roberto M. ZillerDetlef SchmidErstellung korrekter Spezifikationen für diskrete Systeme.MBMV359-3682006Conference and Workshop Papersunavailableconf/mbmv/ZillerS06https://dblp.org/rec/conf/mbmv/ZillerS06URL#5769983Peter ZipfVolker HampelManfred GlesnerThilo PionteckEine Scheduling Heuristik zur Minimierung der Verlustleistung.MBMV51-602006Conference and Workshop Papersunavailableconf/mbmv/ZipfHGP06https://dblp.org/rec/conf/mbmv/ZipfHGP06URL#5769984Bernd StraubeMartin FreibotheMethoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Dresden, Germany, February 20-22, 2006MBMVFraunhofer Institut für Integrierte Schaltungen2006Editorshipunavailableconf/mbmv/2006https://dblp.org/rec/conf/mbmv/2006URL#5799635Bernd Becker 0001Markus BehleFriedrich EisenbrandMartin FränzleMarc HerbstrittChristian HerdeJörg Hoffmann 0001Daniel KröningBernhard NebelIlia PolianRalf Wimmer 0001Bounded Model Checking and Inductive Verification of Hybrid Discrete-continuous Systems.MBMV65-752004Conference and Workshop Papersunavailableconf/mbmv/BeckerBEFHHHKNPW04https://dblp.org/rec/conf/mbmv/BeckerBEFHHHKNPW04URL#6071631Thomas BeierleinDominik FröhlichBernd SteinbachA Model-Based Approach to System-Level Co-Design.MBMV86-952004Conference and Workshop Papersunavailableconf/mbmv/BeierleinFS04https://dblp.org/rec/conf/mbmv/BeierleinFS04URL#6071632Rolf DrechslerUsing Synthesis Techniques in SAT Solvers.MBMV165-1732004Conference and Workshop Papersunavailableconf/mbmv/Drechsler04https://dblp.org/rec/conf/mbmv/Drechsler04URL#6071633Rolf DrechslerWolfgang Günther 0001Burkhard StubertEfficient (Non-)Reachability Analysis of Counterexamples.MBMV250-2592004Conference and Workshop Papersunavailableconf/mbmv/DrechslerGS04https://dblp.org/rec/conf/mbmv/DrechslerGS04URL#6071634Vesselka DuridanovaThorsten HummelOlga FenglerWolfgang Fengler 0001Verifikation von Spezifikationsmodellen mit Intervall-Petri-Netzen.MBMV184-1932004Conference and Workshop Papersunavailableconf/mbmv/DuridanovaHFF04https://dblp.org/rec/conf/mbmv/DuridanovaHFF04URL#6071635Rüdiger EbendtRolf DrechslerA Tight Lower Bound for Dynamic BDD Reordering.MBMV233-2422004Conference and Workshop Papersunavailableconf/mbmv/EbendtD04https://dblp.org/rec/conf/mbmv/EbendtD04URL#6071636Meinrad FiedlerEin Ubersetzungsverfahren von Verilog-Kausalspezifikationen in Signalflankengraph-basierte Spezifikationen zum Entwurf asynchroner Schaltwerke.MBMV194-2032004Conference and Workshop Papersunavailableconf/mbmv/Fiedler04https://dblp.org/rec/conf/mbmv/Fiedler04URL#6071637Patrick GroeneveldPhysical Synthesis: its struggle with Moore's law.MBMV21-232004Conference and Workshop Papersunavailableconf/mbmv/Groeneveld04https://dblp.org/rec/conf/mbmv/Groeneveld04URL#6071638Wolfgang Günther 0001Stefan HörethSome Common Synthesis-Simulation-Mismatches.MBMV127-1362004Conference and Workshop Papersunavailableconf/mbmv/GuntherH04https://dblp.org/rec/conf/mbmv/GuntherH04URL#6071639Jan GutscheHans-Ulrich PostErhöhung der Synthesegenauigkeit durch Sprachraumerweiterung synthesefähiger sequentieller VHDL-Beschreibungen.MBMV137-1462004Conference and Workshop Papersunavailableconf/mbmv/GutscheP04https://dblp.org/rec/conf/mbmv/GutscheP04URL#6071640Joachim HorchAutomatisches Verstärken und Beweisen von Invarianten mit Hilfe von Gegenbeispielen.MBMV76-852004Conference and Workshop Papersunavailableconf/mbmv/Horch04https://dblp.org/rec/conf/mbmv/Horch04URL#6071641Stefan HörethDebugging and Diagnosis in Equivalence Checking of ASICs.MBMV232-2322004Conference and Workshop Papersunavailableconf/mbmv/Horeth04https://dblp.org/rec/conf/mbmv/Horeth04URL#6071642Christoph JäschkeZoltán HidvégiWolfgang RösnerFaust2 -- A Processor High-Level Modeling Framework.MBMV11-202004Conference and Workshop Papersunavailableconf/mbmv/JaschkeHR04https://dblp.org/rec/conf/mbmv/JaschkeHR04URL#6071643Kai KappViktor K. SabelfeldScheduling of Control Flow Intensive Behavioral Descriptions in Formal Synthesis.MBMV204-2132004Conference and Workshop Papersunavailableconf/mbmv/KappS04https://dblp.org/rec/conf/mbmv/KappS04URL#6071644Claudia KretzschmarRobert SiegmundDietmar Müller 0001Adaptive Bus Line Grouping for Power Efficient Data Transfer over Wide System Buses.MBMV44-522004Conference and Workshop Papersunavailableconf/mbmv/KretzschmarSM04https://dblp.org/rec/conf/mbmv/KretzschmarSM04URL#6071645Karsten-O. LauxMarc Michael FeldHadie - Ein portierbarer Mikrokernel für eingebettete Systeme.MBMV174-1832004Conference and Workshop Papersunavailableconf/mbmv/LauxF04https://dblp.org/rec/conf/mbmv/LauxF04URL#6071646Matthew D. T. LewisTobias Schubert 0001Bernd Becker 0001Early Conflict Detection Based SAT Solving.MBMV243-2492004Conference and Workshop Papersunavailableconf/mbmv/LewisSB04https://dblp.org/rec/conf/mbmv/LewisSB04URL#6071647Tudor MurganMihail PetrovMateusz MajerPeter ZipfManfred GlesnerUlrich HeinkelFlexible Overhead Processing Architectures for G.709 Optical Transport Networks.MBMV156-1642004Conference and Workshop Papersunavailableconf/mbmv/MurganPMZGH04https://dblp.org/rec/conf/mbmv/MurganPMZGH04URL#6071648Ingmar NeumannDominik StoffelKolja SulimmaMichel R. C. M. BerkelaarWolfgang KunzLayout Driven Optimization of Datapath Circuits using Arithmetic Reasoning.MBMV24-332004Conference and Workshop Papersunavailableconf/mbmv/NeumannSSBK04https://dblp.org/rec/conf/mbmv/NeumannSSBK04URL#6071649Jan-Hendrik OetjensJoachim GerlachWolfgang RosenstielEin XML-basierter Ansatz zur flexiblen Darstellung und Transformation von Schaltungsbeschreibungen.MBMV116-1252004Conference and Workshop Papersunavailableconf/mbmv/OetjensGR04https://dblp.org/rec/conf/mbmv/OetjensGR04URL#6071650Georg PelzEntwurfs-Methodik für Automobil-Elektronik.MBMV53-532004Conference and Workshop Papersunavailableconf/mbmv/Pelz04https://dblp.org/rec/conf/mbmv/Pelz04URL#6071651Prakash Mohan PeranandamRoland J. WeissJürgen RufThomas KropfTransactional Level Verification and Coverage Metrics by Means of Symbolic Simulation.MBMV260-2692004Conference and Workshop Papersunavailableconf/mbmv/PeranandamWRK04https://dblp.org/rec/conf/mbmv/PeranandamWRK04URL#6071652Razvan RacuKai Richter 0001Rolf ErnstCalculating Task Output Event Models to Reduce Distributed System Cost.MBMV1-102004Conference and Workshop Papersunavailableconf/mbmv/RacuRE04https://dblp.org/rec/conf/mbmv/RacuRE04URL#6071653Achim RettbergFlorian Dittmann 0001Thomas Lehmann 0001Mauro Cesar ZanellaA New High-Level Synthesis Approach of a Synchronous Bit-Serial Architecture.MBMV34-432004Conference and Workshop Papersunavailableconf/mbmv/RettbergDLZ04https://dblp.org/rec/conf/mbmv/RettbergDLZ04URL#6071654Michael SchlegelGöran HerrmannDietmar Müller 0001Erweiterte Kostenmodellierung mit VHDL/VHDL-AMS.MBMV147-1552004Conference and Workshop Papersunavailableconf/mbmv/SchlegelHM04https://dblp.org/rec/conf/mbmv/SchlegelHM04URL#6071655Stephen SchmittWolfgang RosenstielRapid Prototyping of a Microcontroller IP Core under Resource Limitations.MBMV214-2232004Conference and Workshop Papersunavailableconf/mbmv/SchmittR04https://dblp.org/rec/conf/mbmv/SchmittR04URL#6071656Christoph Scholl 0001Matthias BücheFilter Based Diagnosis for Multiple Design Errors.MBMV270-2792004Conference and Workshop Papersunavailableconf/mbmv/SchollB04https://dblp.org/rec/conf/mbmv/SchollB04URL#6071657Tobias SchüleKlaus Schneider 0001Global vs. Local Model Checking of Infinite State Systems.MBMV54-642004Conference and Workshop Papersunavailableconf/mbmv/SchuleS04https://dblp.org/rec/conf/mbmv/SchuleS04URL#6071658Alexander ThomasJürgen Becker 0001Ulrich HeinkelKlaus WinkelmannJörg BormannFormale Verifikation eines Sonet/SDH Framers.MBMV280-2882004Conference and Workshop Papersunavailableconf/mbmv/ThomasBHWB04https://dblp.org/rec/conf/mbmv/ThomasBHWB04URL#6071659Alain VachouxDo we really need SystemC-AMS?MBMV126-1262004Conference and Workshop Papersunavailableconf/mbmv/Vachoux04https://dblp.org/rec/conf/mbmv/Vachoux04URL#6071660Markus VisariusWolfram HardtThe IPQ Format -- An Approach to Support IP based Design.MBMV106-1152004Conference and Workshop Papersunavailableconf/mbmv/VisariusH04https://dblp.org/rec/conf/mbmv/VisariusH04URL#6071661Martin ZambaldiWolfgang EckerEin orthogonales Schema für die Klassifikation der Modellierungsabstraktion von digitalen Systemen.MBMV96-1052004Conference and Workshop Papersunavailableconf/mbmv/ZambaldiE04https://dblp.org/rec/conf/mbmv/ZambaldiE04URL#6071662Peter ZipfHeiko HinkelmannAdeel AshrafThomas HollsteinManfred GlesnerAn Asynchronous Switch Implmentation for Systems-on-a-Chip.MBMV224-2312004Conference and Workshop Papersunavailableconf/mbmv/ZipfHAHG04https://dblp.org/rec/conf/mbmv/ZipfHAHG04URL#6071663Dominik StoffelWolfgang KunzMethoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Kaiserslautern, Germany, February 24-25, 2004MBMVShaker2004Editorshipunavailableconf/mbmv/2004https://dblp.org/rec/conf/mbmv/2004URL#6095621Marco BeyerHans-Ulrich PostVHDL-Hardware/Software-Board-Level-Simulation innerhalb eines FPGA/DSP-Entwicklungssystems.MBMV154-1632003Conference and Workshop Papersunavailableconf/mbmv/BeyerP03https://dblp.org/rec/conf/mbmv/BeyerP03URL#6193463Hans-Jürgen BrandVerifikation von Prozessorplattformen -- Probleme und Trends aus Sicht der Chipentwicklung.MBMV61-612003Conference and Workshop Papersunavailableconf/mbmv/Brand03https://dblp.org/rec/conf/mbmv/Brand03URL#6193464Marco FischerStefan FörsterAndré WindischBurkhard BalserDieter MonjauA New Process-Algebraic Specification Methodology for Integrated Modular Avionic Systems.MBMV21-292003Conference and Workshop Papersunavailableconf/mbmv/FischerFWBM03https://dblp.org/rec/conf/mbmv/FischerFWBM03URL#6193465Eva FordranMatthias FruthUlrich HenselHu ShaoyuMadabhushi SrinivasanModel Checking in an Industrial Environment.MBMV239-2482003Conference and Workshop Papersunavailableconf/mbmv/FordranFHSS03https://dblp.org/rec/conf/mbmv/FordranFHSS03URL#6193466Fanny GarnierWolfgang EckerIncremental Design: A VHDL based Case Study.MBMV81-922003Conference and Workshop Papersunavailableconf/mbmv/GarnierE03https://dblp.org/rec/conf/mbmv/GarnierE03URL#6193467Carsten GremzowE. HansenNico MoserHans-Ulrich PostDatapath constrained High-Level Synthesis of Central Memory Architectures.MBMV144-1532003Conference and Workshop Papersunavailableconf/mbmv/GremzowHMP03https://dblp.org/rec/conf/mbmv/GremzowHMP03URL#6193468Daniel GroßeRolf DrechslerFormale Verifikation von LTL-Formeln für SystemC-Beschreibungen.MBMV229-2382003Conference and Workshop Papersunavailableconf/mbmv/GrosseD03https://dblp.org/rec/conf/mbmv/GrosseD03URL#6193469Joachim HaaseRegeln für die Erstellung von VHDL-AMS-Modellen.MBMV30-402003Conference and Workshop Papersunavailableconf/mbmv/Haase03https://dblp.org/rec/conf/mbmv/Haase03URL#6193470Marc HerbstrittBernd Becker 0001Conflict-based Selection of Branching Rules in SAT-Algorithms.MBMV189-1982003Conference and Workshop Papersunavailableconf/mbmv/HerbstrittB03https://dblp.org/rec/conf/mbmv/HerbstrittB03URL#6193471Stefan IhmorMarkus VisariusWolfram HardtModeling of Configurable HW/SW-Interfaces.MBMV51-602003Conference and Workshop Papersunavailableconf/mbmv/IhmorVH03https://dblp.org/rec/conf/mbmv/IhmorVH03URL#6193472Christoph JaeschkeBodo HoppeWolfram SauerA Universal Disassembler using Table Based Formal Architectural Specification.MBMV93-1012003Conference and Workshop Papersunavailableconf/mbmv/JaeschkeHS03https://dblp.org/rec/conf/mbmv/JaeschkeHS03URL#6193473Marek JersakKai Richter 0001Rolf ErnstJörn-Christian BraamZheng-Yu JiangFabian WolfCertifiable Software-Integration for Engine Electronics.MBMV102-1112003Conference and Workshop Papersunavailableconf/mbmv/JersakREBJW03https://dblp.org/rec/conf/mbmv/JersakREBJW03URL#6193474Kai KappViktor K. SabelfeldDead Code Elimination in Formal Synthesis.MBMV121-1302003Conference and Workshop Papersunavailableconf/mbmv/KappS03https://dblp.org/rec/conf/mbmv/KappS03URL#6193475Michael KerstenRamon BiniaschWolfgang NebelFrank OppenheimerErweiterung der UML um Zeitannotationen zur Analyse des Zeitverhaltens reaktiver Systeme.MBMV11-202003Conference and Workshop Papersunavailableconf/mbmv/KerstenBNO03https://dblp.org/rec/conf/mbmv/KerstenBNO03URL#6193476Alexander KruppWolfgang Müller 0003Formale Verfeinerung und Modelchecking von zeitbehafteten endlichen Automaten.MBMV219-2282003Conference and Workshop Papersunavailableconf/mbmv/Krupp003https://dblp.org/rec/conf/mbmv/Krupp003URL#6193477Christian MeiseChristoph Grimm 0001Konzept einer Klassensammlung zur Verhaltensmodellierung hybrider Systeme am Beispiel der Leistungselektronik.MBMV41-502003Conference and Workshop Papersunavailableconf/mbmv/MeiseG03https://dblp.org/rec/conf/mbmv/MeiseG03URL#6193478Matthias MengeCarsten GremzowIrenäus SchoppalaLa -- An Object Oriented Language for Schematic and Printed Circuit Board Specification.MBMV72-802003Conference and Workshop Papersunavailableconf/mbmv/MengeGS03https://dblp.org/rec/conf/mbmv/MengeGS03URL#6193479Michael PayerA Platform for Construction and Integration of Digital IP Blocks.MBMV131-1312003Conference and Workshop Papersunavailableconf/mbmv/Payer03https://dblp.org/rec/conf/mbmv/Payer03URL#6193480Jan Peleska 0001Automated Test Suites for Modern Aircraft Controllers.MBMV1-102003Conference and Workshop Papersunavailableconf/mbmv/Peleska03https://dblp.org/rec/conf/mbmv/Peleska03URL#6193481Ilia PolianWolfgang Günther 0001Bernd Becker 0001The Case for 2-POF.MBMV164-1732003Conference and Workshop Papersunavailableconf/mbmv/PolianGB03https://dblp.org/rec/conf/mbmv/PolianGB03URL#6193482Jürgen RufPrakash Mohan PeranandamBounded Property Checking with Symbolic Simulation.MBMV209-2182003Conference and Workshop Papersunavailableconf/mbmv/RufP03https://dblp.org/rec/conf/mbmv/RufP03URL#6193483Viktor K. SabelfeldKai KappArithmetic in Formal Synthesis.MBMV112-1202003Conference and Workshop Papersunavailableconf/mbmv/SabelfeldK03https://dblp.org/rec/conf/mbmv/SabelfeldK03URL#6193484Mathias SporerDieter MonjauDatenbanken zur konsistenten Speicherung von Entwurfsdaten für eingebettete Systeme.MBMV62-712003Conference and Workshop Papersunavailableconf/mbmv/SporerM03https://dblp.org/rec/conf/mbmv/SporerM03URL#6193485Markus WedlerDominik StoffelWolfgang KunzTowards the impact of state encoding on induction-based property checking.MBMV199-2082003Conference and Workshop Papersunavailableconf/mbmv/WedlerSK03https://dblp.org/rec/conf/mbmv/WedlerSK03URL#6193486Klaus WinkelmannHans-Joachim TrylusDominik StoffelGörschwin FeyCost-efficient Formal Block Verification for ASIC Design.MBMV184-1882003Conference and Workshop Papersunavailableconf/mbmv/WinkelmannTSF03https://dblp.org/rec/conf/mbmv/WinkelmannTSF03URL#6193487Martin ZambaldiMatthias Bauer 0003Wolfgang EckerRenate HenftlingAndreas ZinnAn Enhanced Environment for Multi-Level Simulation.MBMV174-1832003Conference and Workshop Papersunavailableconf/mbmv/ZambaldiBEHZ03https://dblp.org/rec/conf/mbmv/ZambaldiBEHZ03URL#6193488Roberto ZillerKlaus Schneider 0001A μ-Calculus Approach to Supervisor Synthesis.MBMV132-1432003Conference and Workshop Papersunavailableconf/mbmv/ZillerS03https://dblp.org/rec/conf/mbmv/ZillerS03URL#6193489Rolf DrechslerMethoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Bremen, Germany, February 24-25, 2003MBMVShaker2003Editorshipunavailableconf/mbmv/2003https://dblp.org/rec/conf/mbmv/2003URL#6212896Jens BastianJoachim HaaseSven ReitzVerhaltensbeschreibung von Systemen mit verteilten Parametern durch Ordnungsreduktion.MBMV144-1532002Conference and Workshop Papersunavailableconf/mbmv/BastianHR02https://dblp.org/rec/conf/mbmv/BastianHR02URL#6295235Rolf DrechslerJochen RömmlerImplementation and Visualization of a BDD Package in JAVA.MBMV219-2282002Conference and Workshop Papersunavailableconf/mbmv/DrechslerR02https://dblp.org/rec/conf/mbmv/DrechslerR02URL#6295236Klaus-Jürgen EnglertBernd Becker 0001Rolf DrechslerSymbolic Simulation of Algorithms Specified in HDL.MBMV113-1222002Conference and Workshop Papersunavailableconf/mbmv/EnglertBD02https://dblp.org/rec/conf/mbmv/EnglertBD02URL#6295237Olga FenglerThorsten HummelWolfgang Fengler 0001Modellierung kooperierender Prozesse mit gefärbten Sequenzdiagrammen.MBMV199-2082002Conference and Workshop Papersunavailableconf/mbmv/FenglerHF02https://dblp.org/rec/conf/mbmv/FenglerHF02URL#6295238Jürgen FrößlSynthese großer Schaltungen.MBMV56-562002Conference and Workshop Papersunavailableconf/mbmv/Frossl02https://dblp.org/rec/conf/mbmv/Frossl02URL#6295239Carsten GremzowE. HansenNico MoserHans-Ulrich PostIntegration einer Datenpfad-orientierten Ablaufplanung und Bindung in die High-Level-Synthese.MBMV57-662002Conference and Workshop Papersunavailableconf/mbmv/GremzowHMP02https://dblp.org/rec/conf/mbmv/GremzowHMP02URL#6295240Christoph Grimm 0001Christian MeiseWilhelm HeupkeKlaus WaldschmidtEntwurf analog/digitaler Systeme mit SystemC.MBMV46-552002Conference and Workshop Papersunavailableconf/mbmv/GrimmMHW02https://dblp.org/rec/conf/mbmv/GrimmMHW02URL#6295241Werner Haas 0003Stefan GossensUlrich HeinkelBehavioural Specification for Advanced Design and Verification of ASICs (ADeVA).MBMV96-1052002Conference and Workshop Papersunavailableconf/mbmv/HaasGH02https://dblp.org/rec/conf/mbmv/HaasGH02URL#6295242Cordula HansenWolfgang RosenstielHigh Level Testbench Transformation for Pipelined Components.MBMV124-1332002Conference and Workshop Papersunavailableconf/mbmv/HansenR02https://dblp.org/rec/conf/mbmv/HansenR02URL#6295243Christian HaubeltJürgen TeichKai Richter 0001Rolf ErnstModellierung rekonfigurierbarer Systemarchitekturen.MBMV163-1712002Conference and Workshop Papersunavailableconf/mbmv/HaubeltTRE02https://dblp.org/rec/conf/mbmv/HaubeltTRE02URL#6295244Oliver KrausMartin PadeffkeEntwurfsumgebung für asynchrone Burst-Mode Automaten.MBMV86-952002Conference and Workshop Papersunavailableconf/mbmv/KrausP02https://dblp.org/rec/conf/mbmv/KrausP02URL#6295245Thomas KumpfCarsten Müller-SchwannekeBjörn JelonnekArmin SplettAlbrecht RothermelSchnelle Simulation analoger Sigma-Delta-Modulatoren durch Abstraktion von Transistorschaltungen.MBMV106-1122002Conference and Workshop Papersunavailableconf/mbmv/KumpfMJSR02https://dblp.org/rec/conf/mbmv/KumpfMJSR02URL#6295246Thomas Lehmann 0001Mauro Cesar ZanellaModeling and Software Synthesis of Interrupt Systems.MBMV9-172002Conference and Workshop Papersunavailableconf/mbmv/LehmannZ02https://dblp.org/rec/conf/mbmv/LehmannZ02URL#6295247Matthias MengeIrenäus SchoppaHardwaresynthese von Programmiermodellen.MBMV76-852002Conference and Workshop Papersunavailableconf/mbmv/MengeS02https://dblp.org/rec/conf/mbmv/MengeS02URL#6295248Dieter MonjauMathias SporerAnalyse dynamischer Eigenschaften eingebetteter Systeme mit GPSS.MBMV172-1822002Conference and Workshop Papersunavailableconf/mbmv/MonjauS02https://dblp.org/rec/conf/mbmv/MonjauS02URL#6295249Kai Richter 0001Rolf ErnstWayne H. WolfLocal Constraint Derivation for Platform-Based Design.MBMV26-352002Conference and Workshop Papersunavailableconf/mbmv/RichterEW02https://dblp.org/rec/conf/mbmv/RichterEW02URL#6295250Wolfgang RosenstielStruktur und Aufgaben des edacentrums.MBMV183-1982002Conference and Workshop Papersunavailableconf/mbmv/Rosenstiel02https://dblp.org/rec/conf/mbmv/Rosenstiel02URL#6295251Jürgen RufThomas KropfCombination of Simulation and Formal Verification.MBMV134-1432002Conference and Workshop Papersunavailableconf/mbmv/RufK02https://dblp.org/rec/conf/mbmv/RufK02URL#6295252Michael SchlegelGöran HerrmannDietmar Müller 0001"Multi-Architecture-Modeling" Entwurfsmethode für Mixed-Signal- und Multi-Domain-Systemsimulation.MBMV18-252002Conference and Workshop Papersunavailableconf/mbmv/SchlegelHM02https://dblp.org/rec/conf/mbmv/SchlegelHM02URL#6295253Mathias SchmalischHagen PloogDirk TimmermannLaufzeitoptimierte VHDL Bibliothek zur Verifikation und Simulation Kryptographischer Prozessoren.MBMV154-1622002Conference and Workshop Papersunavailableconf/mbmv/SchmalischPT02https://dblp.org/rec/conf/mbmv/SchmalischPT02URL#6295254Jörg SchneiderMaik BodenSteffen RülkeEine wiederverwendungsgerechte Entwurfsmethodik für rekonfigurierbare SoC-Architekturen.MBMV36-452002Conference and Workshop Papersunavailableconf/mbmv/SchneiderBR02https://dblp.org/rec/conf/mbmv/SchneiderBR02URL#6295255Christoph Scholl 0001Bernd Becker 0001Equivalence Checking in the Presence of Incompletely Specified Boxes.MBMV239-2482002Conference and Workshop Papersunavailableconf/mbmv/SchollB02https://dblp.org/rec/conf/mbmv/SchollB02URL#6295256Klaus-Dieter SchubertFormal Verification versus Simulation in Functional Verification -- An Industry Perspective.MBMV123-1232002Conference and Workshop Papersunavailableconf/mbmv/Schubert02https://dblp.org/rec/conf/mbmv/Schubert02URL#6295257Tobias SchueleKlaus Schneider 0001Symbolic Model Checking by Automata Based Set Representation.MBMV229-2382002Conference and Workshop Papersunavailableconf/mbmv/SchueleS02https://dblp.org/rec/conf/mbmv/SchueleS02URL#6295258Kolja SulimmaIngmar NeumannLukas P. P. P. van GinnekenWolfgang KunzImproving Placement under the Constant Delay Model.MBMV67-752002Conference and Workshop Papersunavailableconf/mbmv/SulimmaNGK02https://dblp.org/rec/conf/mbmv/SulimmaNGK02URL#6295259Sven VerdenhalvenHolger KühlInterfacing Concept for Different Levels of Abstraction in IP-based SoC Design.MBMV1-82002Conference and Workshop Papersunavailableconf/mbmv/VerdenhalvenK02https://dblp.org/rec/conf/mbmv/VerdenhalvenK02URL#6295260Roberto ZillerFinding Bad States during Symbolic Supervisor Synthesis.MBMV209-2182002Conference and Workshop Papersunavailableconf/mbmv/Ziller02https://dblp.org/rec/conf/mbmv/Ziller02URL#6295261Jürgen RufMethoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Tübingen, Germany, February 25-27, 2002MBMVShaker2002Editorshipunavailableconf/mbmv/2002https://dblp.org/rec/conf/mbmv/2002URL#6311210Jörg BormannFormale Verifikation wird zum Handwerk.MBMV9-102001Conference and Workshop Papersunavailableconf/mbmv/Bormann01https://dblp.org/rec/conf/mbmv/Bormann01URL#6383396Rolf DrechslerGateComp: Equivalence Checking in CVE.MBMV109-1102001Conference and Workshop Papersunavailableconf/mbmv/Drechsler01https://dblp.org/rec/conf/mbmv/Drechsler01URL#6383397Wolfgang EckerHardware-basierter Hardware-Entwurf.MBMV59-612001Conference and Workshop Papersunavailableconf/mbmv/Ecker01https://dblp.org/rec/conf/mbmv/Ecker01URL#6383398Marco GötzeWolfram KattanekErfahrungen mit der UML beim Entwurf von Kfz-Steuerungen.MBMV87-982001Conference and Workshop Papersunavailableconf/mbmv/GotzeK01https://dblp.org/rec/conf/mbmv/GotzeK01URL#6383399Christoph Grimm 0001Peter OehlerChristian MeiseKlaus WaldschmidtWolfgang FeyErstellung von C++-Modellen analoger Leistungselektronik zur schnellen Systemsimulation.MBMV107-1172001Conference and Workshop Papersunavailableconf/mbmv/GrimmOMWF01https://dblp.org/rec/conf/mbmv/GrimmOMWF01URL#6383400Eike GrimpeFrank OppenheimerObjektorientierte Hardwarebeschreibung und -synthese aufbauend auf SystemC.MBMV99-1082001Conference and Workshop Papersunavailableconf/mbmv/GrimpeO01https://dblp.org/rec/conf/mbmv/GrimpeO01URL#6383401Wolfram HardtThomas Lehmann 0001Markus VisariusTowards a Design Methodology Capturing Interface Synthesis.MBMV93-972001Conference and Workshop Papersunavailableconf/mbmv/HardtLV01https://dblp.org/rec/conf/mbmv/HardtLV01URL#6383402Uwe HatnikJürgen HaufePeter SchwarzObjektorientierte Simulation von heterogenen Kommunikations-Systemen.MBMV83-912001Conference and Workshop Papersunavailableconf/mbmv/HatnikHS01https://dblp.org/rec/conf/mbmv/HatnikHS01URL#6383403Andreas HettBernd Becker 0001Supervised Dynamic Recording in Model Checking.MBMV21-302001Conference and Workshop Papersunavailableconf/mbmv/HettB01https://dblp.org/rec/conf/mbmv/HettB01URL#6383404Thorsten HummelDer Einsatz von hybriden Petri-Netzen für den Entwurf gemischt analog-digitaler eingebetteter Systeme.MBMV49-582001Conference and Workshop Papersunavailableconf/mbmv/Hummel01https://dblp.org/rec/conf/mbmv/Hummel01URL#6383405Holger KrispChristian Müller-SchloerVirtual Prototyping of Embedded Systems by High-Level Modeling and Simulation.MBMV99-1062001Conference and Workshop Papersunavailableconf/mbmv/KrispM01https://dblp.org/rec/conf/mbmv/KrispM01URL#6383406Gunter LantzschAndré SchneiderInternet-basierte Simulation unter Nutzung des HLA-Ansatzes.MBMV119-1282001Conference and Workshop Papersunavailableconf/mbmv/LantzschS01https://dblp.org/rec/conf/mbmv/LantzschS01URL#6383407Dieter MonjauMathias SporerTobias WeberAnwendung von UML zur Beschreibung von eingebetteten Systemen.MBMV75-862001Conference and Workshop Papersunavailableconf/mbmv/MonjauSW01https://dblp.org/rec/conf/mbmv/MonjauSW01URL#6383408Ingmar NeumannWolfgang KunzPerformance Optimization during Placement by Retiming.MBMV19-282001Conference and Workshop Papersunavailableconf/mbmv/NeumannK01https://dblp.org/rec/conf/mbmv/NeumannK01URL#6383409Thomas OberthürMichael BolleHiperSonicTM: A programmable solution for 5 GHz wireless networks.MBMV131-1362001Conference and Workshop Papersunavailableconf/mbmv/OberthurB01https://dblp.org/rec/conf/mbmv/OberthurB01URL#6383410R. PeukertKarsten HenkeHeinz-Dietrich WuttkeVerifikation im Experimentalsystem GIFT.MBMV63-722001Conference and Workshop Papersunavailableconf/mbmv/PeukertHW01https://dblp.org/rec/conf/mbmv/PeukertHW01URL#6383411Ilia PolianWolfgang Günther 0001Bernd Becker 0001Efficient Pattern-Based Verification of Connections to Intellectual Property Cores.MBMV111-1202001Conference and Workshop Papersunavailableconf/mbmv/PolianGB01https://dblp.org/rec/conf/mbmv/PolianGB01URL#6383412Wolfram Putzke-RömingDurchgängiges Kommunikationsdesign für den strukturalen, objektorientierten Hardwareentwurf.MBMV39-482001Conference and Workshop Papersunavailableconf/mbmv/Putzke-Roming01https://dblp.org/rec/conf/mbmv/Putzke-Roming01URL#6383413Jürgen RufData Analysis of Timed Finite State Systems.MBMV11-202001Conference and Workshop Papersunavailableconf/mbmv/Ruf01https://dblp.org/rec/conf/mbmv/Ruf01URL#6383414Holger SchmittHigh-Level Bewertung sequentieller Schaltungen.MBMV7-172001Conference and Workshop Papersunavailableconf/mbmv/Schmitt01https://dblp.org/rec/conf/mbmv/Schmitt01URL#6383415Christoph Scholl 0001Bernd Becker 0001Checking Equivalence for Partial Implementations.MBMV31-432001Conference and Workshop Papersunavailableconf/mbmv/SchollB01https://dblp.org/rec/conf/mbmv/SchollB01URL#6383416Christoph Scholl 0001Marc HerbstrittBernd Becker 0001Don't Care Minimization of BMDs: Complexity and Algorithms.MBMV45-572001Conference and Workshop Papersunavailableconf/mbmv/SchollHB01https://dblp.org/rec/conf/mbmv/SchollHB01URL#6383417Peter SchwarzObjektorientierte Modellbildung in Elektronik und Mikrosystemtechnik.MBMV29-382001Conference and Workshop Papersunavailableconf/mbmv/Schwarz01https://dblp.org/rec/conf/mbmv/Schwarz01URL#6383418Ralf SeepoldStandardization of System-Level IP.MBMV67-742001Conference and Workshop Papersunavailableconf/mbmv/Seepold01https://dblp.org/rec/conf/mbmv/Seepold01URL#6383419Marc TheisenBurkart VossManfred GlesnerTransformierende Synthese zur Verlustleistungsreduktion mittels Partitionierung.MBMV73-812001Conference and Workshop Papersunavailableconf/mbmv/TheisenVG01https://dblp.org/rec/conf/mbmv/TheisenVG01URL#6383420Reimund WittmannThomas RühleSimone SchneidersIngo KönenkampEffizientes Auswahlverfahren zum Auffinden parametrisierbarer Analogschaltungen in Repository-Werkzeugen.MBMV59-662001Conference and Workshop Papersunavailableconf/mbmv/WittmannRSK01https://dblp.org/rec/conf/mbmv/WittmannRSK01URL#6383421Roberto ZillerSystem Modeling Using Marker States in the RW-Framework.MBMV121-1302001Conference and Workshop Papersunavailableconf/mbmv/Ziller01https://dblp.org/rec/conf/mbmv/Ziller01URL#6383422Dieter MonjauMethoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Meißen, Germany, February 19-21, 2001MBMVMoPress2001Editorshipunavailableconf/mbmv/2001https://dblp.org/rec/conf/mbmv/2001URL#6398252Matthias Bauer 0003Wolfgang EckerAndreas ZinnGraphische Spezifikation und Analyse funktionaler Testabläufe mit MSCs der UML.MBMV113-1202000Conference and Workshop Papersunavailableconf/mbmv/BauerEZ00https://dblp.org/rec/conf/mbmv/BauerEZ00URL#6466939Andreas BauerWolfgang SchwarzVolterra Kernel for Automatic Analysis and Optimization of Nonlinear Analogue Circuits.MBMV288-2972000Conference and Workshop Papersunavailableconf/mbmv/BauerS00https://dblp.org/rec/conf/mbmv/BauerS00URL#6466940Christine Bauer 0002Peter ZipfHans WojtkowiakIntegration und Fehlertoleranz im Codesign.MBMV250-2582000Conference and Workshop Papersunavailableconf/mbmv/BauerZW00https://dblp.org/rec/conf/mbmv/BauerZW00URL#6466941Dirk BierbaumReimund WittmannMichael BuchmannMohsen DarianianA 2k High Speed CMOS Embedded Dual Port SRAM Using an Advanced Generator Concept.MBMV221-2262000Conference and Workshop Papersunavailableconf/mbmv/BierbaumWBD00https://dblp.org/rec/conf/mbmv/BierbaumWBD00URL#6466942Claudia BlankGerd RitterHolger HinrichsenHans EvekingFormale Verifikation der Register-Allokation.MBMV27-352000Conference and Workshop Papersunavailableconf/mbmv/BlankRHE00https://dblp.org/rec/conf/mbmv/BlankRHE00URL#6466943Wolfgang BoßungSorin A. HussMichael StinixCDM -- Ein interaktives Werkzeug zur graphenbasierten Systemmodellierung.MBMV153-1612000Conference and Workshop Papersunavailableconf/mbmv/BossungHS00https://dblp.org/rec/conf/mbmv/BossungHS00URL#6466944C. BuchholzWolfgang RosenstielA Constraint-Based Design Methodology for Automated Composition with IPs.MBMV211-2192000Conference and Workshop Papersunavailableconf/mbmv/BuchholzR00https://dblp.org/rec/conf/mbmv/BuchholzR00URL#6466945Wolfgang EckerMike HeuchlingJochen MadesThomas Schneider 0006André WindischKe YangVXML: VHDL Hardware Design Representation in XML.MBMV129-1402000Conference and Workshop Papersunavailableconf/mbmv/EckerHMSWY00https://dblp.org/rec/conf/mbmv/EckerHMSWY00URL#6466946Wolfgang FeySystem Simulation: A Basic Tool for Modern System Development.MBMV246-2462000Conference and Workshop Papersunavailableconf/mbmv/Fey00https://dblp.org/rec/conf/mbmv/Fey00URL#6466947Stephan FlakeWolfgang Müller 0003Jürgen RufStructured English for Model Checking Specification.MBMV99-1082000Conference and Workshop Papersunavailableconf/mbmv/Flake0R00https://dblp.org/rec/conf/mbmv/Flake0R00URL#6466948Riccardo ForthPaul MolitorPermutation Independent Comparison of Pseudo Boolean Functions.MBMV79-882000Conference and Workshop Papersunavailableconf/mbmv/ForthM00https://dblp.org/rec/conf/mbmv/ForthM00URL#6466949Christoph Grimm 0001Thomas StaunerÜbersetzung von HyCharts in HDFG.MBMV141-1512000Conference and Workshop Papersunavailableconf/mbmv/GrimmS00https://dblp.org/rec/conf/mbmv/GrimmS00URL#6466950Wolfgang Günther 0001Nicole DrechslerRolf DrechslerBernd Becker 0001Verification of Designs Containing Black Boxes.MBMV19-262000Conference and Workshop Papersunavailableconf/mbmv/GuntherDDB00https://dblp.org/rec/conf/mbmv/GuntherDDB00URL#6466951Jürgen HaasePeter SchwarzPeter TrappeWolfgang VermeirenErfahrungen mit VHDL-AMS bei der Simulation heterogener Systeme.MBMV167-1752000Conference and Workshop Papersunavailableconf/mbmv/HaaseSTV00https://dblp.org/rec/conf/mbmv/HaaseSTV00URL#6466952Gunter HaugUdo KebschullWolfgang RosenstielEmulation synthetisierter Verhaltensbeschreibungen mit VLIW-Prozessoren.MBMV177-1852000Conference and Workshop Papersunavailableconf/mbmv/HaugKR00https://dblp.org/rec/conf/mbmv/HaugKR00URL#6466953Andreas HettChristoph Scholl 0001Bernd Becker 0001State Traversal guided by Hamming Distance Profiles.MBMV57-662000Conference and Workshop Papersunavailableconf/mbmv/HettSB00https://dblp.org/rec/conf/mbmv/HettSB00URL#6466954Frank HeuschenChristoph Grimm 0001Klaus WaldschmidtModellierung des Implementierungsraumes im Analog/Digital Co-Design.MBMV187-1972000Conference and Workshop Papersunavailableconf/mbmv/HeuschenGW00https://dblp.org/rec/conf/mbmv/HeuschenGW00URL#6466955Jürgen KampeDie formale Beschreibung des Strukturentwurfs analoger Systemkomponenten.MBMV199-2082000Conference and Workshop Papersunavailableconf/mbmv/Kampe00https://dblp.org/rec/conf/mbmv/Kampe00URL#6466956Jürgen KoehlJürgen SchietkePlatzierungsbasierte Logikoptimierung komplexer VLSI Chips.MBMV270-2772000Conference and Workshop Papersunavailableconf/mbmv/KoehlS00https://dblp.org/rec/conf/mbmv/KoehlS00URL#6466957Daniel KröningWolfgang J. PaulSilvia M. MüllerProving the Correctness of Pipelined Micro-Architectures.MBMV89-982000Conference and Workshop Papersunavailableconf/mbmv/KroningPM00https://dblp.org/rec/conf/mbmv/KroningPM00URL#6466958Michael KropfAutomotive Electronics: European Challenges in Circuit and System Design.MBMV109-1092000Conference and Workshop Papersunavailableconf/mbmv/Kropf00https://dblp.org/rec/conf/mbmv/Kropf00URL#6466959Michael MrvaRainer Kress 0002Role-Centered Conceptual Modeling in System Design.MBMV121-1282000Conference and Workshop Papersunavailableconf/mbmv/MrvaK00https://dblp.org/rec/conf/mbmv/MrvaK00URL#6466960Michael PayerIndustrial Experience with Formal Verification.MBMV9-162000Conference and Workshop Papersunavailableconf/mbmv/Payer00https://dblp.org/rec/conf/mbmv/Payer00URL#6466961Frank-Michael RennerJürgen Becker 0001Manfred GlesnerCommunication Performance Estimation and Communication Synthesis for Architecture-precise Prototyping of Real-time Embedded Systems.MBMV227-2352000Conference and Workshop Papersunavailableconf/mbmv/RennerBG00https://dblp.org/rec/conf/mbmv/RennerBG00URL#6466962Thomas RinglerEntwicklung und Analyse von verteilten zeitgesteuerten Systemen.MBMV260-2692000Conference and Workshop Papersunavailableconf/mbmv/Ringler00https://dblp.org/rec/conf/mbmv/Ringler00URL#6466963Jürgen RufA Toolset for the Symbolic Examination of Finite State Transition Systems.MBMV69-782000Conference and Workshop Papersunavailableconf/mbmv/Ruf00https://dblp.org/rec/conf/mbmv/Ruf00URL#6466964Sergej SawitzkiSteffen KöhlerRainer G. SpallekJörg SchneiderS. RülkeExperimenteller Vergleich verschiedener Entwurfsmethoden für FPGA-basierte Entwurfsabläufe.MBMV236-2442000Conference and Workshop Papersunavailableconf/mbmv/SawitzkiKSSR00https://dblp.org/rec/conf/mbmv/SawitzkiKSSR00URL#6466965Heinz-Josef SchlebuschC-based Design of Systems-on-Chip: An EDA Perspective.MBMV163-1632000Conference and Workshop Papersunavailableconf/mbmv/Schlebusch00https://dblp.org/rec/conf/mbmv/Schlebusch00URL#6466966Jens SchönherrBernd StraubeInduction based Equivalence Check at Register Transfer Level.MBMV37-442000Conference and Workshop Papersunavailableconf/mbmv/SchonherrS00https://dblp.org/rec/conf/mbmv/SchonherrS00URL#6466967Jens SchönherrBernd StraubeFormale Verifikation auf höheren Entwurfsebenen mittels symbolischer Traversierung unendlicher Automaten.MBMV47-562000Conference and Workshop Papersunavailableconf/mbmv/SchonherrS00ahttps://dblp.org/rec/conf/mbmv/SchonherrS00aURL#6466968Andreas WassatschDirk TimmermannUntersuchung zum Einfluß der speziellen Anforderungen dynamischer Schaltungstechnik auf den Systementwurf.MBMV278-2872000Conference and Workshop Papersunavailableconf/mbmv/WassatschT00https://dblp.org/rec/conf/mbmv/WassatschT00URL#6466969Klaus WaldschmidtChristoph Grimm 0001Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Frankfurt, Germany, February 28 - March 1, 2000MBMVVDE2000Editorshipunavailableconf/mbmv/2000https://dblp.org/rec/conf/mbmv/2000URL#6479435Karlheinz AgsteinerDieter MonjauBernt NaumannMathias SporerEin kompositioneller Ansatz zur Synthese von Datenpfaden.MBMV131-1401999Conference and Workshop Papersunavailableconf/mbmv/AgsteinerMNS99https://dblp.org/rec/conf/mbmv/AgsteinerMNS99URL#6539589Cristina BarnaWolfgang RosenstielDescription and Classification of VHDL Objects in the Reuse Management System.MBMV150-1591999Conference and Workshop Papersunavailableconf/mbmv/BarnaR99https://dblp.org/rec/conf/mbmv/BarnaR99URL#6539590Tom BarthelDietmar Müller 0001Jan PauliukBeschreibungsmittel und Werkzeuge für Spezifikationen heterogener Systeme.MBMV81-901999Conference and Workshop Papersunavailableconf/mbmv/BarthelMP99https://dblp.org/rec/conf/mbmv/BarthelMP99URL#6539591Christian BlumenröhrA Formal Approach to Specify and Synthesize at the System Level.MBMV11-201999Conference and Workshop Papersunavailableconf/mbmv/Blumenrohr99https://dblp.org/rec/conf/mbmv/Blumenrohr99URL#6539592Christoph ClaußAndré SchneiderPeter SchwarzObjektorientierte Beschreibung elektrischer Schaltelemente mit Modelica.MBMV101-1101999Conference and Workshop Papersunavailableconf/mbmv/ClaussSS99https://dblp.org/rec/conf/mbmv/ClaussSS99URL#6539593Rolf DrechslerMarc HerbstrittBernd Becker 0001Grouping Heuristics for Word-Level Decision Diagrams.MBMV41-501999Conference and Workshop Papersunavailableconf/mbmv/DrechslerHB99https://dblp.org/rec/conf/mbmv/DrechslerHB99URL#6539594Joachim GerlachThilo KlöpferWolfgang RosenstielAlgorithmischer Ansatz zur automatisierten Entwurfsraum-Exploration auf hoher Abstraktionsebene.MBMV111-1201999Conference and Workshop Papersunavailableconf/mbmv/GerlachKR99https://dblp.org/rec/conf/mbmv/GerlachKR99URL#6539595Cordula HansenMatthias UhlmannWolfgang RosenstielAn Interface Description Model for Reuse of Algorithmic Hardware Specifications.MBMV141-1491999Conference and Workshop Papersunavailableconf/mbmv/HansenUR99https://dblp.org/rec/conf/mbmv/HansenUR99URL#6539596Heiko HenkelmannC. BruennleinWalter AnheierEffiziente Methoden zum Zahlenvergleich und zur Vorzeichenerkennung in Restklassensystemen.MBMV121-1301999Conference and Workshop Papersunavailableconf/mbmv/HenkelmannBA99https://dblp.org/rec/conf/mbmv/HenkelmannBA99URL#6539597Frank HeuschenHolger SchmittKlaus WaldschmidtFormale Modellierung der Partitionierung eines gemischt analog/digitalen Systems.MBMV71-801999Conference and Workshop Papersunavailableconf/mbmv/HeuschenSW99https://dblp.org/rec/conf/mbmv/HeuschenSW99URL#6539598Holger HinrichsenGerd RitterHans EvekingAutomatische Synthese und Verifikation von RISC-Prozessoren.MBMV1-101999Conference and Workshop Papersunavailableconf/mbmv/HinrichsenRE99https://dblp.org/rec/conf/mbmv/HinrichsenRE99URL#6539599Tommy KuhnWolfgang RosenstielUdo KebschullBeschreibung und Simulation von Hardware/Software-Systemen mit Java.MBMV170-1811999Conference and Workshop Papersunavailableconf/mbmv/KuhnRK99https://dblp.org/rec/conf/mbmv/KuhnRK99URL#6539600Thomas LockMichael MendlerÄquivalenz von annotierten Kontrollflussgraphen zur Darstellung von HLS-Ein-und Ausgaben bei Verwendung pfadbasierter Einplanungsverfahren.MBMV51-601999Conference and Workshop Papersunavailableconf/mbmv/LockM99https://dblp.org/rec/conf/mbmv/LockM99URL#6539601Matthias MeixnerJürgen Becker 0001Thomas HollsteinManfred GlesnerObject-oriented Specification Approach for Synthesis of Hardware-/Software Systems.MBMV182-1911999Conference and Workshop Papersunavailableconf/mbmv/MeixnerBHG99https://dblp.org/rec/conf/mbmv/MeixnerBHG99URL#6539602Matthias MutzSebastian SteiblFormale Verifikation der Architekturverbesserung eines Viterbi Decoder IP Blocks.MBMV61-701999Conference and Workshop Papersunavailableconf/mbmv/MutzS99https://dblp.org/rec/conf/mbmv/MutzS99URL#6539603Jürgen RufThomas KropfModeling Real-Time Systems with I/O-Interval Structures.MBMV91-1001999Conference and Workshop Papersunavailableconf/mbmv/RufK99https://dblp.org/rec/conf/mbmv/RufK99URL#6539604Klaus Schneider 0001George LogothetisAbstraction of Systems with Counters for Symbolic Model Checking.MBMV31-401999Conference and Workshop Papersunavailableconf/mbmv/SchneiderL99https://dblp.org/rec/conf/mbmv/SchneiderL99URL#6539605Bernd StöhrUtz G. BaitingerEine neue Methode zur Spezifikation von komplexen Steuerwerken unter der Randbedingung der Synthese und eines kurzen Entwurfszyklus.MBMV21-301999Conference and Workshop Papersunavailableconf/mbmv/StohrB99https://dblp.org/rec/conf/mbmv/StohrB99URL#6539606Dirk ZiegenbeinKai Richter 0001Rolf ErnstLothar ThieleJürgen TeichSPI -- An Internal Representation for Heterogeneously Specified Embedded Systems.MBMV160-1691999Conference and Workshop Papersunavailableconf/mbmv/ZiegenbeinRETT99https://dblp.org/rec/conf/mbmv/ZiegenbeinRETT99URL#6539607Matthias MutzNikolaus LangeMethoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Braunschweig, Germany, February 22-24, 1999MBMVShaker1999Editorshipunavailableconf/mbmv/1999https://dblp.org/rec/conf/mbmv/1999URL#6550825Peter BlinzerUlrich GolzeUlrich HoltmannEntwurf von Controller-Schaltungen für Kommunikationsprotokolle mit dem Protocol-Compiler von Synopsys.MBMV50-581998Conference and Workshop Papersunavailableconf/mbmv/BlinzerGH98https://dblp.org/rec/conf/mbmv/BlinzerGH98URL#6604273Christian BlumenröhrDirk EisenbieglerDeriving Structural RT-Implementations from Algorithmic Descriptions by means of Logical Transformations.MBMV38-491998Conference and Workshop Papersunavailableconf/mbmv/BlumenrohrE98https://dblp.org/rec/conf/mbmv/BlumenrohrE98URL#6604274Markus BühlerD. DallmannUtz G. BaitingerSwitching Activity Analysis Using a Set Theoretical Approach.MBMV124-1301998Conference and Workshop Papersunavailableconf/mbmv/BuhlerDB98https://dblp.org/rec/conf/mbmv/BuhlerDB98URL#6604275Giuseppe Del CastilloWolfram HardtTowards a Unified Analysis Methodology of HW/SW Systems based on Abstract State Machines: Modelling of Instruction Sets.MBMV141-1501998Conference and Workshop Papersunavailableconf/mbmv/CastilloH98https://dblp.org/rec/conf/mbmv/CastilloH98URL#6604276Edelweis Helena Ache GarcezFrancisco Assis M. do NascimentoA Model Checker for a Partial Order based Model of Concurrency.MBMV95-1031998Conference and Workshop Papersunavailableconf/mbmv/GarcezN98https://dblp.org/rec/conf/mbmv/GarcezN98URL#6604277Joachim GerlachWolfgang RosenstielEine Umgebung zur transformationalen Entwurfsraum-Exploration.MBMV59-661998Conference and Workshop Papersunavailableconf/mbmv/GerlachR98https://dblp.org/rec/conf/mbmv/GerlachR98URL#6604278Christoph Grimm 0001Klaus WaldschmidtSpezifikation hybrider Systeme.MBMV1-101998Conference and Workshop Papersunavailableconf/mbmv/GrimmW98https://dblp.org/rec/conf/mbmv/GrimmW98URL#6604279Winfried GrünewaldKlaus Schneider 0001Modeling and Verifying Abstract Multithreaded Systems.MBMV85-941998Conference and Workshop Papersunavailableconf/mbmv/GrunewaldS98https://dblp.org/rec/conf/mbmv/GrunewaldS98URL#6604280Uwe KnöchelUlrich TannertJürgen HaufePeter SchwarzVerifikation nachrichtentechnischer Systeme mit Systemsimulation und HW/SW-Cosimulation.MBMV175-1841998Conference and Workshop Papersunavailableconf/mbmv/KnochelTHS98https://dblp.org/rec/conf/mbmv/KnochelTHS98URL#6604281Manfred KoegstGünter FrankeKlaus FeskeSteffen RülkeVerringerung der Leistungsaufnahme in sequentiellen Schaltungen durch Vorlogik und zweistufige Zustandskodierung.MBMV30-371998Conference and Workshop Papersunavailableconf/mbmv/KoegstFFR98https://dblp.org/rec/conf/mbmv/KoegstFFR98URL#6604282Thomas KropfJürgen RufKlaus Schneider 0001Markus WildA Synchronous Language for Modeling and Verifying Real Time and Embedded Systems.MBMV11-201998Conference and Workshop Papersunavailableconf/mbmv/KropfRSW98https://dblp.org/rec/conf/mbmv/KropfRSW98URL#6604283Nikolaus LangeMatthias MutzFormale Verifikation eines funktionalen VHDL Modells der J1850 Busarbitrierung.MBMV67-741998Conference and Workshop Papersunavailableconf/mbmv/LangeM98https://dblp.org/rec/conf/mbmv/LangeM98URL#6604284Thomas LockMichael MendlerFormale Modellierung von kontrollflussdominierten High-Level-Synthese-Eingabebeschreibungen zur Verifikation von Ergebnissen kontrollflussgesteuerter Einplanungsverfahren.MBMV75-841998Conference and Workshop Papersunavailableconf/mbmv/LockM98https://dblp.org/rec/conf/mbmv/LockM98URL#6604285Guido PostAndrea MüllerRainer SchoenenObject-Oriented Design of ATM Switch Hardware in a Telecommunication Network Simulation Environment.MBMV151-1641998Conference and Workshop Papersunavailableconf/mbmv/PostMS98https://dblp.org/rec/conf/mbmv/PostMS98URL#6604286Martin RadetzkiWolfram Putzke-RömingWolfgang NebelÜbersetzung von Objektorientiertem VHDL nach Standard VHDL.MBMV21-291998Conference and Workshop Papersunavailableconf/mbmv/RadetzkiPN98https://dblp.org/rec/conf/mbmv/RadetzkiPN98URL#6604287Stefan ReichörMarkus PfaffMarkus SchuttiIntegration externer Komponenten in den Simulationsablauf von VHDL.MBMV165-1741998Conference and Workshop Papersunavailableconf/mbmv/ReichorPS98https://dblp.org/rec/conf/mbmv/ReichorPS98URL#6604288Ingo SchreiberJens SchönherrEva FordranKlaus Schneider 0001Bernd StraubeKontrollfluss-Verifikation von Algorithmen mittels Modellprüfung.MBMV114-1231998Conference and Workshop Papersunavailableconf/mbmv/SchreiberSFSS98https://dblp.org/rec/conf/mbmv/SchreiberSFSS98URL#6604289Peter TholeWolfgang RosenstielProfilierung von VHDL-Prozessen mit minimierten Aufwand.MBMV131-1401998Conference and Workshop Papersunavailableconf/mbmv/TholeR98https://dblp.org/rec/conf/mbmv/TholeR98URL#6604290Markus WannemacherReiner LichteneckerWolfgang A. HalangEntwurfsmethode für einen universellen Koprozessor für zeitkritische Aufgaben in sicherheitsgerichteten Echtzeitsystemen.MBMV104-1131998Conference and Workshop Papersunavailableconf/mbmv/WannemacherLH98https://dblp.org/rec/conf/mbmv/WannemacherLH98URL#6604291Franz-Josef RammigWolfgang Müller 0003Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Paderborn, Germany, March 9-11, 1998MBMVHNI-Verlagsschriften1998Editorshipunavailableconf/mbmv/1998https://dblp.org/rec/conf/mbmv/1998URL#6615373