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"Advances in Automated Source-Level Debugging of Verilog Designs."

Bernhard Peischl, Naveed Riaz, Franz Wotawa (2008)

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DOI: 10.1007/978-3-540-79355-7_35

access: closed

type: Part in Book or Collection

metadata version: 2018-11-14

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  - https://dblp.org/rec/series/sci/PeischlRW08
Bernhard Peischl, Naveed Riaz, Franz Wotawa:
Advances in Automated Source-Level Debugging of Verilog Designs. New Challenges in Applied Intelligence Technologies 2008: 363-372

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