"Power-constrained aware and latency-aware microarchitectural optimizations ..."

Sudhanshu Shekhar Jha (2016)

> Home

Details and statistics

DOI: —

access: closed

type: Book or Thesis

metadata version: 2022-09-27

- view
  - electronic edition via handle.net
- export record
  dblp key:
  - phd/es/Jha16
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/phd/es/Jha16
Sudhanshu Shekhar Jha:
Power-constrained aware and latency-aware microarchitectural optimizations in many-core processors. Polytechnic University of Catalonia, Spain, 2016

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.