"Parallelisierung des Viterbi-Decoders: Algorithmus und VLSI-Architektur."

Gerhard P. Fettweis (1990)

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Gerhard P. Fettweis:
Parallelisierung des Viterbi-Decoders: Algorithmus und VLSI-Architektur. RWTH Aachen University, Germany, VDI-Verlag 1990, ISBN 978-3-18-144410-8, pp. 1-129

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