"Fault modeling, delay evaluation and path selection for delay test under ..."

Xiang Lu (2005)

> Home

Details and statistics

DOI: —

access: closed

type: Book or Thesis

metadata version: 2022-05-04

- view
  - electronic edition via handle.net
  authority control:
- export record
  dblp key:
  - phd/basesearch/Lu06
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/phd/basesearch/Lu06
Xiang Lu:
Fault modeling, delay evaluation and path selection for delay test under process variation in nano-scale VLSI circuits. Texas A&M University, College Station, USA, 2005

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.