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"Self Clock-Gating Scheme for Low Power Basic Logic Element Architecture."

R. Udaiyakumar et al. (2018)

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DOI: 10.1007/S11277-018-5385-2

access: closed

type: Journal Article

metadata version: 2021-10-14

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  - https://dblp.org/rec/journals/wpc/UdaiyakumarJSVM18
R. Udaiyakumar, Senoj Joseph, T. V. P. Sundararajan, Dhasarathan Vigneswaran, R. Maheswar, Iraj S. Amiri:
Self Clock-Gating Scheme for Low Power Basic Logic Element Architecture. Wirel. Pers. Commun. 102(4): 3477-3488 (2018)

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