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"Techniques for power estimation and optimization at the logic level: A survey."

José Monteiro, Srinivas Devadas (1996)

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DOI: 10.1007/BF01130409

access: closed

type: Journal Article

metadata version: 2022-02-23

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  - https://dblp.org/rec/journals/vlsisp/MonteiroD96
José Monteiro, Srinivas Devadas:
Techniques for power estimation and optimization at the logic level: A survey. J. VLSI Signal Process. 13(2-3): 259-276 (1996)

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