"Systolic architecture for the VLSI implementation of high-speed staged ..."

Giuseppe Caire et al. (1995)

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DOI: 10.1007/BF02407033

access: closed

type: Journal Article

metadata version: 2020-05-20

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  - https://dblp.org/rec/journals/vlsisp/CaireVHB95
Giuseppe Caire, Javier Ventura-Traveset, M. Hollreiser, Ezio Biglieri:
Systolic architecture for the VLSI implementation of high-speed staged decoders/quantizers. J. VLSI Signal Process. 10(2): 153-168 (1995)

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