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"Systolic architecture for the VLSI implementation of high-speed staged ..."
Giuseppe Caire et al. (1995)
- Giuseppe Caire, Javier Ventura-Traveset, M. Hollreiser, Ezio Biglieri:
Systolic architecture for the VLSI implementation of high-speed staged decoders/quantizers. J. VLSI Signal Process. 10(2): 153-168 (1995)
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