"Design of an Inter-plane Circuit for Clocked PLAs."

Chua-Chin Wang et al. (2002)

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DOI: 10.1080/10655140290011186

access: open

type: Journal Article

metadata version: 2023-05-08

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  - https://dblp.org/rec/journals/vlsi/WangHCC02
Chua-Chin Wang, Ya-Hsin Hsueh, Yu-Tsun Chien, Ying-Pei Chen:
Design of an Inter-plane Circuit for Clocked PLAs. VLSI Design 14(4): 373-381 (2002)

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