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"Performance and Wirability Driven Layout for Row-Based FPGAs."

Sudip Nag, Kaushik Roy (1998)

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DOI: 10.1155/1998/57380

access: open

type: Journal Article

metadata version: 2023-05-08

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  dblp key:
  - journals/vlsi/NagR98
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  - https://dblp.org/rec/journals/vlsi/NagR98
Sudip Nag, Kaushik Roy:
Performance and Wirability Driven Layout for Row-Based FPGAs. VLSI Design 7(4): 353-364 (1998)

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