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"High-speed VLSI architectures for the AES algorithm."

Xinmiao Zhang, Keshab K. Parhi (2004)

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DOI: 10.1109/TVLSI.2004.832943

access: closed

type: Journal Article

metadata version: 2024-05-07

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Xinmiao Zhang, Keshab K. Parhi:
High-speed VLSI architectures for the AES algorithm. IEEE Trans. Very Large Scale Integr. Syst. 12(9): 957-967 (2004)

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