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ORCID"Predicting Interconnect Delay for Physical Synthesis in a FPGA CAD Flow."
Valavan Manohararajah et al. (2007)
- Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh
, Stephen Dean Brown:
Predicting Interconnect Delay for Physical Synthesis in a FPGA CAD Flow. IEEE Trans. Very Large Scale Integr. Syst. 15(8): 895-903 (2007)
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