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"A Reconfigurable Clock Polarity Assignment Flow for Clock Gated Designs."

Jianchao Lu, Ying Teng, Baris Taskin (2012)

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DOI: 10.1109/TVLSI.2011.2147339

access: closed

type: Journal Article

metadata version: 2020-03-11

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  - https://dblp.org/rec/journals/tvlsi/LuTT12
Jianchao Lu, Ying Teng, Baris Taskin:
A Reconfigurable Clock Polarity Assignment Flow for Clock Gated Designs. IEEE Trans. Very Large Scale Integr. Syst. 20(6): 1002-1011 (2012)

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