"RISC-V CPU Design Using RRAM-CMOS Standard Cells."

Markus Fritscher et al. (2025)

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DOI: 10.1109/TVLSI.2025.3554476

access: open

type: Journal Article

metadata version: 2025-11-02

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Markus Fritscher, Max Uhlmann, Philip Ostrovskyy, Daniel Reiser, Junchao Chen, Jianan Wen, Carsten Schulze, Gerhard Kahmen, Dietmar Fey, Marc Reichenbach, Milos Krstic, Christian Wenger:
RISC-V CPU Design Using RRAM-CMOS Standard Cells. IEEE Trans. Very Large Scale Integr. Syst. 33(9): 2406-2414 (2025)

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