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"Load-balanced clock tree synthesis with adjustable delay buffer insertion ..."
Kuan-Yu Lin et al. (2012)
- Kuan-Yu Lin, Hong-Ting Lin, Tsung-Yi Ho
, Chia-Chun Tsai:
Load-balanced clock tree synthesis with adjustable delay buffer insertion for clock skew reduction in multiple dynamic supply voltage designs. ACM Trans. Design Autom. Electr. Syst. 17(3): 34:1-34:22 (2012)
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