"Improved Design for Hardware Implementation of Graph-Based Large Margin ..."

Janier Arias-Garcia et al. (2024)

> Home

Details and statistics

DOI: 10.1109/TNNLS.2022.3183236

access: closed

type: Journal Article

metadata version: 2024-01-26

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/tnn/AriasGarciaSGMCCTB24
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tnn/AriasGarciaSGMCCTB24
Janier Arias-Garcia, Alan Cândido de Souza, Liliane Gade, Jones Yudi Mori, Frederico Coelho, Cristiano Leite Castro, Luiz C. B. Torres, Antônio P. Braga:
Improved Design for Hardware Implementation of Graph-Based Large Margin Classifiers for Embedded Edge Computing. IEEE Trans. Neural Networks Learn. Syst. 35(1): 1320-1329 (2024)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.