"An 8.5-ps Two-Stage Vernier Delay-Line Loop Shrinking Time-to-Digital ..."

Jie Zhang, Dongming Zhou (2018)

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DOI: 10.1109/TIM.2017.2769239

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type: Journal Article

metadata version: 2020-06-08

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Jie Zhang, Dongming Zhou:
An 8.5-ps Two-Stage Vernier Delay-Line Loop Shrinking Time-to-Digital Converter in 130-nm Flash FPGA. IEEE Trans. Instrum. Meas. 67(2): 406-414 (2018)

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