Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"Real-Time Visual Saliency Architecture for FPGA With Top-Down Attention ..."

Francisco Barranco et al. (2014)

> Home

Details and statistics

DOI: 10.1109/TII.2014.2319581

access: closed

type: Journal Article

metadata version: 2020-11-10

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/tii/BarrancoDPR14
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tii/BarrancoDPR14
Francisco Barranco, Javier Díaz, Begoña del Pino, Eduardo Ros:
Real-Time Visual Saliency Architecture for FPGA With Top-Down Attention Modulation. IEEE Trans. Ind. Informatics 10(3): 1726-1735 (2014)

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.