"Performance and Area Trade-Off of 3D-Stacked DRAM Based Chip ..."

Rakesh Pandey, Aryabartta Sahu (2021)

> Home

Details and statistics

DOI: 10.1109/TETC.2019.2946887

access: closed

type: Journal Article

metadata version: 2021-12-15

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/tetc/PandeyS21
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tetc/PandeyS21
Rakesh Pandey, Aryabartta Sahu:
Performance and Area Trade-Off of 3D-Stacked DRAM Based Chip Multiprocessor with Hybrid Interconnect. IEEE Trans. Emerg. Top. Comput. 9(4): 1945-1959 (2021)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.