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"Efficient ASIC Architecture for Low Latency Classic McEliece Decoding."

Daniel Fallnich et al. (2024)

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DOI: 10.46586/TCHES.V2024.I2.403-425

access: open

type: Journal Article

metadata version: 2024-06-08

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  - https://dblp.org/rec/journals/tches/FallnichLZG24
Daniel Fallnich, Christian Lanius, Shutao Zhang, Tobias Gemmeke:
Efficient ASIC Architecture for Low Latency Classic McEliece Decoding. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2024(2): 403-425 (2024)

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