"A SRAM-Based In-Memory Accelerator Featuring Complete SAT Solving and CAM ..."

Jinrong Zhou et al. (2025)

> Home

Details and statistics

DOI: 10.1109/TCSII.2025.3616326

access: closed

type: Journal Article

metadata version: 2025-12-07

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/tcasII/ZhouLZFC25
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tcasII/ZhouLZFC25
Jinrong Zhou, Renlong Li, Yifeng Zhou, Qiaoyi Fu, Zhuojun Chen:
A SRAM-Based In-Memory Accelerator Featuring Complete SAT Solving and CAM Operations for Efficient Network Transmission. IEEE Trans. Circuits Syst. II Express Briefs 72(11): 1785-1789 (2025)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.