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"Efficient FPGA-implementation of two's complement digit-serial/parallel ..."

Javier Valls, Eduardo I. Boemo (2003)

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DOI: 10.1109/TCSII.2003.811438

access: closed

type: Journal Article

metadata version: 2021-07-25

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Javier Valls, Eduardo I. Boemo:
Efficient FPGA-implementation of two's complement digit-serial/parallel multipliers. IEEE Trans. Circuits Syst. II Express Briefs 50(6): 317-322 (2003)

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