"A Capacitive Computing-In-Memory Circuit With Low Input Loading SRAM ..."

Eunhwan Kim et al. (2023)

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DOI: 10.1109/TCSII.2023.3266239

access: closed

type: Journal Article

metadata version: 2023-09-14

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Eunhwan Kim, Hyunmyung Oh, Nameun Kang, Jihoon Park, Jae-Joon Kim:
A Capacitive Computing-In-Memory Circuit With Low Input Loading SRAM Bitcell and Adjustable ADC Input Range. IEEE Trans. Circuits Syst. II Express Briefs 70(9): 3268-3272 (2023)

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