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"A High-Performance Core Micro-Architecture Based on RISC-V ISA for Low ..."

Satyajit Bora, Roy Paily (2021)

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DOI: 10.1109/TCSII.2020.3043204

access: closed

type: Journal Article

metadata version: 2021-06-15

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Satyajit Bora, Roy Paily:
A High-Performance Core Micro-Architecture Based on RISC-V ISA for Low Power Applications. IEEE Trans. Circuits Syst. II Express Briefs 68(6): 2132-2136 (2021)

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