Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"Parallel Balanced-Bit-Serial Design Technique for Ultra-Low-Voltage ..."

Bing-Chen Wu, I-Chyn Wey (2018)

> Home

Details and statistics

DOI: 10.1109/TCSI.2017.2719283

access: closed

type: Journal Article

metadata version: 2020-05-22

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/tcas/WuW18
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tcas/WuW18
Bing-Chen Wu, I-Chyn Wey:
Parallel Balanced-Bit-Serial Design Technique for Ultra-Low-Voltage Circuits With Energy Saving and Area Efficiency Enhancement. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(1): 141-153 (2018)

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.