"90 nm 32 times 32 bit Tunneling SRAM Memory Array With 0.5 ns Write Access ..."

Anisha Ramesh, Si-Young Park, Paul R. Berger (2011)

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DOI: 10.1109/TCSI.2011.2123630

access: closed

type: Journal Article

metadata version: 2020-05-22

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Anisha Ramesh, Si-Young Park, Paul R. Berger:
90 nm 32 times 32 bit Tunneling SRAM Memory Array With 0.5 ns Write Access Time, 1 ns Read Access Time and 0.5 V Operation. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(10): 2432-2445 (2011)

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